Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	27743	1			T1	12		T2	18		T3	5
auto[PWRUP]	119	1			T47	1		T58	3		T60	1
auto[ONEST_0]	86	1			T56	1		T58	3		T59	1
auto[ONEST_021]	15	1			T58	2		T60	1		T61	1
auto[ONEST_1]	76	1			T48	1		T58	2		T59	3
auto[ONEST_DONE]	2	1			T235	1		T236	1		-	-
auto[LP_0]	110	1			T47	1		T56	4		T58	2
auto[LP_021]	25	1			T237	1		T235	2		T238	1
auto[LP_1]	142	1			T56	3		T58	1		T60	3
auto[LP_EVAL]	65	1			T60	1		T59	1		T49	1
auto[LP_SLP]	513	1			T47	4		T56	5		T58	12
auto[LP_PWRUP]	24	1			T58	1		T59	2		T49	1
auto[NP_0]	174	1			T56	2		T48	1		T58	3
auto[NP_021]	33	1			T58	1		T59	1		T52	1
auto[NP_1]	135	1			T12	1		T47	1		T60	1
auto[NP_EVAL]	26	1			T49	1		T239	1		T237	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

5

1

T59

1

T239

1

T240

1

min

27195

1

T1

12

T2

18

T3

5

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27203	1			T1	12		T2	18		T3	5
pow[0x1]	3	1			T241	1		T242	1		T243	1
pow[0x2]	13	1			T58	1		T237	1		T61	1
pow[0x3]	32	1			T56	1		T58	1		T59	1
pow[0x4]	69	1			T47	1		T56	1		T58	1
pow[0x5]	134	1			T12	2		T56	3		T60	1
pow[0x6]	256	1			T56	1		T48	1		T58	2
pow[0x7]	540	1			T15	1		T47	3		T56	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

190

1

T15

1

T47

1

T56

2

min

26713

1

T1

12

T2

18

T3

5

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x6]	0	1	1
pow[0x7]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	26713	1			T1	12		T2	18		T3	5
pow[0x1]	1	1			T244	1		-	-		-	-
pow[0x4]	1	1			T245	1		-	-		-	-
pow[0x5]	2	1			T201	1		T246	1		-	-
pow[0x8]	7	1			T32	1		T247	1		T248	2
pow[0x9]	10	1			T239	1		T249	1		T250	1
pow[0xa]	23	1			T56	1		T58	1		T60	1
pow[0xb]	29	1			T56	1		T58	1		T237	1
pow[0xc]	56	1			T60	1		T49	1		T239	1
pow[0xd]	147	1			T12	1		T47	1		T56	1
pow[0xe]	301	1			T15	1		T47	1		T56	4
pow[0xf]	633	1			T47	4		T56	3		T58	11