Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	0	17	100.00	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	0	17	100.00

Automatically Generated Bins for fsm_state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2287	1			T1	4		T8	6		T10	4
auto[PWRUP]	149	1			T56	5		T58	1		T60	3
auto[ONEST_0]	59	1			T48	1		T49	2		T51	1
auto[ONEST_021]	15	1			T238	1		T369	1		T240	1
auto[ONEST_1]	95	1			T47	2		T60	1		T59	2
auto[ONEST_DONE]	4	1			T237	1		T36	1		T370	1
auto[LP_0]	139	1			T47	1		T56	2		T58	2
auto[LP_021]	25	1			T15	1		T47	2		T56	1
auto[LP_1]	145	1			T12	1		T47	1		T58	3
auto[LP_EVAL]	66	1			T47	4		T56	2		T58	1
auto[LP_SLP]	528	1			T12	1		T15	1		T47	1
auto[LP_PWRUP]	41	1			T56	2		T239	1		T37	1
auto[NP_0]	255	1			T8	1		T12	1		T15	1
auto[NP_021]	56	1			T15	3		T59	2		T54	2
auto[NP_1]	222	1			T8	1		T12	4		T15	2
auto[NP_EVAL]	34	1			T47	2		T56	1		T201	1
auto[NP_DONE]	1	1			T371	1		-	-		-	-

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

11

1

T60

1

T59

1

T201

1

min

2005

1

T1

4

T8

8

T10

4

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	2013	1			T1	4		T8	8		T10	4
pow[0x1]	17	1			T15	1		T58	1		T49	1
pow[0x2]	16	1			T60	1		T52	1		T53	1
pow[0x3]	30	1			T15	1		T51	1		T173	1
pow[0x4]	59	1			T56	1		T58	1		T52	1
pow[0x5]	115	1			T47	1		T56	4		T58	1
pow[0x6]	293	1			T12	2		T15	1		T47	2
pow[0x7]	533	1			T12	1		T15	1		T47	10

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

195

1

T47

5

T56

3

T48

1

min

1346

1

T1

4

T8

6

T10

4

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1354	1			T1	4		T8	6		T10	4
pow[0x1]	9	1			T47	1		T53	1		T37	1
pow[0x2]	44	1			T15	2		T49	4		T52	4
pow[0x3]	55	1			T8	2		T12	3		T15	3
pow[0x4]	61	1			T15	1		T47	1		T48	3
pow[0x6]	2	1			T372	1		T373	1		-	-
pow[0x7]	4	1			T374	1		T375	1		T376	1
pow[0x8]	2	1			T316	1		T377	1		-	-
pow[0x9]	9	1			T239	1		T100	1		T240	1
pow[0xa]	21	1			T173	1		T239	1		T378	1
pow[0xb]	40	1			T58	1		T60	2		T49	1
pow[0xc]	76	1			T15	1		T56	1		T58	2
pow[0xd]	145	1			T15	1		T47	1		T56	2
pow[0xe]	265	1			T47	1		T56	4		T58	1
pow[0xf]	610	1			T12	1		T15	1		T47	6