Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2672	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2796	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2778	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2624	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2662	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2521	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2453	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2657	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2742	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2906	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2580	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2550	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2527	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2610	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2511	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2763	0	0
adc_en_ctl_rd_A	2147483647	2397	0	0
adc_fsm_rst_rd_A	2147483647	2002	0	0
adc_intr_ctl_rd_A	2147483647	2550	0	0
adc_lp_sample_ctl_rd_A	2147483647	2193	0	0
adc_pd_ctl_rd_A	2147483647	2307	0	0
adc_sample_ctl_rd_A	2147483647	2091	0	0
adc_wakeup_ctl_rd_A	2147483647	2060	0	0
intr_enable_rd_A	2147483647	2663	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2672	0	0
T20	307050	14	0	0
T21	0	2	0	0
T22	0	4	0	0
T23	0	41	0	0
T24	0	16	0	0
T25	0	35	0	0
T26	0	37	0	0
T27	0	28	0	0
T28	0	52	0	0
T29	0	7	0	0
T30	969536	0	0	0
T31	427288	0	0	0
T32	549373	0	0	0
T33	82583	0	0	0
T34	118589	0	0	0
T35	328469	0	0	0
T36	485358	0	0	0
T37	411112	0	0	0
T38	553733	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2796	0	0
T20	307050	18	0	0
T21	0	7	0	0
T22	0	8	0	0
T23	0	21	0	0
T24	0	20	0	0
T25	0	39	0	0
T26	0	37	0	0
T27	0	15	0	0
T28	0	29	0	0
T30	969536	0	0	0
T31	427288	0	0	0
T32	549373	0	0	0
T33	82583	0	0	0
T34	118589	0	0	0
T35	328469	0	0	0
T36	485358	0	0	0
T37	411112	0	0	0
T38	553733	0	0	0
T39	0	18	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2778	0	0
T20	307050	24	0	0
T21	0	10	0	0
T22	0	5	0	0
T23	0	40	0	0
T24	0	16	0	0
T25	0	26	0	0
T26	0	32	0	0
T27	0	19	0	0
T28	0	22	0	0
T29	0	2	0	0
T30	969536	0	0	0
T31	427288	0	0	0
T32	549373	0	0	0
T33	82583	0	0	0
T34	118589	0	0	0
T35	328469	0	0	0
T36	485358	0	0	0
T37	411112	0	0	0
T38	553733	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2624	0	0
T20	307050	20	0	0
T21	0	13	0	0
T22	0	13	0	0
T23	0	42	0	0
T24	0	33	0	0
T25	0	23	0	0
T26	0	32	0	0
T27	0	20	0	0
T28	0	47	0	0
T30	969536	0	0	0
T31	427288	0	0	0
T32	549373	0	0	0
T33	82583	0	0	0
T34	118589	0	0	0
T35	328469	0	0	0
T36	485358	0	0	0
T37	411112	0	0	0
T38	553733	0	0	0
T39	0	24	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2662	0	0
T20	307050	17	0	0
T21	0	2	0	0
T22	0	1	0	0
T23	0	47	0	0
T24	0	13	0	0
T25	0	24	0	0
T26	0	34	0	0
T27	0	11	0	0
T28	0	22	0	0
T29	0	7	0	0
T30	969536	0	0	0
T31	427288	0	0	0
T32	549373	0	0	0
T33	82583	0	0	0
T34	118589	0	0	0
T35	328469	0	0	0
T36	485358	0	0	0
T37	411112	0	0	0
T38	553733	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2521	0	0
T20	307050	15	0	0
T21	0	10	0	0
T22	0	15	0	0
T23	0	35	0	0
T24	0	13	0	0
T25	0	40	0	0
T26	0	30	0	0
T27	0	24	0	0
T28	0	24	0	0
T30	969536	0	0	0
T31	427288	0	0	0
T32	549373	0	0	0
T33	82583	0	0	0
T34	118589	0	0	0
T35	328469	0	0	0
T36	485358	0	0	0
T37	411112	0	0	0
T38	553733	0	0	0
T39	0	7	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2453	0	0
T20	307050	18	0	0
T21	0	23	0	0
T22	0	19	0	0
T23	0	38	0	0
T24	0	11	0	0
T25	0	10	0	0
T26	0	33	0	0
T27	0	15	0	0
T28	0	42	0	0
T29	0	4	0	0
T30	969536	0	0	0
T31	427288	0	0	0
T32	549373	0	0	0
T33	82583	0	0	0
T34	118589	0	0	0
T35	328469	0	0	0
T36	485358	0	0	0
T37	411112	0	0	0
T38	553733	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2657	0	0
T20	307050	9	0	0
T21	0	7	0	0
T22	0	13	0	0
T23	0	48	0	0
T24	0	13	0	0
T25	0	43	0	0
T26	0	30	0	0
T27	0	23	0	0
T28	0	46	0	0
T29	0	7	0	0
T30	969536	0	0	0
T31	427288	0	0	0
T32	549373	0	0	0
T33	82583	0	0	0
T34	118589	0	0	0
T35	328469	0	0	0
T36	485358	0	0	0
T37	411112	0	0	0
T38	553733	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2742	0	0
T20	307050	22	0	0
T21	0	11	0	0
T22	0	23	0	0
T23	0	33	0	0
T24	0	21	0	0
T25	0	36	0	0
T26	0	35	0	0
T27	0	9	0	0
T28	0	56	0	0
T29	0	2	0	0
T30	969536	0	0	0
T31	427288	0	0	0
T32	549373	0	0	0
T33	82583	0	0	0
T34	118589	0	0	0
T35	328469	0	0	0
T36	485358	0	0	0
T37	411112	0	0	0
T38	553733	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2906	0	0
T20	307050	10	0	0
T21	0	9	0	0
T22	0	18	0	0
T23	0	69	0	0
T24	0	21	0	0
T25	0	31	0	0
T26	0	39	0	0
T27	0	8	0	0
T28	0	68	0	0
T29	0	8	0	0
T30	969536	0	0	0
T31	427288	0	0	0
T32	549373	0	0	0
T33	82583	0	0	0
T34	118589	0	0	0
T35	328469	0	0	0
T36	485358	0	0	0
T37	411112	0	0	0
T38	553733	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2580	0	0
T20	307050	5	0	0
T21	0	4	0	0
T22	0	21	0	0
T23	0	47	0	0
T24	0	14	0	0
T25	0	19	0	0
T26	0	30	0	0
T27	0	27	0	0
T28	0	74	0	0
T29	0	9	0	0
T30	969536	0	0	0
T31	427288	0	0	0
T32	549373	0	0	0
T33	82583	0	0	0
T34	118589	0	0	0
T35	328469	0	0	0
T36	485358	0	0	0
T37	411112	0	0	0
T38	553733	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2550	0	0
T20	307050	18	0	0
T21	0	13	0	0
T22	0	8	0	0
T23	0	35	0	0
T24	0	13	0	0
T25	0	30	0	0
T26	0	33	0	0
T27	0	24	0	0
T28	0	33	0	0
T30	969536	0	0	0
T31	427288	0	0	0
T32	549373	0	0	0
T33	82583	0	0	0
T34	118589	0	0	0
T35	328469	0	0	0
T36	485358	0	0	0
T37	411112	0	0	0
T38	553733	0	0	0
T39	0	9	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2527	0	0
T20	307050	24	0	0
T21	0	15	0	0
T22	0	16	0	0
T23	0	51	0	0
T24	0	14	0	0
T25	0	19	0	0
T26	0	35	0	0
T27	0	19	0	0
T28	0	38	0	0
T30	969536	0	0	0
T31	427288	0	0	0
T32	549373	0	0	0
T33	82583	0	0	0
T34	118589	0	0	0
T35	328469	0	0	0
T36	485358	0	0	0
T37	411112	0	0	0
T38	553733	0	0	0
T39	0	11	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2610	0	0
T20	307050	21	0	0
T21	0	12	0	0
T22	0	17	0	0
T23	0	45	0	0
T24	0	22	0	0
T25	0	18	0	0
T26	0	39	0	0
T27	0	23	0	0
T28	0	47	0	0
T30	969536	0	0	0
T31	427288	0	0	0
T32	549373	0	0	0
T33	82583	0	0	0
T34	118589	0	0	0
T35	328469	0	0	0
T36	485358	0	0	0
T37	411112	0	0	0
T38	553733	0	0	0
T39	0	9	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2511	0	0
T20	307050	12	0	0
T21	0	4	0	0
T22	0	17	0	0
T23	0	39	0	0
T24	0	6	0	0
T25	0	17	0	0
T26	0	37	0	0
T27	0	26	0	0
T28	0	50	0	0
T30	969536	0	0	0
T31	427288	0	0	0
T32	549373	0	0	0
T33	82583	0	0	0
T34	118589	0	0	0
T35	328469	0	0	0
T36	485358	0	0	0
T37	411112	0	0	0
T38	553733	0	0	0
T39	0	10	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2763	0	0
T20	307050	29	0	0
T21	0	15	0	0
T22	0	15	0	0
T23	0	52	0	0
T24	0	16	0	0
T25	0	14	0	0
T26	0	28	0	0
T27	0	17	0	0
T28	0	20	0	0
T29	0	10	0	0
T30	969536	0	0	0
T31	427288	0	0	0
T32	549373	0	0	0
T33	82583	0	0	0
T34	118589	0	0	0
T35	328469	0	0	0
T36	485358	0	0	0
T37	411112	0	0	0
T38	553733	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2397	0	0
T20	307050	25	0	0
T21	0	16	0	0
T22	0	11	0	0
T23	0	40	0	0
T24	0	19	0	0
T25	0	11	0	0
T26	0	33	0	0
T27	0	16	0	0
T28	0	37	0	0
T30	969536	0	0	0
T31	427288	0	0	0
T32	549373	0	0	0
T33	82583	0	0	0
T34	118589	0	0	0
T35	328469	0	0	0
T36	485358	0	0	0
T37	411112	0	0	0
T38	553733	0	0	0
T39	0	13	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2002	0	0
T20	307050	19	0	0
T21	0	8	0	0
T22	0	7	0	0
T23	0	51	0	0
T24	0	17	0	0
T25	0	30	0	0
T26	0	36	0	0
T27	0	10	0	0
T28	0	24	0	0
T30	969536	0	0	0
T31	427288	0	0	0
T32	549373	0	0	0
T33	82583	0	0	0
T34	118589	0	0	0
T35	328469	0	0	0
T36	485358	0	0	0
T37	411112	0	0	0
T38	553733	0	0	0
T39	0	5	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2550	0	0
T20	307050	20	0	0
T21	0	5	0	0
T22	0	9	0	0
T23	0	59	0	0
T24	0	13	0	0
T25	0	44	0	0
T26	0	50	0	0
T27	0	23	0	0
T28	0	27	0	0
T29	0	4	0	0
T30	969536	0	0	0
T31	427288	0	0	0
T32	549373	0	0	0
T33	82583	0	0	0
T34	118589	0	0	0
T35	328469	0	0	0
T36	485358	0	0	0
T37	411112	0	0	0
T38	553733	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2193	0	0
T20	307050	24	0	0
T21	0	7	0	0
T22	0	18	0	0
T23	0	38	0	0
T24	0	5	0	0
T25	0	32	0	0
T26	0	25	0	0
T27	0	26	0	0
T28	0	22	0	0
T30	969536	0	0	0
T31	427288	0	0	0
T32	549373	0	0	0
T33	82583	0	0	0
T34	118589	0	0	0
T35	328469	0	0	0
T36	485358	0	0	0
T37	411112	0	0	0
T38	553733	0	0	0
T39	0	7	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2307	0	0
T20	307050	22	0	0
T21	0	11	0	0
T22	0	5	0	0
T23	0	29	0	0
T24	0	30	0	0
T25	0	22	0	0
T26	0	29	0	0
T27	0	8	0	0
T28	0	29	0	0
T29	0	8	0	0
T30	969536	0	0	0
T31	427288	0	0	0
T32	549373	0	0	0
T33	82583	0	0	0
T34	118589	0	0	0
T35	328469	0	0	0
T36	485358	0	0	0
T37	411112	0	0	0
T38	553733	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2091	0	0
T20	307050	32	0	0
T21	0	17	0	0
T22	0	13	0	0
T23	0	31	0	0
T24	0	9	0	0
T25	0	27	0	0
T26	0	21	0	0
T27	0	26	0	0
T28	0	28	0	0
T30	969536	0	0	0
T31	427288	0	0	0
T32	549373	0	0	0
T33	82583	0	0	0
T34	118589	0	0	0
T35	328469	0	0	0
T36	485358	0	0	0
T37	411112	0	0	0
T38	553733	0	0	0
T39	0	7	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2060	0	0
T20	307050	16	0	0
T22	0	1	0	0
T23	0	52	0	0
T24	0	7	0	0
T25	0	49	0	0
T26	0	12	0	0
T27	0	19	0	0
T28	0	14	0	0
T30	969536	0	0	0
T31	427288	0	0	0
T32	549373	0	0	0
T33	82583	0	0	0
T34	118589	0	0	0
T35	328469	0	0	0
T36	485358	0	0	0
T37	411112	0	0	0
T38	553733	0	0	0
T39	0	11	0	0
T40	0	20	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2663	0	0
T10	197904	1	0	0
T11	171851	0	0	0
T12	100331	0	0	0
T15	615995	0	0	0
T18	808952	0	0	0
T19	57123	0	0	0
T20	0	57	0	0
T21	0	26	0	0
T22	0	5	0	0
T23	0	71	0	0
T24	0	21	0	0
T25	0	56	0	0
T41	0	18	0	0
T42	0	10	0	0
T43	0	41	0	0
T44	19478	0	0	0
T45	12540	0	0	0
T46	161797	0	0	0
T47	558257	0	0	0