Module Definition
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Module : prim_reg_cdc_arb
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.04 100.00 96.51 95.65 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb 77.58 95.65 78.95 85.71 50.00
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb 83.73 90.00 66.67 78.26 100.00
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb 83.73 90.00 66.67 78.26 100.00
tb.dut.u_reg.u_filter_status_cdc.u_arb 97.72 100.00 95.24 95.65 100.00
tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb 100.00 100.00 100.00

Line Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=2,ResetVal=0,DstWrReq=0 + DataWidth=32,ResetVal,DstWrReq=0 + DataWidth=8,ResetVal=4,DstWrReq=0 + DataWidth=16,ResetVal=155,DstWrReq=0 + DataWidth=1,ResetVal=0,DstWrReq=0 + DataWidth=9,ResetVal=0,DstWrReq=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb

Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN28411100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN30000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 1 1
284 1 1
285 1 1
300 unreachable

Line Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=28,ResetVal=0,DstWrReq=1 + DataWidth=9,ResetVal=0,DstWrReq=1 + DataWidth=5,ResetVal=0,DstWrReq=1 )
Line Coverage for Module self-instances :
SCORELINE
83.73 90.00
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb

SCORELINE
83.73 90.00
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb

SCORELINE
97.72 100.00
tb.dut.u_reg.u_filter_status_cdc.u_arb

SCORELINE
77.58 95.65
tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb

Line No.TotalCoveredPercent
TOTAL5050100.00
CONT_ASSIGN10011100.00
ALWAYS11233100.00
ALWAYS12266100.00
CONT_ASSIGN13611100.00
ALWAYS14066100.00
ALWAYS1561010100.00
CONT_ASSIGN18411100.00
ALWAYS1881919100.00
CONT_ASSIGN22911100.00
CONT_ASSIGN24411100.00
CONT_ASSIGN24511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 1 1
112 1 1
113 1 1
115 1 1
122 1 1
123 1 1
124 1 1
129 1 1
130 1 1
133 1 1
MISSING_ELSE
136 1 1
140 1 1
141 1 1
142 1 1
143 1 1
144 1 1
145 1 1
MISSING_ELSE
156 1 1
157 1 1
158 1 1
159 1 1
160 1 1
161 1 1
162 1 1
163 1 1
164 1 1
165 1 1
MISSING_ELSE
184 1 1
188 1 1
189 1 1
193 1 1
194 1 1
196 1 1
198 1 1
200 1 1
201 1 1
203 1 1
204 1 1
205 1 1
206 1 1
207 1 1
208 1 1
211 1 1
212 1 1
MISSING_ELSE
217 1 1
218 1 1
219 1 1
MISSING_ELSE
229 1 1
244 1 1
245 1 1

Cond Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=2,ResetVal=0,DstWrReq=0 + DataWidth=32,ResetVal,DstWrReq=0 + DataWidth=8,ResetVal=4,DstWrReq=0 + DataWidth=16,ResetVal=155,DstWrReq=0 + DataWidth=1,ResetVal=0,DstWrReq=0 + DataWidth=9,ResetVal=0,DstWrReq=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb

TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T4
10Unreachable
11Unreachable 

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T4
Cond Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=28,ResetVal=0,DstWrReq=1 + DataWidth=9,ResetVal=0,DstWrReq=1 + DataWidth=5,ResetVal=0,DstWrReq=1 )
Cond Coverage for Module self-instances :
SCORECOND
83.73 66.67
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb

SCORECOND
83.73 66.67
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb

SCORECOND
97.72 95.24
tb.dut.u_reg.u_filter_status_cdc.u_arb

SCORECOND
77.58 78.95
tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb

TotalCoveredPercent
Conditions434093.02
Logical434093.02
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T2,T3 

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T3 

 LINE       124
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT68,T69,T70
11CoveredT68,T69,T70 

 LINE       130
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110CoveredT1,T2,T5
111CoveredT68,T69,T70 

 LINE       136
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T5
10CoveredT68,T69,T70 

 LINE       158
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       160
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT68,T69,T70
11CoveredT1,T2,T5 

 LINE       162
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T4
11CoveredT1,T2,T3 

 LINE       184
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------
-1--2-StatusTests
01CoveredT68,T69,T70
10CoveredT1,T2,T4
11CoveredT1,T2,T5 

 LINE       208
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T5 

 LINE       229
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------
-1--2--3-StatusTests
000CoveredT1,T2,T4
001CoveredT1,T2,T5
010CoveredT1,T2,T3
100CoveredT1,T2,T3 

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T5 

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T4 

 LINE       245
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T5
11CoveredT1,T2,T3 

 LINE       245
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T3
Branch Coverage for Module : prim_reg_cdc_arb
Line No.TotalCoveredPercent
Branches 23 22 95.65
IF 112 2 2 100.00
IF 122 4 4 100.00
IF 140 4 4 100.00
IF 156 6 6 100.00
CASE 198 7 6 85.71

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	112	if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4 



	LineNo.	Expression
-1-:	122	if ((!rst_dst_ni))
-2-:	124	if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d))
-3-:	130	if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T4
0 1 - Covered T68,T69,T70
0 0 1 Covered T68,T69,T70
0 0 0 Covered T1,T2,T4 



	LineNo.	Expression
-1-:	140	if ((!rst_dst_ni))
-2-:	142	if (gen_wr_req.dst_lat_d)
-3-:	144	if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T4
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T5
0 0 0 Covered T1,T2,T4 



	LineNo.	Expression
-1-:	156	if ((!rst_dst_ni))
-2-:	158	if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack))
-3-:	160	if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d))
-4-:	162	if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d))
-5-:	164	if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T4
0 1 - - - Covered T1,T2,T3
0 0 1 - - Covered T1,T2,T5
0 0 0 1 - Covered T1,T2,T3
0 0 0 0 1 Covered T1,T2,T5
0 0 0 0 0 Covered T1,T2,T4 



	LineNo.	Expression
-1-:	198	case (gen_wr_req.state_q)
-2-:	201	if (gen_wr_req.dst_req)
-3-:	205	if (dst_update)
-4-:	208	if ((dst_qs_o != dst_qs_i))
-5-:	218	if (gen_wr_req.dst_update_ack)

Branches:
-1--2--3--4--5-StatusTests
StIdle 1 - - - Covered T1,T2,T5
StIdle 0 1 - - Covered T1,T2,T3
StIdle 0 0 1 - Covered T1,T2,T5
StIdle 0 0 0 - Covered T1,T2,T4
StWait - - - 1 Covered T1,T2,T3
StWait - - - 0 Covered T1,T2,T3
default - - - - Not Covered

Assert Coverage for Module : prim_reg_cdc_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_wr_req.DstUpdateReqCheck_A 141843860 1298814 0 3680
gen_wr_req.HwIdSelCheck_A 141843860 4597541 0 0


gen_wr_req.DstUpdateReqCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 141843860 1298814 0 3680
T1 205209 2807 0 3
T2 305673 4276 0 3
T3 55047 382 0 3
T4 5343 0 0 3
T5 97989 1411 0 3
T6 96183 1359 0 3
T7 63102 434 0 3
T8 99291 1402 0 3
T9 295914 4230 0 3
T10 0 4226 0 0
T11 0 2813 0 0
T12 0 61 0 0
T13 300 0 0 3

gen_wr_req.HwIdSelCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 141843860 4597541 0 0
T1 273612 9758 0 0
T2 407564 14731 0 0
T3 73396 1415 0 0
T4 7124 0 0 0
T5 130652 4763 0 0
T6 128244 4645 0 0
T7 84136 1643 0 0
T8 132388 4784 0 0
T9 394552 14368 0 0
T10 0 14223 0 0
T11 0 9637 0 0
T12 0 61 0 0
T13 400 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%