Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2784	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2456	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2353	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2317	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2362	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2517	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2381	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2389	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2291	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2508	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2456	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2235	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2423	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2302	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2677	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2374	0	0
adc_en_ctl_rd_A	2147483647	2197	0	0
adc_fsm_rst_rd_A	2147483647	1720	0	0
adc_intr_ctl_rd_A	2147483647	2241	0	0
adc_lp_sample_ctl_rd_A	2147483647	1779	0	0
adc_pd_ctl_rd_A	2147483647	2164	0	0
adc_sample_ctl_rd_A	2147483647	1905	0	0
adc_wakeup_ctl_rd_A	2147483647	2176	0	0
intr_enable_rd_A	2147483647	2750	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2784	0	0
T14	151756	22	0	0
T15	0	44	0	0
T16	0	8	0	0
T17	0	41	0	0
T18	0	44	0	0
T19	0	44	0	0
T20	0	26	0	0
T21	0	42	0	0
T22	0	48	0	0
T23	0	6	0	0
T24	950038	0	0	0
T25	490430	0	0	0
T26	352206	0	0	0
T27	328129	0	0	0
T28	151782	0	0	0
T29	16923	0	0	0
T30	207491	0	0	0
T31	28744	0	0	0
T32	195265	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2456	0	0
T14	151756	24	0	0
T15	0	38	0	0
T16	0	5	0	0
T17	0	32	0	0
T18	0	39	0	0
T19	0	55	0	0
T20	0	12	0	0
T21	0	37	0	0
T22	0	36	0	0
T23	0	6	0	0
T24	950038	0	0	0
T25	490430	0	0	0
T26	352206	0	0	0
T27	328129	0	0	0
T28	151782	0	0	0
T29	16923	0	0	0
T30	207491	0	0	0
T31	28744	0	0	0
T32	195265	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2353	0	0
T14	151756	16	0	0
T15	0	53	0	0
T17	0	21	0	0
T18	0	41	0	0
T19	0	42	0	0
T20	0	24	0	0
T21	0	34	0	0
T22	0	34	0	0
T23	0	5	0	0
T24	950038	0	0	0
T25	490430	0	0	0
T26	352206	0	0	0
T27	328129	0	0	0
T28	151782	0	0	0
T29	16923	0	0	0
T30	207491	0	0	0
T31	28744	0	0	0
T32	195265	0	0	0
T33	0	9	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2317	0	0
T14	151756	17	0	0
T15	0	27	0	0
T16	0	6	0	0
T17	0	26	0	0
T18	0	41	0	0
T19	0	48	0	0
T20	0	10	0	0
T21	0	36	0	0
T22	0	35	0	0
T23	0	4	0	0
T24	950038	0	0	0
T25	490430	0	0	0
T26	352206	0	0	0
T27	328129	0	0	0
T28	151782	0	0	0
T29	16923	0	0	0
T30	207491	0	0	0
T31	28744	0	0	0
T32	195265	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2362	0	0
T14	151756	4	0	0
T15	0	57	0	0
T16	0	23	0	0
T17	0	32	0	0
T18	0	37	0	0
T19	0	32	0	0
T20	0	26	0	0
T21	0	36	0	0
T22	0	30	0	0
T23	0	16	0	0
T24	950038	0	0	0
T25	490430	0	0	0
T26	352206	0	0	0
T27	328129	0	0	0
T28	151782	0	0	0
T29	16923	0	0	0
T30	207491	0	0	0
T31	28744	0	0	0
T32	195265	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2517	0	0
T14	151756	25	0	0
T15	0	30	0	0
T16	0	21	0	0
T17	0	35	0	0
T18	0	43	0	0
T19	0	38	0	0
T20	0	23	0	0
T21	0	42	0	0
T22	0	52	0	0
T23	0	6	0	0
T24	950038	0	0	0
T25	490430	0	0	0
T26	352206	0	0	0
T27	328129	0	0	0
T28	151782	0	0	0
T29	16923	0	0	0
T30	207491	0	0	0
T31	28744	0	0	0
T32	195265	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2381	0	0
T14	151756	32	0	0
T15	0	42	0	0
T16	0	12	0	0
T17	0	18	0	0
T18	0	32	0	0
T19	0	42	0	0
T20	0	12	0	0
T21	0	37	0	0
T22	0	49	0	0
T23	0	3	0	0
T24	950038	0	0	0
T25	490430	0	0	0
T26	352206	0	0	0
T27	328129	0	0	0
T28	151782	0	0	0
T29	16923	0	0	0
T30	207491	0	0	0
T31	28744	0	0	0
T32	195265	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2389	0	0
T14	151756	25	0	0
T15	0	27	0	0
T16	0	14	0	0
T17	0	13	0	0
T18	0	38	0	0
T19	0	34	0	0
T20	0	15	0	0
T21	0	54	0	0
T22	0	45	0	0
T23	0	8	0	0
T24	950038	0	0	0
T25	490430	0	0	0
T26	352206	0	0	0
T27	328129	0	0	0
T28	151782	0	0	0
T29	16923	0	0	0
T30	207491	0	0	0
T31	28744	0	0	0
T32	195265	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2291	0	0
T14	151756	25	0	0
T15	0	37	0	0
T16	0	8	0	0
T17	0	20	0	0
T18	0	44	0	0
T19	0	27	0	0
T20	0	28	0	0
T21	0	40	0	0
T22	0	38	0	0
T23	0	6	0	0
T24	950038	0	0	0
T25	490430	0	0	0
T26	352206	0	0	0
T27	328129	0	0	0
T28	151782	0	0	0
T29	16923	0	0	0
T30	207491	0	0	0
T31	28744	0	0	0
T32	195265	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2508	0	0
T14	151756	29	0	0
T15	0	39	0	0
T16	0	15	0	0
T17	0	28	0	0
T18	0	42	0	0
T19	0	20	0	0
T20	0	17	0	0
T21	0	49	0	0
T22	0	51	0	0
T24	950038	0	0	0
T25	490430	0	0	0
T26	352206	0	0	0
T27	328129	0	0	0
T28	151782	0	0	0
T29	16923	0	0	0
T30	207491	0	0	0
T31	28744	0	0	0
T32	195265	0	0	0
T33	0	17	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2456	0	0
T14	151756	14	0	0
T15	0	41	0	0
T16	0	6	0	0
T17	0	32	0	0
T18	0	58	0	0
T19	0	37	0	0
T20	0	38	0	0
T21	0	27	0	0
T22	0	55	0	0
T23	0	5	0	0
T24	950038	0	0	0
T25	490430	0	0	0
T26	352206	0	0	0
T27	328129	0	0	0
T28	151782	0	0	0
T29	16923	0	0	0
T30	207491	0	0	0
T31	28744	0	0	0
T32	195265	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2235	0	0
T14	151756	29	0	0
T15	0	33	0	0
T16	0	17	0	0
T17	0	31	0	0
T18	0	54	0	0
T19	0	28	0	0
T20	0	15	0	0
T21	0	37	0	0
T22	0	16	0	0
T24	950038	0	0	0
T25	490430	0	0	0
T26	352206	0	0	0
T27	328129	0	0	0
T28	151782	0	0	0
T29	16923	0	0	0
T30	207491	0	0	0
T31	28744	0	0	0
T32	195265	0	0	0
T33	0	15	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2423	0	0
T14	151756	17	0	0
T15	0	34	0	0
T16	0	17	0	0
T17	0	26	0	0
T18	0	62	0	0
T19	0	35	0	0
T20	0	18	0	0
T21	0	30	0	0
T22	0	37	0	0
T23	0	9	0	0
T24	950038	0	0	0
T25	490430	0	0	0
T26	352206	0	0	0
T27	328129	0	0	0
T28	151782	0	0	0
T29	16923	0	0	0
T30	207491	0	0	0
T31	28744	0	0	0
T32	195265	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2302	0	0
T14	151756	25	0	0
T15	0	35	0	0
T16	0	11	0	0
T17	0	15	0	0
T18	0	48	0	0
T19	0	40	0	0
T20	0	24	0	0
T21	0	37	0	0
T22	0	42	0	0
T23	0	13	0	0
T24	950038	0	0	0
T25	490430	0	0	0
T26	352206	0	0	0
T27	328129	0	0	0
T28	151782	0	0	0
T29	16923	0	0	0
T30	207491	0	0	0
T31	28744	0	0	0
T32	195265	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2677	0	0
T14	151756	23	0	0
T15	0	35	0	0
T16	0	26	0	0
T17	0	39	0	0
T18	0	42	0	0
T19	0	41	0	0
T20	0	25	0	0
T21	0	30	0	0
T22	0	22	0	0
T23	0	8	0	0
T24	950038	0	0	0
T25	490430	0	0	0
T26	352206	0	0	0
T27	328129	0	0	0
T28	151782	0	0	0
T29	16923	0	0	0
T30	207491	0	0	0
T31	28744	0	0	0
T32	195265	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2374	0	0
T14	151756	12	0	0
T15	0	50	0	0
T16	0	13	0	0
T17	0	21	0	0
T18	0	40	0	0
T19	0	38	0	0
T20	0	13	0	0
T21	0	53	0	0
T22	0	39	0	0
T23	0	4	0	0
T24	950038	0	0	0
T25	490430	0	0	0
T26	352206	0	0	0
T27	328129	0	0	0
T28	151782	0	0	0
T29	16923	0	0	0
T30	207491	0	0	0
T31	28744	0	0	0
T32	195265	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2197	0	0
T14	151756	20	0	0
T15	0	22	0	0
T16	0	11	0	0
T17	0	20	0	0
T18	0	50	0	0
T19	0	37	0	0
T20	0	25	0	0
T21	0	41	0	0
T22	0	24	0	0
T23	0	5	0	0
T24	950038	0	0	0
T25	490430	0	0	0
T26	352206	0	0	0
T27	328129	0	0	0
T28	151782	0	0	0
T29	16923	0	0	0
T30	207491	0	0	0
T31	28744	0	0	0
T32	195265	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1720	0	0
T14	151756	25	0	0
T15	0	32	0	0
T16	0	21	0	0
T17	0	43	0	0
T18	0	32	0	0
T19	0	50	0	0
T20	0	11	0	0
T21	0	20	0	0
T22	0	55	0	0
T23	0	2	0	0
T24	950038	0	0	0
T25	490430	0	0	0
T26	352206	0	0	0
T27	328129	0	0	0
T28	151782	0	0	0
T29	16923	0	0	0
T30	207491	0	0	0
T31	28744	0	0	0
T32	195265	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2241	0	0
T14	151756	13	0	0
T15	0	47	0	0
T16	0	17	0	0
T17	0	32	0	0
T18	0	48	0	0
T19	0	23	0	0
T20	0	18	0	0
T21	0	41	0	0
T22	0	37	0	0
T23	0	14	0	0
T24	950038	0	0	0
T25	490430	0	0	0
T26	352206	0	0	0
T27	328129	0	0	0
T28	151782	0	0	0
T29	16923	0	0	0
T30	207491	0	0	0
T31	28744	0	0	0
T32	195265	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1779	0	0
T14	151756	26	0	0
T15	0	28	0	0
T16	0	10	0	0
T17	0	30	0	0
T18	0	38	0	0
T19	0	36	0	0
T20	0	17	0	0
T21	0	36	0	0
T22	0	39	0	0
T23	0	9	0	0
T24	950038	0	0	0
T25	490430	0	0	0
T26	352206	0	0	0
T27	328129	0	0	0
T28	151782	0	0	0
T29	16923	0	0	0
T30	207491	0	0	0
T31	28744	0	0	0
T32	195265	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2164	0	0
T14	151756	30	0	0
T15	0	34	0	0
T16	0	9	0	0
T17	0	26	0	0
T18	0	38	0	0
T19	0	56	0	0
T20	0	24	0	0
T21	0	47	0	0
T22	0	45	0	0
T23	0	5	0	0
T24	950038	0	0	0
T25	490430	0	0	0
T26	352206	0	0	0
T27	328129	0	0	0
T28	151782	0	0	0
T29	16923	0	0	0
T30	207491	0	0	0
T31	28744	0	0	0
T32	195265	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1905	0	0
T14	151756	26	0	0
T15	0	39	0	0
T16	0	9	0	0
T17	0	42	0	0
T18	0	43	0	0
T19	0	43	0	0
T20	0	19	0	0
T21	0	44	0	0
T22	0	40	0	0
T23	0	13	0	0
T24	950038	0	0	0
T25	490430	0	0	0
T26	352206	0	0	0
T27	328129	0	0	0
T28	151782	0	0	0
T29	16923	0	0	0
T30	207491	0	0	0
T31	28744	0	0	0
T32	195265	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2176	0	0
T14	151756	21	0	0
T15	0	34	0	0
T16	0	13	0	0
T17	0	35	0	0
T18	0	32	0	0
T19	0	47	0	0
T20	0	16	0	0
T21	0	37	0	0
T22	0	44	0	0
T23	0	14	0	0
T24	950038	0	0	0
T25	490430	0	0	0
T26	352206	0	0	0
T27	328129	0	0	0
T28	151782	0	0	0
T29	16923	0	0	0
T30	207491	0	0	0
T31	28744	0	0	0
T32	195265	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2750	0	0
T14	151756	20	0	0
T15	0	61	0	0
T16	0	28	0	0
T17	0	59	0	0
T18	0	69	0	0
T19	0	81	0	0
T20	0	39	0	0
T21	0	47	0	0
T24	950038	0	0	0
T25	490430	0	0	0
T26	352206	0	0	0
T27	328129	0	0	0
T28	151782	0	0	0
T29	16923	0	0	0
T30	207491	0	0	0
T31	28744	0	0	0
T32	195265	0	0	0
T34	0	8	0	0
T35	0	23	0	0