Line Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Module :
prim_pulse_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T4,T5,T1 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T5,T1 |
Branch Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Module :
prim_pulse_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
361245 |
0 |
0 |
T1 |
3615627 |
42 |
0 |
0 |
T2 |
4212330 |
84 |
0 |
0 |
T3 |
10091006 |
87 |
0 |
0 |
T4 |
11161 |
0 |
0 |
0 |
T5 |
7833 |
0 |
0 |
0 |
T6 |
7769056 |
42 |
0 |
0 |
T7 |
8840342 |
84 |
0 |
0 |
T8 |
9617876 |
126 |
0 |
0 |
T9 |
2614267 |
1363 |
0 |
0 |
T10 |
12778792 |
203 |
0 |
0 |
T11 |
390025 |
236 |
0 |
0 |
T12 |
554758 |
42 |
0 |
0 |
T13 |
264743 |
108 |
0 |
0 |
T14 |
103726 |
108 |
0 |
0 |
T15 |
33162 |
28 |
0 |
0 |
T16 |
208116 |
0 |
0 |
0 |
T17 |
3884138 |
0 |
0 |
0 |
T27 |
5440 |
0 |
0 |
0 |
T28 |
67696 |
0 |
0 |
0 |
T29 |
4979 |
0 |
0 |
0 |
T30 |
960 |
10 |
0 |
0 |
T31 |
0 |
20 |
0 |
0 |
T34 |
0 |
1 |
0 |
0 |
T42 |
0 |
34 |
0 |
0 |
T43 |
0 |
41 |
0 |
0 |
T45 |
0 |
67 |
0 |
0 |
T79 |
0 |
20 |
0 |
0 |
T103 |
0 |
20 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
364506 |
0 |
0 |
T1 |
3490371 |
42 |
0 |
0 |
T2 |
4129653 |
84 |
0 |
0 |
T3 |
9085846 |
87 |
0 |
0 |
T4 |
87 |
0 |
0 |
0 |
T5 |
64 |
0 |
0 |
0 |
T6 |
7116190 |
42 |
0 |
0 |
T7 |
8199732 |
84 |
0 |
0 |
T8 |
9028116 |
126 |
0 |
0 |
T9 |
2523294 |
1365 |
0 |
0 |
T10 |
12778792 |
207 |
0 |
0 |
T11 |
390025 |
241 |
0 |
0 |
T12 |
554758 |
42 |
0 |
0 |
T13 |
264743 |
108 |
0 |
0 |
T14 |
183327 |
108 |
0 |
0 |
T15 |
159178 |
28 |
0 |
0 |
T16 |
197330 |
0 |
0 |
0 |
T17 |
3501580 |
0 |
0 |
0 |
T27 |
489739 |
0 |
0 |
0 |
T28 |
169801 |
0 |
0 |
0 |
T29 |
249023 |
0 |
0 |
0 |
T30 |
465946 |
10 |
0 |
0 |
T31 |
0 |
20 |
0 |
0 |
T34 |
0 |
5 |
0 |
0 |
T42 |
0 |
34 |
0 |
0 |
T43 |
0 |
41 |
0 |
0 |
T45 |
0 |
67 |
0 |
0 |
T79 |
0 |
20 |
0 |
0 |
T103 |
0 |
20 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 5 | 2 | 40.00 |
Logical | 5 | 2 | 40.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Unreachable | |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 5 | 2 | 40.00 |
Logical | 5 | 2 | 40.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Unreachable | |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 6 | 75.00 |
Logical | 8 | 6 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T10,T11,T34 |
1 | 0 | Covered | T10,T11,T34 |
1 | 1 | Not Covered | |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T10,T11,T34 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T10,T11,T34 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
78 |
0 |
0 |
T10 |
53244 |
1 |
0 |
0 |
T11 |
7646 |
1 |
0 |
0 |
T12 |
4584 |
0 |
0 |
0 |
T13 |
120338 |
0 |
0 |
0 |
T14 |
103726 |
0 |
0 |
0 |
T15 |
33162 |
0 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T19 |
0 |
1 |
0 |
0 |
T27 |
5440 |
0 |
0 |
0 |
T28 |
67696 |
0 |
0 |
0 |
T29 |
4979 |
0 |
0 |
0 |
T30 |
960 |
0 |
0 |
0 |
T34 |
0 |
1 |
0 |
0 |
T35 |
0 |
1 |
0 |
0 |
T36 |
0 |
1 |
0 |
0 |
T37 |
0 |
1 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
T39 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
371 |
0 |
0 |
T10 |
619324 |
5 |
0 |
0 |
T11 |
382379 |
5 |
0 |
0 |
T12 |
550174 |
0 |
0 |
0 |
T13 |
144405 |
0 |
0 |
0 |
T14 |
183327 |
0 |
0 |
0 |
T15 |
159178 |
0 |
0 |
0 |
T18 |
0 |
5 |
0 |
0 |
T19 |
0 |
5 |
0 |
0 |
T27 |
489739 |
0 |
0 |
0 |
T28 |
169801 |
0 |
0 |
0 |
T29 |
249023 |
0 |
0 |
0 |
T30 |
465946 |
0 |
0 |
0 |
T34 |
0 |
5 |
0 |
0 |
T35 |
0 |
9 |
0 |
0 |
T36 |
0 |
9 |
0 |
0 |
T37 |
0 |
4 |
0 |
0 |
T38 |
0 |
5 |
0 |
0 |
T39 |
0 |
5 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
40863 |
0 |
0 |
T1 |
33399 |
3 |
0 |
0 |
T2 |
71391 |
6 |
0 |
0 |
T3 |
1037 |
39 |
0 |
0 |
T6 |
32642 |
3 |
0 |
0 |
T7 |
64059 |
6 |
0 |
0 |
T8 |
97902 |
9 |
0 |
0 |
T9 |
23940 |
388 |
0 |
0 |
T10 |
53244 |
35 |
0 |
0 |
T11 |
0 |
67 |
0 |
0 |
T12 |
0 |
21 |
0 |
0 |
T16 |
86 |
0 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
41029 |
0 |
0 |
T1 |
158655 |
3 |
0 |
0 |
T2 |
154068 |
6 |
0 |
0 |
T3 |
503617 |
39 |
0 |
0 |
T6 |
359075 |
3 |
0 |
0 |
T7 |
384364 |
6 |
0 |
0 |
T8 |
392782 |
9 |
0 |
0 |
T9 |
114913 |
389 |
0 |
0 |
T10 |
619324 |
35 |
0 |
0 |
T11 |
0 |
68 |
0 |
0 |
T12 |
0 |
21 |
0 |
0 |
T16 |
10872 |
0 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
40978 |
0 |
0 |
T1 |
158655 |
3 |
0 |
0 |
T2 |
154068 |
6 |
0 |
0 |
T3 |
503617 |
39 |
0 |
0 |
T6 |
359075 |
3 |
0 |
0 |
T7 |
384364 |
6 |
0 |
0 |
T8 |
392782 |
9 |
0 |
0 |
T9 |
114913 |
388 |
0 |
0 |
T10 |
619324 |
35 |
0 |
0 |
T11 |
0 |
67 |
0 |
0 |
T12 |
0 |
21 |
0 |
0 |
T16 |
10872 |
0 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
40996 |
0 |
0 |
T1 |
33399 |
3 |
0 |
0 |
T2 |
71391 |
6 |
0 |
0 |
T3 |
1037 |
39 |
0 |
0 |
T6 |
32642 |
3 |
0 |
0 |
T7 |
64059 |
6 |
0 |
0 |
T8 |
97902 |
9 |
0 |
0 |
T9 |
23940 |
389 |
0 |
0 |
T10 |
53244 |
35 |
0 |
0 |
T11 |
0 |
67 |
0 |
0 |
T12 |
0 |
21 |
0 |
0 |
T16 |
86 |
0 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
19035 |
0 |
0 |
T1 |
33399 |
2 |
0 |
0 |
T2 |
71391 |
4 |
0 |
0 |
T3 |
1037 |
19 |
0 |
0 |
T6 |
32642 |
2 |
0 |
0 |
T7 |
64059 |
4 |
0 |
0 |
T8 |
97902 |
6 |
0 |
0 |
T9 |
23940 |
194 |
0 |
0 |
T10 |
53244 |
21 |
0 |
0 |
T11 |
0 |
17 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T16 |
86 |
0 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
19158 |
0 |
0 |
T1 |
158655 |
2 |
0 |
0 |
T2 |
154068 |
4 |
0 |
0 |
T3 |
503617 |
19 |
0 |
0 |
T6 |
359075 |
2 |
0 |
0 |
T7 |
384364 |
4 |
0 |
0 |
T8 |
392782 |
6 |
0 |
0 |
T9 |
114913 |
194 |
0 |
0 |
T10 |
619324 |
21 |
0 |
0 |
T11 |
0 |
17 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T16 |
10872 |
0 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
19147 |
0 |
0 |
T1 |
158655 |
2 |
0 |
0 |
T2 |
154068 |
4 |
0 |
0 |
T3 |
503617 |
19 |
0 |
0 |
T6 |
359075 |
2 |
0 |
0 |
T7 |
384364 |
4 |
0 |
0 |
T8 |
392782 |
6 |
0 |
0 |
T9 |
114913 |
194 |
0 |
0 |
T10 |
619324 |
21 |
0 |
0 |
T11 |
0 |
17 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T16 |
10872 |
0 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
19147 |
0 |
0 |
T1 |
33399 |
2 |
0 |
0 |
T2 |
71391 |
4 |
0 |
0 |
T3 |
1037 |
19 |
0 |
0 |
T6 |
32642 |
2 |
0 |
0 |
T7 |
64059 |
4 |
0 |
0 |
T8 |
97902 |
6 |
0 |
0 |
T9 |
23940 |
194 |
0 |
0 |
T10 |
53244 |
21 |
0 |
0 |
T11 |
0 |
17 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T16 |
86 |
0 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T4,T5,T1 |
1 | 1 | Covered | T2,T7,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T2,T7,T8 |
1 | 1 | Covered | T4,T5,T1 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
15170 |
0 |
0 |
T1 |
33399 |
1 |
0 |
0 |
T2 |
71391 |
2 |
0 |
0 |
T3 |
1037 |
0 |
0 |
0 |
T4 |
87 |
1 |
0 |
0 |
T5 |
64 |
1 |
0 |
0 |
T6 |
32642 |
1 |
0 |
0 |
T7 |
64059 |
2 |
0 |
0 |
T8 |
97902 |
3 |
0 |
0 |
T9 |
0 |
194 |
0 |
0 |
T16 |
86 |
1 |
0 |
0 |
T17 |
1541 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
15339 |
0 |
0 |
T1 |
158655 |
1 |
0 |
0 |
T2 |
154068 |
2 |
0 |
0 |
T3 |
503617 |
0 |
0 |
0 |
T4 |
11161 |
1 |
0 |
0 |
T5 |
7833 |
1 |
0 |
0 |
T6 |
359075 |
1 |
0 |
0 |
T7 |
384364 |
2 |
0 |
0 |
T8 |
392782 |
3 |
0 |
0 |
T9 |
0 |
194 |
0 |
0 |
T16 |
10872 |
1 |
0 |
0 |
T17 |
192820 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T4,T5,T1 |
1 | 1 | Covered | T2,T7,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T2,T7,T8 |
1 | 1 | Covered | T4,T5,T1 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
15294 |
0 |
0 |
T1 |
158655 |
1 |
0 |
0 |
T2 |
154068 |
2 |
0 |
0 |
T3 |
503617 |
0 |
0 |
0 |
T4 |
11161 |
1 |
0 |
0 |
T5 |
7833 |
1 |
0 |
0 |
T6 |
359075 |
1 |
0 |
0 |
T7 |
384364 |
2 |
0 |
0 |
T8 |
392782 |
3 |
0 |
0 |
T9 |
0 |
194 |
0 |
0 |
T16 |
10872 |
1 |
0 |
0 |
T17 |
192820 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
15294 |
0 |
0 |
T1 |
33399 |
1 |
0 |
0 |
T2 |
71391 |
2 |
0 |
0 |
T3 |
1037 |
0 |
0 |
0 |
T4 |
87 |
1 |
0 |
0 |
T5 |
64 |
1 |
0 |
0 |
T6 |
32642 |
1 |
0 |
0 |
T7 |
64059 |
2 |
0 |
0 |
T8 |
97902 |
3 |
0 |
0 |
T9 |
0 |
194 |
0 |
0 |
T16 |
86 |
1 |
0 |
0 |
T17 |
1541 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T4,T5,T1 |
1 | 1 | Covered | T2,T7,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T2,T7,T8 |
1 | 1 | Covered | T4,T5,T1 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
15128 |
0 |
0 |
T1 |
33399 |
1 |
0 |
0 |
T2 |
71391 |
2 |
0 |
0 |
T3 |
1037 |
0 |
0 |
0 |
T4 |
87 |
1 |
0 |
0 |
T5 |
64 |
1 |
0 |
0 |
T6 |
32642 |
1 |
0 |
0 |
T7 |
64059 |
2 |
0 |
0 |
T8 |
97902 |
3 |
0 |
0 |
T9 |
0 |
194 |
0 |
0 |
T16 |
86 |
1 |
0 |
0 |
T17 |
1541 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
15295 |
0 |
0 |
T1 |
158655 |
1 |
0 |
0 |
T2 |
154068 |
2 |
0 |
0 |
T3 |
503617 |
0 |
0 |
0 |
T4 |
11161 |
1 |
0 |
0 |
T5 |
7833 |
1 |
0 |
0 |
T6 |
359075 |
1 |
0 |
0 |
T7 |
384364 |
2 |
0 |
0 |
T8 |
392782 |
3 |
0 |
0 |
T9 |
0 |
194 |
0 |
0 |
T16 |
10872 |
1 |
0 |
0 |
T17 |
192820 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T4,T5,T1 |
1 | 1 | Covered | T2,T7,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T2,T7,T8 |
1 | 1 | Covered | T4,T5,T1 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
15250 |
0 |
0 |
T1 |
158655 |
1 |
0 |
0 |
T2 |
154068 |
2 |
0 |
0 |
T3 |
503617 |
0 |
0 |
0 |
T4 |
11161 |
1 |
0 |
0 |
T5 |
7833 |
1 |
0 |
0 |
T6 |
359075 |
1 |
0 |
0 |
T7 |
384364 |
2 |
0 |
0 |
T8 |
392782 |
3 |
0 |
0 |
T9 |
0 |
194 |
0 |
0 |
T16 |
10872 |
1 |
0 |
0 |
T17 |
192820 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
15250 |
0 |
0 |
T1 |
33399 |
1 |
0 |
0 |
T2 |
71391 |
2 |
0 |
0 |
T3 |
1037 |
0 |
0 |
0 |
T4 |
87 |
1 |
0 |
0 |
T5 |
64 |
1 |
0 |
0 |
T6 |
32642 |
1 |
0 |
0 |
T7 |
64059 |
2 |
0 |
0 |
T8 |
97902 |
3 |
0 |
0 |
T9 |
0 |
194 |
0 |
0 |
T16 |
86 |
1 |
0 |
0 |
T17 |
1541 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T1,T2,T6 |
1 | 1 | Covered | T1,T2,T6 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T1,T2,T6 |
1 | 1 | Covered | T1,T2,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
21339 |
0 |
0 |
T1 |
33399 |
2 |
0 |
0 |
T2 |
71391 |
4 |
0 |
0 |
T3 |
1037 |
0 |
0 |
0 |
T6 |
32642 |
2 |
0 |
0 |
T7 |
64059 |
4 |
0 |
0 |
T8 |
97902 |
6 |
0 |
0 |
T9 |
23940 |
262 |
0 |
0 |
T10 |
53244 |
2 |
0 |
0 |
T11 |
0 |
6 |
0 |
0 |
T13 |
0 |
6 |
0 |
0 |
T14 |
0 |
6 |
0 |
0 |
T16 |
86 |
0 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
21461 |
0 |
0 |
T1 |
158655 |
2 |
0 |
0 |
T2 |
154068 |
4 |
0 |
0 |
T3 |
503617 |
0 |
0 |
0 |
T6 |
359075 |
2 |
0 |
0 |
T7 |
384364 |
4 |
0 |
0 |
T8 |
392782 |
6 |
0 |
0 |
T9 |
114913 |
262 |
0 |
0 |
T10 |
619324 |
2 |
0 |
0 |
T11 |
0 |
6 |
0 |
0 |
T13 |
0 |
6 |
0 |
0 |
T14 |
0 |
6 |
0 |
0 |
T16 |
10872 |
0 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T1,T2,T6 |
1 | 1 | Covered | T1,T2,T6 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T1,T2,T6 |
1 | 1 | Covered | T1,T2,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
21449 |
0 |
0 |
T1 |
158655 |
2 |
0 |
0 |
T2 |
154068 |
4 |
0 |
0 |
T3 |
503617 |
0 |
0 |
0 |
T6 |
359075 |
2 |
0 |
0 |
T7 |
384364 |
4 |
0 |
0 |
T8 |
392782 |
6 |
0 |
0 |
T9 |
114913 |
262 |
0 |
0 |
T10 |
619324 |
2 |
0 |
0 |
T11 |
0 |
6 |
0 |
0 |
T13 |
0 |
6 |
0 |
0 |
T14 |
0 |
6 |
0 |
0 |
T16 |
10872 |
0 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
21449 |
0 |
0 |
T1 |
33399 |
2 |
0 |
0 |
T2 |
71391 |
4 |
0 |
0 |
T3 |
1037 |
0 |
0 |
0 |
T6 |
32642 |
2 |
0 |
0 |
T7 |
64059 |
4 |
0 |
0 |
T8 |
97902 |
6 |
0 |
0 |
T9 |
23940 |
262 |
0 |
0 |
T10 |
53244 |
2 |
0 |
0 |
T11 |
0 |
6 |
0 |
0 |
T13 |
0 |
6 |
0 |
0 |
T14 |
0 |
6 |
0 |
0 |
T16 |
86 |
0 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T1,T2,T6 |
1 | 1 | Covered | T2,T7,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T2,T7,T8 |
1 | 1 | Covered | T1,T2,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
1967 |
0 |
0 |
T1 |
33399 |
1 |
0 |
0 |
T2 |
71391 |
2 |
0 |
0 |
T3 |
1037 |
0 |
0 |
0 |
T6 |
32642 |
1 |
0 |
0 |
T7 |
64059 |
2 |
0 |
0 |
T8 |
97902 |
3 |
0 |
0 |
T9 |
23940 |
1 |
0 |
0 |
T10 |
53244 |
4 |
0 |
0 |
T11 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T16 |
86 |
0 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2088 |
0 |
0 |
T1 |
158655 |
1 |
0 |
0 |
T2 |
154068 |
2 |
0 |
0 |
T3 |
503617 |
0 |
0 |
0 |
T6 |
359075 |
1 |
0 |
0 |
T7 |
384364 |
2 |
0 |
0 |
T8 |
392782 |
3 |
0 |
0 |
T9 |
114913 |
1 |
0 |
0 |
T10 |
619324 |
4 |
0 |
0 |
T11 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T16 |
10872 |
0 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T1,T2,T6 |
1 | 1 | Covered | T2,T7,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T2,T7,T8 |
1 | 1 | Covered | T1,T2,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2075 |
0 |
0 |
T1 |
158655 |
1 |
0 |
0 |
T2 |
154068 |
2 |
0 |
0 |
T3 |
503617 |
0 |
0 |
0 |
T6 |
359075 |
1 |
0 |
0 |
T7 |
384364 |
2 |
0 |
0 |
T8 |
392782 |
3 |
0 |
0 |
T9 |
114913 |
1 |
0 |
0 |
T10 |
619324 |
4 |
0 |
0 |
T11 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T16 |
10872 |
0 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
2075 |
0 |
0 |
T1 |
33399 |
1 |
0 |
0 |
T2 |
71391 |
2 |
0 |
0 |
T3 |
1037 |
0 |
0 |
0 |
T6 |
32642 |
1 |
0 |
0 |
T7 |
64059 |
2 |
0 |
0 |
T8 |
97902 |
3 |
0 |
0 |
T9 |
23940 |
1 |
0 |
0 |
T10 |
53244 |
4 |
0 |
0 |
T11 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T16 |
86 |
0 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T1,T2,T6 |
1 | 1 | Covered | T2,T7,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T2,T7,T8 |
1 | 1 | Covered | T1,T2,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
1843 |
0 |
0 |
T1 |
33399 |
1 |
0 |
0 |
T2 |
71391 |
2 |
0 |
0 |
T3 |
1037 |
0 |
0 |
0 |
T6 |
32642 |
1 |
0 |
0 |
T7 |
64059 |
2 |
0 |
0 |
T8 |
97902 |
3 |
0 |
0 |
T9 |
23940 |
0 |
0 |
0 |
T10 |
53244 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
86 |
0 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1965 |
0 |
0 |
T1 |
158655 |
1 |
0 |
0 |
T2 |
154068 |
2 |
0 |
0 |
T3 |
503617 |
0 |
0 |
0 |
T6 |
359075 |
1 |
0 |
0 |
T7 |
384364 |
2 |
0 |
0 |
T8 |
392782 |
3 |
0 |
0 |
T9 |
114913 |
0 |
0 |
0 |
T10 |
619324 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
10872 |
0 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T1,T2,T6 |
1 | 1 | Covered | T2,T7,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T2,T7,T8 |
1 | 1 | Covered | T1,T2,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1954 |
0 |
0 |
T1 |
158655 |
1 |
0 |
0 |
T2 |
154068 |
2 |
0 |
0 |
T3 |
503617 |
0 |
0 |
0 |
T6 |
359075 |
1 |
0 |
0 |
T7 |
384364 |
2 |
0 |
0 |
T8 |
392782 |
3 |
0 |
0 |
T9 |
114913 |
0 |
0 |
0 |
T10 |
619324 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
10872 |
0 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
1954 |
0 |
0 |
T1 |
33399 |
1 |
0 |
0 |
T2 |
71391 |
2 |
0 |
0 |
T3 |
1037 |
0 |
0 |
0 |
T6 |
32642 |
1 |
0 |
0 |
T7 |
64059 |
2 |
0 |
0 |
T8 |
97902 |
3 |
0 |
0 |
T9 |
23940 |
0 |
0 |
0 |
T10 |
53244 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
86 |
0 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T1,T2,T6 |
1 | 1 | Covered | T2,T7,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T2,T7,T8 |
1 | 1 | Covered | T1,T2,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
1829 |
0 |
0 |
T1 |
33399 |
1 |
0 |
0 |
T2 |
71391 |
2 |
0 |
0 |
T3 |
1037 |
0 |
0 |
0 |
T6 |
32642 |
1 |
0 |
0 |
T7 |
64059 |
2 |
0 |
0 |
T8 |
97902 |
3 |
0 |
0 |
T9 |
23940 |
0 |
0 |
0 |
T10 |
53244 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
86 |
0 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1950 |
0 |
0 |
T1 |
158655 |
1 |
0 |
0 |
T2 |
154068 |
2 |
0 |
0 |
T3 |
503617 |
0 |
0 |
0 |
T6 |
359075 |
1 |
0 |
0 |
T7 |
384364 |
2 |
0 |
0 |
T8 |
392782 |
3 |
0 |
0 |
T9 |
114913 |
0 |
0 |
0 |
T10 |
619324 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
10872 |
0 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T1,T2,T6 |
1 | 1 | Covered | T2,T7,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T2,T7,T8 |
1 | 1 | Covered | T1,T2,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1937 |
0 |
0 |
T1 |
158655 |
1 |
0 |
0 |
T2 |
154068 |
2 |
0 |
0 |
T3 |
503617 |
0 |
0 |
0 |
T6 |
359075 |
1 |
0 |
0 |
T7 |
384364 |
2 |
0 |
0 |
T8 |
392782 |
3 |
0 |
0 |
T9 |
114913 |
0 |
0 |
0 |
T10 |
619324 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
10872 |
0 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
1937 |
0 |
0 |
T1 |
33399 |
1 |
0 |
0 |
T2 |
71391 |
2 |
0 |
0 |
T3 |
1037 |
0 |
0 |
0 |
T6 |
32642 |
1 |
0 |
0 |
T7 |
64059 |
2 |
0 |
0 |
T8 |
97902 |
3 |
0 |
0 |
T9 |
23940 |
0 |
0 |
0 |
T10 |
53244 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
86 |
0 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T1,T2,T6 |
1 | 1 | Covered | T2,T7,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T2,T7,T8 |
1 | 1 | Covered | T1,T2,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
1843 |
0 |
0 |
T1 |
33399 |
1 |
0 |
0 |
T2 |
71391 |
2 |
0 |
0 |
T3 |
1037 |
0 |
0 |
0 |
T6 |
32642 |
1 |
0 |
0 |
T7 |
64059 |
2 |
0 |
0 |
T8 |
97902 |
3 |
0 |
0 |
T9 |
23940 |
0 |
0 |
0 |
T10 |
53244 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
86 |
0 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1963 |
0 |
0 |
T1 |
158655 |
1 |
0 |
0 |
T2 |
154068 |
2 |
0 |
0 |
T3 |
503617 |
0 |
0 |
0 |
T6 |
359075 |
1 |
0 |
0 |
T7 |
384364 |
2 |
0 |
0 |
T8 |
392782 |
3 |
0 |
0 |
T9 |
114913 |
0 |
0 |
0 |
T10 |
619324 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
10872 |
0 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T1,T2,T6 |
1 | 1 | Covered | T2,T7,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T2,T7,T8 |
1 | 1 | Covered | T1,T2,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1950 |
0 |
0 |
T1 |
158655 |
1 |
0 |
0 |
T2 |
154068 |
2 |
0 |
0 |
T3 |
503617 |
0 |
0 |
0 |
T6 |
359075 |
1 |
0 |
0 |
T7 |
384364 |
2 |
0 |
0 |
T8 |
392782 |
3 |
0 |
0 |
T9 |
114913 |
0 |
0 |
0 |
T10 |
619324 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
10872 |
0 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
1950 |
0 |
0 |
T1 |
33399 |
1 |
0 |
0 |
T2 |
71391 |
2 |
0 |
0 |
T3 |
1037 |
0 |
0 |
0 |
T6 |
32642 |
1 |
0 |
0 |
T7 |
64059 |
2 |
0 |
0 |
T8 |
97902 |
3 |
0 |
0 |
T9 |
23940 |
0 |
0 |
0 |
T10 |
53244 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
86 |
0 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T1,T2,T6 |
1 | 1 | Covered | T2,T7,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T2,T7,T8 |
1 | 1 | Covered | T1,T2,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
1839 |
0 |
0 |
T1 |
33399 |
1 |
0 |
0 |
T2 |
71391 |
2 |
0 |
0 |
T3 |
1037 |
0 |
0 |
0 |
T6 |
32642 |
1 |
0 |
0 |
T7 |
64059 |
2 |
0 |
0 |
T8 |
97902 |
3 |
0 |
0 |
T9 |
23940 |
0 |
0 |
0 |
T10 |
53244 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
86 |
0 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1960 |
0 |
0 |
T1 |
158655 |
1 |
0 |
0 |
T2 |
154068 |
2 |
0 |
0 |
T3 |
503617 |
0 |
0 |
0 |
T6 |
359075 |
1 |
0 |
0 |
T7 |
384364 |
2 |
0 |
0 |
T8 |
392782 |
3 |
0 |
0 |
T9 |
114913 |
0 |
0 |
0 |
T10 |
619324 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
10872 |
0 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T1,T2,T6 |
1 | 1 | Covered | T2,T7,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T2,T7,T8 |
1 | 1 | Covered | T1,T2,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1949 |
0 |
0 |
T1 |
158655 |
1 |
0 |
0 |
T2 |
154068 |
2 |
0 |
0 |
T3 |
503617 |
0 |
0 |
0 |
T6 |
359075 |
1 |
0 |
0 |
T7 |
384364 |
2 |
0 |
0 |
T8 |
392782 |
3 |
0 |
0 |
T9 |
114913 |
0 |
0 |
0 |
T10 |
619324 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
10872 |
0 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
1949 |
0 |
0 |
T1 |
33399 |
1 |
0 |
0 |
T2 |
71391 |
2 |
0 |
0 |
T3 |
1037 |
0 |
0 |
0 |
T6 |
32642 |
1 |
0 |
0 |
T7 |
64059 |
2 |
0 |
0 |
T8 |
97902 |
3 |
0 |
0 |
T9 |
23940 |
0 |
0 |
0 |
T10 |
53244 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
86 |
0 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T1,T2,T6 |
1 | 1 | Covered | T2,T7,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T2,T7,T8 |
1 | 1 | Covered | T1,T2,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
1863 |
0 |
0 |
T1 |
33399 |
1 |
0 |
0 |
T2 |
71391 |
2 |
0 |
0 |
T3 |
1037 |
0 |
0 |
0 |
T6 |
32642 |
1 |
0 |
0 |
T7 |
64059 |
2 |
0 |
0 |
T8 |
97902 |
3 |
0 |
0 |
T9 |
23940 |
0 |
0 |
0 |
T10 |
53244 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
86 |
0 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1981 |
0 |
0 |
T1 |
158655 |
1 |
0 |
0 |
T2 |
154068 |
2 |
0 |
0 |
T3 |
503617 |
0 |
0 |
0 |
T6 |
359075 |
1 |
0 |
0 |
T7 |
384364 |
2 |
0 |
0 |
T8 |
392782 |
3 |
0 |
0 |
T9 |
114913 |
0 |
0 |
0 |
T10 |
619324 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
10872 |
0 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T1,T2,T6 |
1 | 1 | Covered | T2,T7,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T2,T7,T8 |
1 | 1 | Covered | T1,T2,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1969 |
0 |
0 |
T1 |
158655 |
1 |
0 |
0 |
T2 |
154068 |
2 |
0 |
0 |
T3 |
503617 |
0 |
0 |
0 |
T6 |
359075 |
1 |
0 |
0 |
T7 |
384364 |
2 |
0 |
0 |
T8 |
392782 |
3 |
0 |
0 |
T9 |
114913 |
0 |
0 |
0 |
T10 |
619324 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
10872 |
0 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
1969 |
0 |
0 |
T1 |
33399 |
1 |
0 |
0 |
T2 |
71391 |
2 |
0 |
0 |
T3 |
1037 |
0 |
0 |
0 |
T6 |
32642 |
1 |
0 |
0 |
T7 |
64059 |
2 |
0 |
0 |
T8 |
97902 |
3 |
0 |
0 |
T9 |
23940 |
0 |
0 |
0 |
T10 |
53244 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
86 |
0 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T1,T2,T6 |
1 | 1 | Covered | T2,T7,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T2,T7,T8 |
1 | 1 | Covered | T1,T2,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
1838 |
0 |
0 |
T1 |
33399 |
1 |
0 |
0 |
T2 |
71391 |
2 |
0 |
0 |
T3 |
1037 |
0 |
0 |
0 |
T6 |
32642 |
1 |
0 |
0 |
T7 |
64059 |
2 |
0 |
0 |
T8 |
97902 |
3 |
0 |
0 |
T9 |
23940 |
0 |
0 |
0 |
T10 |
53244 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
86 |
0 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1962 |
0 |
0 |
T1 |
158655 |
1 |
0 |
0 |
T2 |
154068 |
2 |
0 |
0 |
T3 |
503617 |
0 |
0 |
0 |
T6 |
359075 |
1 |
0 |
0 |
T7 |
384364 |
2 |
0 |
0 |
T8 |
392782 |
3 |
0 |
0 |
T9 |
114913 |
0 |
0 |
0 |
T10 |
619324 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
10872 |
0 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T1,T2,T6 |
1 | 1 | Covered | T2,T7,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T2,T7,T8 |
1 | 1 | Covered | T1,T2,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1950 |
0 |
0 |
T1 |
158655 |
1 |
0 |
0 |
T2 |
154068 |
2 |
0 |
0 |
T3 |
503617 |
0 |
0 |
0 |
T6 |
359075 |
1 |
0 |
0 |
T7 |
384364 |
2 |
0 |
0 |
T8 |
392782 |
3 |
0 |
0 |
T9 |
114913 |
0 |
0 |
0 |
T10 |
619324 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
10872 |
0 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
1950 |
0 |
0 |
T1 |
33399 |
1 |
0 |
0 |
T2 |
71391 |
2 |
0 |
0 |
T3 |
1037 |
0 |
0 |
0 |
T6 |
32642 |
1 |
0 |
0 |
T7 |
64059 |
2 |
0 |
0 |
T8 |
97902 |
3 |
0 |
0 |
T9 |
23940 |
0 |
0 |
0 |
T10 |
53244 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
86 |
0 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T1,T2,T6 |
1 | 1 | Covered | T2,T7,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T2,T7,T8 |
1 | 1 | Covered | T1,T2,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
1826 |
0 |
0 |
T1 |
33399 |
1 |
0 |
0 |
T2 |
71391 |
2 |
0 |
0 |
T3 |
1037 |
0 |
0 |
0 |
T6 |
32642 |
1 |
0 |
0 |
T7 |
64059 |
2 |
0 |
0 |
T8 |
97902 |
3 |
0 |
0 |
T9 |
23940 |
0 |
0 |
0 |
T10 |
53244 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
86 |
0 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1951 |
0 |
0 |
T1 |
158655 |
1 |
0 |
0 |
T2 |
154068 |
2 |
0 |
0 |
T3 |
503617 |
0 |
0 |
0 |
T6 |
359075 |
1 |
0 |
0 |
T7 |
384364 |
2 |
0 |
0 |
T8 |
392782 |
3 |
0 |
0 |
T9 |
114913 |
0 |
0 |
0 |
T10 |
619324 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
10872 |
0 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T1,T2,T6 |
1 | 1 | Covered | T2,T7,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T2,T7,T8 |
1 | 1 | Covered | T1,T2,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1939 |
0 |
0 |
T1 |
158655 |
1 |
0 |
0 |
T2 |
154068 |
2 |
0 |
0 |
T3 |
503617 |
0 |
0 |
0 |
T6 |
359075 |
1 |
0 |
0 |
T7 |
384364 |
2 |
0 |
0 |
T8 |
392782 |
3 |
0 |
0 |
T9 |
114913 |
0 |
0 |
0 |
T10 |
619324 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
10872 |
0 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
1939 |
0 |
0 |
T1 |
33399 |
1 |
0 |
0 |
T2 |
71391 |
2 |
0 |
0 |
T3 |
1037 |
0 |
0 |
0 |
T6 |
32642 |
1 |
0 |
0 |
T7 |
64059 |
2 |
0 |
0 |
T8 |
97902 |
3 |
0 |
0 |
T9 |
23940 |
0 |
0 |
0 |
T10 |
53244 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
86 |
0 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T1,T2,T6 |
1 | 1 | Covered | T2,T7,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T2,T7,T8 |
1 | 1 | Covered | T1,T2,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
1946 |
0 |
0 |
T1 |
33399 |
1 |
0 |
0 |
T2 |
71391 |
2 |
0 |
0 |
T3 |
1037 |
0 |
0 |
0 |
T6 |
32642 |
1 |
0 |
0 |
T7 |
64059 |
2 |
0 |
0 |
T8 |
97902 |
3 |
0 |
0 |
T9 |
23940 |
1 |
0 |
0 |
T10 |
53244 |
4 |
0 |
0 |
T11 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T16 |
86 |
0 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2070 |
0 |
0 |
T1 |
158655 |
1 |
0 |
0 |
T2 |
154068 |
2 |
0 |
0 |
T3 |
503617 |
0 |
0 |
0 |
T6 |
359075 |
1 |
0 |
0 |
T7 |
384364 |
2 |
0 |
0 |
T8 |
392782 |
3 |
0 |
0 |
T9 |
114913 |
1 |
0 |
0 |
T10 |
619324 |
4 |
0 |
0 |
T11 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T16 |
10872 |
0 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T1,T2,T6 |
1 | 1 | Covered | T2,T7,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T2,T7,T8 |
1 | 1 | Covered | T1,T2,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2058 |
0 |
0 |
T1 |
158655 |
1 |
0 |
0 |
T2 |
154068 |
2 |
0 |
0 |
T3 |
503617 |
0 |
0 |
0 |
T6 |
359075 |
1 |
0 |
0 |
T7 |
384364 |
2 |
0 |
0 |
T8 |
392782 |
3 |
0 |
0 |
T9 |
114913 |
1 |
0 |
0 |
T10 |
619324 |
4 |
0 |
0 |
T11 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T16 |
10872 |
0 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
2058 |
0 |
0 |
T1 |
33399 |
1 |
0 |
0 |
T2 |
71391 |
2 |
0 |
0 |
T3 |
1037 |
0 |
0 |
0 |
T6 |
32642 |
1 |
0 |
0 |
T7 |
64059 |
2 |
0 |
0 |
T8 |
97902 |
3 |
0 |
0 |
T9 |
23940 |
1 |
0 |
0 |
T10 |
53244 |
4 |
0 |
0 |
T11 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T16 |
86 |
0 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T1,T2,T6 |
1 | 1 | Covered | T2,T7,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T2,T7,T8 |
1 | 1 | Covered | T1,T2,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
1804 |
0 |
0 |
T1 |
33399 |
1 |
0 |
0 |
T2 |
71391 |
2 |
0 |
0 |
T3 |
1037 |
0 |
0 |
0 |
T6 |
32642 |
1 |
0 |
0 |
T7 |
64059 |
2 |
0 |
0 |
T8 |
97902 |
3 |
0 |
0 |
T9 |
23940 |
0 |
0 |
0 |
T10 |
53244 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
86 |
0 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1927 |
0 |
0 |
T1 |
158655 |
1 |
0 |
0 |
T2 |
154068 |
2 |
0 |
0 |
T3 |
503617 |
0 |
0 |
0 |
T6 |
359075 |
1 |
0 |
0 |
T7 |
384364 |
2 |
0 |
0 |
T8 |
392782 |
3 |
0 |
0 |
T9 |
114913 |
0 |
0 |
0 |
T10 |
619324 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
10872 |
0 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T1,T2,T6 |
1 | 1 | Covered | T2,T7,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T2,T7,T8 |
1 | 1 | Covered | T1,T2,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1917 |
0 |
0 |
T1 |
158655 |
1 |
0 |
0 |
T2 |
154068 |
2 |
0 |
0 |
T3 |
503617 |
0 |
0 |
0 |
T6 |
359075 |
1 |
0 |
0 |
T7 |
384364 |
2 |
0 |
0 |
T8 |
392782 |
3 |
0 |
0 |
T9 |
114913 |
0 |
0 |
0 |
T10 |
619324 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
10872 |
0 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
1917 |
0 |
0 |
T1 |
33399 |
1 |
0 |
0 |
T2 |
71391 |
2 |
0 |
0 |
T3 |
1037 |
0 |
0 |
0 |
T6 |
32642 |
1 |
0 |
0 |
T7 |
64059 |
2 |
0 |
0 |
T8 |
97902 |
3 |
0 |
0 |
T9 |
23940 |
0 |
0 |
0 |
T10 |
53244 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
86 |
0 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T1,T2,T6 |
1 | 1 | Covered | T2,T7,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T2,T7,T8 |
1 | 1 | Covered | T1,T2,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
1787 |
0 |
0 |
T1 |
33399 |
1 |
0 |
0 |
T2 |
71391 |
2 |
0 |
0 |
T3 |
1037 |
0 |
0 |
0 |
T6 |
32642 |
1 |
0 |
0 |
T7 |
64059 |
2 |
0 |
0 |
T8 |
97902 |
3 |
0 |
0 |
T9 |
23940 |
0 |
0 |
0 |
T10 |
53244 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
86 |
0 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1911 |
0 |
0 |
T1 |
158655 |
1 |
0 |
0 |
T2 |
154068 |
2 |
0 |
0 |
T3 |
503617 |
0 |
0 |
0 |
T6 |
359075 |
1 |
0 |
0 |
T7 |
384364 |
2 |
0 |
0 |
T8 |
392782 |
3 |
0 |
0 |
T9 |
114913 |
0 |
0 |
0 |
T10 |
619324 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
10872 |
0 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T1,T2,T6 |
1 | 1 | Covered | T2,T7,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T2,T7,T8 |
1 | 1 | Covered | T1,T2,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1899 |
0 |
0 |
T1 |
158655 |
1 |
0 |
0 |
T2 |
154068 |
2 |
0 |
0 |
T3 |
503617 |
0 |
0 |
0 |
T6 |
359075 |
1 |
0 |
0 |
T7 |
384364 |
2 |
0 |
0 |
T8 |
392782 |
3 |
0 |
0 |
T9 |
114913 |
0 |
0 |
0 |
T10 |
619324 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
10872 |
0 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
1899 |
0 |
0 |
T1 |
33399 |
1 |
0 |
0 |
T2 |
71391 |
2 |
0 |
0 |
T3 |
1037 |
0 |
0 |
0 |
T6 |
32642 |
1 |
0 |
0 |
T7 |
64059 |
2 |
0 |
0 |
T8 |
97902 |
3 |
0 |
0 |
T9 |
23940 |
0 |
0 |
0 |
T10 |
53244 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
86 |
0 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T1,T2,T6 |
1 | 1 | Covered | T2,T7,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T2,T7,T8 |
1 | 1 | Covered | T1,T2,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
1841 |
0 |
0 |
T1 |
33399 |
1 |
0 |
0 |
T2 |
71391 |
2 |
0 |
0 |
T3 |
1037 |
0 |
0 |
0 |
T6 |
32642 |
1 |
0 |
0 |
T7 |
64059 |
2 |
0 |
0 |
T8 |
97902 |
3 |
0 |
0 |
T9 |
23940 |
0 |
0 |
0 |
T10 |
53244 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
86 |
0 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1963 |
0 |
0 |
T1 |
158655 |
1 |
0 |
0 |
T2 |
154068 |
2 |
0 |
0 |
T3 |
503617 |
0 |
0 |
0 |
T6 |
359075 |
1 |
0 |
0 |
T7 |
384364 |
2 |
0 |
0 |
T8 |
392782 |
3 |
0 |
0 |
T9 |
114913 |
0 |
0 |
0 |
T10 |
619324 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
10872 |
0 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T1,T2,T6 |
1 | 1 | Covered | T2,T7,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T2,T7,T8 |
1 | 1 | Covered | T1,T2,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1951 |
0 |
0 |
T1 |
158655 |
1 |
0 |
0 |
T2 |
154068 |
2 |
0 |
0 |
T3 |
503617 |
0 |
0 |
0 |
T6 |
359075 |
1 |
0 |
0 |
T7 |
384364 |
2 |
0 |
0 |
T8 |
392782 |
3 |
0 |
0 |
T9 |
114913 |
0 |
0 |
0 |
T10 |
619324 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
10872 |
0 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
1951 |
0 |
0 |
T1 |
33399 |
1 |
0 |
0 |
T2 |
71391 |
2 |
0 |
0 |
T3 |
1037 |
0 |
0 |
0 |
T6 |
32642 |
1 |
0 |
0 |
T7 |
64059 |
2 |
0 |
0 |
T8 |
97902 |
3 |
0 |
0 |
T9 |
23940 |
0 |
0 |
0 |
T10 |
53244 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
86 |
0 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T1,T2,T6 |
1 | 1 | Covered | T2,T7,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T2,T7,T8 |
1 | 1 | Covered | T1,T2,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
1829 |
0 |
0 |
T1 |
33399 |
1 |
0 |
0 |
T2 |
71391 |
2 |
0 |
0 |
T3 |
1037 |
0 |
0 |
0 |
T6 |
32642 |
1 |
0 |
0 |
T7 |
64059 |
2 |
0 |
0 |
T8 |
97902 |
3 |
0 |
0 |
T9 |
23940 |
0 |
0 |
0 |
T10 |
53244 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
86 |
0 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1950 |
0 |
0 |
T1 |
158655 |
1 |
0 |
0 |
T2 |
154068 |
2 |
0 |
0 |
T3 |
503617 |
0 |
0 |
0 |
T6 |
359075 |
1 |
0 |
0 |
T7 |
384364 |
2 |
0 |
0 |
T8 |
392782 |
3 |
0 |
0 |
T9 |
114913 |
0 |
0 |
0 |
T10 |
619324 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
10872 |
0 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T1,T2,T6 |
1 | 1 | Covered | T2,T7,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T2,T7,T8 |
1 | 1 | Covered | T1,T2,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1937 |
0 |
0 |
T1 |
158655 |
1 |
0 |
0 |
T2 |
154068 |
2 |
0 |
0 |
T3 |
503617 |
0 |
0 |
0 |
T6 |
359075 |
1 |
0 |
0 |
T7 |
384364 |
2 |
0 |
0 |
T8 |
392782 |
3 |
0 |
0 |
T9 |
114913 |
0 |
0 |
0 |
T10 |
619324 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
10872 |
0 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
1937 |
0 |
0 |
T1 |
33399 |
1 |
0 |
0 |
T2 |
71391 |
2 |
0 |
0 |
T3 |
1037 |
0 |
0 |
0 |
T6 |
32642 |
1 |
0 |
0 |
T7 |
64059 |
2 |
0 |
0 |
T8 |
97902 |
3 |
0 |
0 |
T9 |
23940 |
0 |
0 |
0 |
T10 |
53244 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
86 |
0 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T1,T2,T6 |
1 | 1 | Covered | T2,T7,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T2,T7,T8 |
1 | 1 | Covered | T1,T2,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
1851 |
0 |
0 |
T1 |
33399 |
1 |
0 |
0 |
T2 |
71391 |
2 |
0 |
0 |
T3 |
1037 |
0 |
0 |
0 |
T6 |
32642 |
1 |
0 |
0 |
T7 |
64059 |
2 |
0 |
0 |
T8 |
97902 |
3 |
0 |
0 |
T9 |
23940 |
0 |
0 |
0 |
T10 |
53244 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
86 |
0 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1973 |
0 |
0 |
T1 |
158655 |
1 |
0 |
0 |
T2 |
154068 |
2 |
0 |
0 |
T3 |
503617 |
0 |
0 |
0 |
T6 |
359075 |
1 |
0 |
0 |
T7 |
384364 |
2 |
0 |
0 |
T8 |
392782 |
3 |
0 |
0 |
T9 |
114913 |
0 |
0 |
0 |
T10 |
619324 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
10872 |
0 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T1,T2,T6 |
1 | 1 | Covered | T2,T7,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T2,T7,T8 |
1 | 1 | Covered | T1,T2,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1964 |
0 |
0 |
T1 |
158655 |
1 |
0 |
0 |
T2 |
154068 |
2 |
0 |
0 |
T3 |
503617 |
0 |
0 |
0 |
T6 |
359075 |
1 |
0 |
0 |
T7 |
384364 |
2 |
0 |
0 |
T8 |
392782 |
3 |
0 |
0 |
T9 |
114913 |
0 |
0 |
0 |
T10 |
619324 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
10872 |
0 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
1964 |
0 |
0 |
T1 |
33399 |
1 |
0 |
0 |
T2 |
71391 |
2 |
0 |
0 |
T3 |
1037 |
0 |
0 |
0 |
T6 |
32642 |
1 |
0 |
0 |
T7 |
64059 |
2 |
0 |
0 |
T8 |
97902 |
3 |
0 |
0 |
T9 |
23940 |
0 |
0 |
0 |
T10 |
53244 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
86 |
0 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T1,T2,T6 |
1 | 1 | Covered | T2,T7,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T2,T7,T8 |
1 | 1 | Covered | T1,T2,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
1840 |
0 |
0 |
T1 |
33399 |
1 |
0 |
0 |
T2 |
71391 |
2 |
0 |
0 |
T3 |
1037 |
0 |
0 |
0 |
T6 |
32642 |
1 |
0 |
0 |
T7 |
64059 |
2 |
0 |
0 |
T8 |
97902 |
3 |
0 |
0 |
T9 |
23940 |
0 |
0 |
0 |
T10 |
53244 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
86 |
0 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1960 |
0 |
0 |
T1 |
158655 |
1 |
0 |
0 |
T2 |
154068 |
2 |
0 |
0 |
T3 |
503617 |
0 |
0 |
0 |
T6 |
359075 |
1 |
0 |
0 |
T7 |
384364 |
2 |
0 |
0 |
T8 |
392782 |
3 |
0 |
0 |
T9 |
114913 |
0 |
0 |
0 |
T10 |
619324 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
10872 |
0 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T1,T2,T6 |
1 | 1 | Covered | T2,T7,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T2,T7,T8 |
1 | 1 | Covered | T1,T2,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1949 |
0 |
0 |
T1 |
158655 |
1 |
0 |
0 |
T2 |
154068 |
2 |
0 |
0 |
T3 |
503617 |
0 |
0 |
0 |
T6 |
359075 |
1 |
0 |
0 |
T7 |
384364 |
2 |
0 |
0 |
T8 |
392782 |
3 |
0 |
0 |
T9 |
114913 |
0 |
0 |
0 |
T10 |
619324 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
10872 |
0 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
1949 |
0 |
0 |
T1 |
33399 |
1 |
0 |
0 |
T2 |
71391 |
2 |
0 |
0 |
T3 |
1037 |
0 |
0 |
0 |
T6 |
32642 |
1 |
0 |
0 |
T7 |
64059 |
2 |
0 |
0 |
T8 |
97902 |
3 |
0 |
0 |
T9 |
23940 |
0 |
0 |
0 |
T10 |
53244 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
86 |
0 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T1,T2,T6 |
1 | 1 | Covered | T2,T7,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T2,T7,T8 |
1 | 1 | Covered | T1,T2,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
1823 |
0 |
0 |
T1 |
33399 |
1 |
0 |
0 |
T2 |
71391 |
2 |
0 |
0 |
T3 |
1037 |
0 |
0 |
0 |
T6 |
32642 |
1 |
0 |
0 |
T7 |
64059 |
2 |
0 |
0 |
T8 |
97902 |
3 |
0 |
0 |
T9 |
23940 |
0 |
0 |
0 |
T10 |
53244 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
86 |
0 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1943 |
0 |
0 |
T1 |
158655 |
1 |
0 |
0 |
T2 |
154068 |
2 |
0 |
0 |
T3 |
503617 |
0 |
0 |
0 |
T6 |
359075 |
1 |
0 |
0 |
T7 |
384364 |
2 |
0 |
0 |
T8 |
392782 |
3 |
0 |
0 |
T9 |
114913 |
0 |
0 |
0 |
T10 |
619324 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
10872 |
0 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T1,T2,T6 |
1 | 1 | Covered | T2,T7,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T2,T7,T8 |
1 | 1 | Covered | T1,T2,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1931 |
0 |
0 |
T1 |
158655 |
1 |
0 |
0 |
T2 |
154068 |
2 |
0 |
0 |
T3 |
503617 |
0 |
0 |
0 |
T6 |
359075 |
1 |
0 |
0 |
T7 |
384364 |
2 |
0 |
0 |
T8 |
392782 |
3 |
0 |
0 |
T9 |
114913 |
0 |
0 |
0 |
T10 |
619324 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
10872 |
0 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
1931 |
0 |
0 |
T1 |
33399 |
1 |
0 |
0 |
T2 |
71391 |
2 |
0 |
0 |
T3 |
1037 |
0 |
0 |
0 |
T6 |
32642 |
1 |
0 |
0 |
T7 |
64059 |
2 |
0 |
0 |
T8 |
97902 |
3 |
0 |
0 |
T9 |
23940 |
0 |
0 |
0 |
T10 |
53244 |
4 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
86 |
0 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T2,T8,T10 |
1 | 0 | Covered | T2,T8,T10 |
1 | 1 | Covered | T2,T8,T13 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T2,T8,T10 |
1 | 0 | Covered | T2,T8,T13 |
1 | 1 | Covered | T2,T8,T10 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
1313 |
0 |
0 |
T2 |
71391 |
2 |
0 |
0 |
T3 |
1037 |
0 |
0 |
0 |
T6 |
32642 |
0 |
0 |
0 |
T7 |
64059 |
0 |
0 |
0 |
T8 |
97902 |
3 |
0 |
0 |
T9 |
23940 |
0 |
0 |
0 |
T10 |
53244 |
3 |
0 |
0 |
T11 |
7646 |
1 |
0 |
0 |
T12 |
4584 |
0 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
T28 |
0 |
2 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1437 |
0 |
0 |
T2 |
154068 |
2 |
0 |
0 |
T3 |
503617 |
0 |
0 |
0 |
T6 |
359075 |
0 |
0 |
0 |
T7 |
384364 |
0 |
0 |
0 |
T8 |
392782 |
3 |
0 |
0 |
T9 |
114913 |
0 |
0 |
0 |
T10 |
619324 |
3 |
0 |
0 |
T11 |
382379 |
1 |
0 |
0 |
T12 |
550174 |
0 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
T28 |
0 |
2 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T2,T8,T10 |
1 | 0 | Covered | T2,T8,T10 |
1 | 1 | Covered | T2,T8,T13 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T2,T8,T10 |
1 | 0 | Covered | T2,T8,T13 |
1 | 1 | Covered | T2,T8,T10 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1425 |
0 |
0 |
T2 |
154068 |
2 |
0 |
0 |
T3 |
503617 |
0 |
0 |
0 |
T6 |
359075 |
0 |
0 |
0 |
T7 |
384364 |
0 |
0 |
0 |
T8 |
392782 |
3 |
0 |
0 |
T9 |
114913 |
0 |
0 |
0 |
T10 |
619324 |
3 |
0 |
0 |
T11 |
382379 |
1 |
0 |
0 |
T12 |
550174 |
0 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
T28 |
0 |
2 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
1425 |
0 |
0 |
T2 |
71391 |
2 |
0 |
0 |
T3 |
1037 |
0 |
0 |
0 |
T6 |
32642 |
0 |
0 |
0 |
T7 |
64059 |
0 |
0 |
0 |
T8 |
97902 |
3 |
0 |
0 |
T9 |
23940 |
0 |
0 |
0 |
T10 |
53244 |
3 |
0 |
0 |
T11 |
7646 |
1 |
0 |
0 |
T12 |
4584 |
0 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
3 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
T28 |
0 |
2 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T1,T2,T6 |
1 | 1 | Covered | T1,T2,T6 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T6 |
1 | 0 | Covered | T1,T2,T6 |
1 | 1 | Covered | T1,T2,T6 |
Branch Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35121928 |
66791 |
0 |
0 |
T1 |
33399 |
67 |
0 |
0 |
T2 |
71391 |
131 |
0 |
0 |
T3 |
1037 |
0 |
0 |
0 |
T6 |
32642 |
77 |
0 |
0 |
T7 |
64059 |
175 |
0 |
0 |
T8 |
97902 |
84 |
0 |
0 |
T9 |
23940 |
0 |
0 |
0 |
T10 |
53244 |
89 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
242 |
0 |
0 |
T14 |
0 |
81 |
0 |
0 |
T15 |
0 |
97 |
0 |
0 |
T16 |
86 |
0 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
66917 |
0 |
0 |
T1 |
158655 |
67 |
0 |
0 |
T2 |
154068 |
131 |
0 |
0 |
T3 |
503617 |
0 |
0 |
0 |
T6 |
359075 |
77 |
0 |
0 |
T7 |
384364 |
175 |
0 |
0 |
T8 |
392782 |
84 |
0 |
0 |
T9 |
114913 |
0 |
0 |
0 |
T10 |
619324 |
89 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T13 |
0 |
242 |
0 |
0 |
T14 |
0 |
81 |
0 |
0 |
T15 |
0 |
97 |
0 |
0 |
T16 |
10872 |
0 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_adc_ctrl_core.u_oneshot_done_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_adc_ctrl_core.u_oneshot_done_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T3,T9,T11 |
1 | 0 | Covered | T3,T9,T11 |
1 | 1 | Covered | T3,T9,T11 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T3,T9,T11 |
1 | 0 | Covered | T3,T9,T11 |
1 | 1 | Covered | T3,T9,T11 |
Branch Coverage for Instance : tb.dut.u_adc_ctrl_core.u_oneshot_done_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_adc_ctrl_core.u_oneshot_done_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
7087 |
0 |
0 |
T3 |
503617 |
9 |
0 |
0 |
T6 |
359075 |
0 |
0 |
0 |
T7 |
384364 |
0 |
0 |
0 |
T8 |
392782 |
0 |
0 |
0 |
T9 |
114913 |
59 |
0 |
0 |
T10 |
619324 |
0 |
0 |
0 |
T11 |
382379 |
21 |
0 |
0 |
T12 |
550174 |
0 |
0 |
0 |
T13 |
144405 |
0 |
0 |
0 |
T17 |
192820 |
0 |
0 |
0 |
T30 |
0 |
10 |
0 |
0 |
T31 |
0 |
20 |
0 |
0 |
T42 |
0 |
34 |
0 |
0 |
T43 |
0 |
41 |
0 |
0 |
T45 |
0 |
67 |
0 |
0 |
T79 |
0 |
20 |
0 |
0 |
T103 |
0 |
20 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
35041362 |
7092 |
0 |
0 |
T3 |
1037 |
9 |
0 |
0 |
T6 |
32642 |
0 |
0 |
0 |
T7 |
64059 |
0 |
0 |
0 |
T8 |
97902 |
0 |
0 |
0 |
T9 |
23940 |
59 |
0 |
0 |
T10 |
53244 |
0 |
0 |
0 |
T11 |
7646 |
21 |
0 |
0 |
T12 |
4584 |
0 |
0 |
0 |
T13 |
120338 |
0 |
0 |
0 |
T17 |
1541 |
0 |
0 |
0 |
T30 |
0 |
10 |
0 |
0 |
T31 |
0 |
20 |
0 |
0 |
T42 |
0 |
34 |
0 |
0 |
T43 |
0 |
41 |
0 |
0 |
T45 |
0 |
67 |
0 |
0 |
T79 |
0 |
20 |
0 |
0 |
T103 |
0 |
20 |
0 |
0 |