Unified Coverage Report :: Module :: adc_ctrl_core

Module : adc_ctrl_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_adc_ctrl_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.83	100.00	99.76		100.00	99.37	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_ctrl_fsm	99.75	100.00	100.00		100.00	98.73	100.00
u_adc_ctrl_intr	99.00	100.00	96.00			100.00	100.00
u_oneshot_done_sync	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
TOTAL		63	63	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	73	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	213	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	8	8
63	8	8
72	1	1
73	1	1
74	1	1
75	1	1
83	1	1
86	1	1
87	1	1
88	1	1
89	1	1
104	8	8
107	8	8
117	8	8
121	8	8
137	1	1
138	1	1
140	1	1
141	1	1
145	1	1
213	1	1

---

Cond Coverage for Module : adc_ctrl_core

	Total	Covered	Percent
Conditions	293	293	100.00
Logical	293	293	100.00
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION (reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done : (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0))
             -----------------1----------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T9,T11

 LINE       83
 SUB-EXPRESSION (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0)
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][0].cond)) ? ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v)) : ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v)))

-1-	Status	Tests
0	Covered	T2,T10,T14
1	Covered	T4,T5,T1

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T1

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T10,T14
0	1	Covered	T2,T10,T14
1	0	Covered	T2,T10,T14

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][1].cond)) ? ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v)) : ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v)))

-1-	Status	Tests
0	Covered	T2,T6,T8
1	Covered	T4,T5,T1

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T3,T7
1	1	Covered	T4,T5,T1

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T8
0	1	Covered	T2,T6,T8
1	0	Covered	T2,T6,T8

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][2].cond)) ? ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v)) : ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v)))

-1-	Status	Tests
0	Covered	T1,T2,T14
1	Covered	T4,T5,T1

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Covered	T2,T3,T6
1	1	Covered	T4,T5,T1

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T14
0	1	Covered	T1,T2,T14
1	0	Covered	T1,T2,T14

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][3].cond)) ? ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v)) : ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v)))

-1-	Status	Tests
0	Covered	T2,T6,T8
1	Covered	T4,T5,T1

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T1

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T8
0	1	Covered	T2,T6,T8
1	0	Covered	T2,T6,T8

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][4].cond)) ? ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v)) : ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v)))

-1-	Status	Tests
0	Covered	T2,T6,T8
1	Covered	T4,T5,T1

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T3,T7
1	1	Covered	T4,T5,T1

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T8
0	1	Covered	T2,T6,T8
1	0	Covered	T2,T6,T8

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][5].cond)) ? ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v)) : ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v)))

-1-	Status	Tests
0	Covered	T1,T6,T8
1	Covered	T4,T5,T1

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Covered	T2,T3,T7
1	1	Covered	T4,T5,T1

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T8
0	1	Covered	T1,T6,T8
1	0	Covered	T1,T6,T8

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][6].cond)) ? ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v)) : ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v)))

-1-	Status	Tests
0	Covered	T8,T10,T11
1	Covered	T4,T5,T1

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T1

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T14
0	1	Covered	T8,T10,T28
1	0	Covered	T8,T10,T11

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][7].cond)) ? ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v)) : ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v)))

-1-	Status	Tests
0	Covered	T2,T6,T7
1	Covered	T4,T5,T1

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T1

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T7
0	1	Covered	T2,T6,T7
1	0	Covered	T2,T6,T7

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][0].cond)) ? ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v)) : ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v)))

-1-	Status	Tests
0	Covered	T1,T10,T14
1	Covered	T4,T5,T1

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Covered	T2,T3,T6
1	1	Covered	T4,T5,T1

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T14
0	1	Covered	T1,T10,T14
1	0	Covered	T1,T10,T14

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][1].cond)) ? ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v)) : ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v)))

-1-	Status	Tests
0	Covered	T2,T6,T8
1	Covered	T4,T5,T1

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T10
1	0	Covered	T1,T3,T7
1	1	Covered	T4,T5,T1

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T8
0	1	Covered	T2,T6,T8
1	0	Covered	T2,T6,T8

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][2].cond)) ? ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v)) : ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v)))

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T4,T5,T1

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Covered	T2,T3,T6
1	1	Covered	T4,T5,T1

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T8

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][3].cond)) ? ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v)) : ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v)))

-1-	Status	Tests
0	Covered	T2,T6,T8
1	Covered	T4,T5,T1

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T1

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T8
0	1	Covered	T2,T6,T8
1	0	Covered	T2,T6,T8

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][4].cond)) ? ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v)) : ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v)))

-1-	Status	Tests
0	Covered	T2,T6,T8
1	Covered	T4,T5,T1

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T3,T7
1	1	Covered	T4,T5,T1

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T8
0	1	Covered	T2,T6,T8
1	0	Covered	T2,T6,T8

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][5].cond)) ? ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v)) : ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v)))

-1-	Status	Tests
0	Covered	T1,T6,T8
1	Covered	T4,T5,T1

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Covered	T2,T3,T7
1	1	Covered	T4,T5,T1

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T8
0	1	Covered	T1,T6,T8
1	0	Covered	T1,T6,T8

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][6].cond)) ? ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v)) : ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v)))

-1-	Status	Tests
0	Covered	T8,T10,T11
1	Covered	T4,T5,T1

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T1

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T14
0	1	Covered	T8,T10,T14
1	0	Covered	T8,T10,T11

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][7].cond)) ? ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v)) : ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v)))

-1-	Status	Tests
0	Covered	T2,T6,T7
1	Covered	T4,T5,T1

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T1

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T7
0	1	Covered	T2,T6,T7
1	0	Covered	T2,T6,T7

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][0].en, aon_filter_ctl[1][0].en})) & 
      2  (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en)) & 
      3  (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T6,T7,T8
1	1	0	Covered	T2,T6,T7
1	1	1	Covered	T2,T6,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T7
0	1	Covered	T2,T6,T7
1	0	Covered	T4,T5,T1

 LINE       117
 SUB-EXPRESSION (chn0_match[0] & aon_filter_ctl[0][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Covered	T4,T5,T1
1	1	Covered	T2,T6,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T7
0	1	Covered	T2,T6,T7
1	0	Covered	T4,T5,T1

 LINE       117
 SUB-EXPRESSION (chn1_match[0] & aon_filter_ctl[1][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Covered	T4,T5,T1
1	1	Covered	T2,T6,T7

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][1].en, aon_filter_ctl[1][1].en})) & 
      2  (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en)) & 
      3  (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T2,T7,T8
1	1	0	Covered	T2,T7,T8
1	1	1	Covered	T2,T7,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T8
0	1	Covered	T2,T7,T8
1	0	Covered	T4,T5,T1

 LINE       117
 SUB-EXPRESSION (chn0_match[1] & aon_filter_ctl[0][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Covered	T4,T5,T1
1	1	Covered	T2,T7,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T8
0	1	Covered	T2,T7,T8
1	0	Covered	T4,T5,T1

 LINE       117
 SUB-EXPRESSION (chn1_match[1] & aon_filter_ctl[1][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Covered	T4,T5,T1
1	1	Covered	T2,T7,T8

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][2].en, aon_filter_ctl[1][2].en})) & 
      2  (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en)) & 
      3  (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T2,T7,T8
1	1	0	Covered	T2,T7,T8
1	1	1	Covered	T2,T7,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T8
0	1	Covered	T2,T7,T8
1	0	Covered	T4,T5,T1

 LINE       117
 SUB-EXPRESSION (chn0_match[2] & aon_filter_ctl[0][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Covered	T4,T5,T1
1	1	Covered	T2,T7,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T8
0	1	Covered	T2,T7,T8
1	0	Covered	T4,T5,T1

 LINE       117
 SUB-EXPRESSION (chn1_match[2] & aon_filter_ctl[1][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Covered	T4,T5,T1
1	1	Covered	T2,T7,T8

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][3].en, aon_filter_ctl[1][3].en})) & 
      2  (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en)) & 
      3  (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T1,T6,T7
1	1	0	Covered	T1,T6,T7
1	1	1	Covered	T1,T6,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T6,T7
1	0	Covered	T4,T5,T1

 LINE       117
 SUB-EXPRESSION (chn0_match[3] & aon_filter_ctl[0][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T4,T5,T1
1	1	Covered	T1,T6,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T6,T7
1	0	Covered	T4,T5,T1

 LINE       117
 SUB-EXPRESSION (chn1_match[3] & aon_filter_ctl[1][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T4,T5,T1
1	1	Covered	T1,T6,T7

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][4].en, aon_filter_ctl[1][4].en})) & 
      2  (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en)) & 
      3  (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T1,T7,T8
1	1	0	Covered	T1,T7,T8
1	1	1	Covered	T1,T7,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Covered	T1,T7,T8
1	0	Covered	T4,T5,T1

 LINE       117
 SUB-EXPRESSION (chn0_match[4] & aon_filter_ctl[0][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Covered	T4,T5,T1
1	1	Covered	T1,T7,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Covered	T1,T7,T8
1	0	Covered	T4,T5,T1

 LINE       117
 SUB-EXPRESSION (chn1_match[4] & aon_filter_ctl[1][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Covered	T4,T5,T1
1	1	Covered	T1,T7,T8

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][5].en, aon_filter_ctl[1][5].en})) & 
      2  (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en)) & 
      3  (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T1,T2,T6
1	1	0	Covered	T1,T2,T6
1	1	1	Covered	T1,T2,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Covered	T1,T2,T6
1	0	Covered	T4,T5,T1

 LINE       117
 SUB-EXPRESSION (chn0_match[5] & aon_filter_ctl[0][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T4,T5,T1
1	1	Covered	T1,T2,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Covered	T1,T2,T6
1	0	Covered	T4,T5,T1

 LINE       117
 SUB-EXPRESSION (chn1_match[5] & aon_filter_ctl[1][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T4,T5,T1
1	1	Covered	T1,T2,T6

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][6].en, aon_filter_ctl[1][6].en})) & 
      2  (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en)) & 
      3  (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T2,T6,T7
1	1	0	Covered	T2,T6,T7
1	1	1	Covered	T2,T6,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T7
0	1	Covered	T2,T6,T7
1	0	Covered	T4,T5,T1

 LINE       117
 SUB-EXPRESSION (chn0_match[6] & aon_filter_ctl[0][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Covered	T4,T5,T1
1	1	Covered	T2,T6,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T7
0	1	Covered	T2,T6,T7
1	0	Covered	T4,T5,T1

 LINE       117
 SUB-EXPRESSION (chn1_match[6] & aon_filter_ctl[1][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Covered	T4,T5,T1
1	1	Covered	T2,T6,T7

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][7].en, aon_filter_ctl[1][7].en})) & 
      2  (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en)) & 
      3  (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T2,T7,T8
1	1	0	Covered	T2,T7,T8
1	1	1	Covered	T2,T7,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T8
0	1	Covered	T2,T7,T8
1	0	Covered	T4,T5,T1

 LINE       117
 SUB-EXPRESSION (chn0_match[7] & aon_filter_ctl[0][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Covered	T4,T5,T1
1	1	Covered	T2,T7,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T8
0	1	Covered	T2,T7,T8
1	0	Covered	T4,T5,T1

 LINE       117
 SUB-EXPRESSION (chn1_match[7] & aon_filter_ctl[1][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Covered	T4,T5,T1
1	1	Covered	T2,T7,T8

 LINE       121
 EXPRESSION (adc_ctrl_done && match[0])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Covered	T1,T2,T6
1	1	Covered	T2,T6,T7

 LINE       121
 EXPRESSION (adc_ctrl_done && match[1])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Covered	T1,T2,T6
1	1	Covered	T2,T7,T8

 LINE       121
 EXPRESSION (adc_ctrl_done && match[2])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Covered	T1,T2,T6
1	1	Covered	T2,T7,T8

 LINE       121
 EXPRESSION (adc_ctrl_done && match[3])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T6,T7

 LINE       121
 EXPRESSION (adc_ctrl_done && match[4])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T7,T8

 LINE       121
 EXPRESSION (adc_ctrl_done && match[5])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T2,T6,T7
1	1	Covered	T1,T2,T6

 LINE       121
 EXPRESSION (adc_ctrl_done && match[6])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Covered	T1,T2,T6
1	1	Covered	T2,T6,T7

 LINE       121
 EXPRESSION (adc_ctrl_done && match[7])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Covered	T1,T2,T6
1	1	Covered	T7,T8,T10

 LINE       140
 EXPRESSION (aon_fsm_trans | reg2hw_i.filter_status.trans.q)
             ------1------   ---------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T2,T10,T13
1	0	Covered	T2,T10,T13

 LINE       145
 EXPRESSION (((|(reg2hw_i.filter_status.match.q & reg2hw_i.adc_wakeup_ctl.match_en.q))) || (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q))
             -------------------------------------1------------------------------------    ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T13,T14,T40
1	0	Covered	T2,T8,T10

 LINE       145
 SUB-EXPRESSION (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q)
                 ---------------1--------------   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T13,T14
1	0	Covered	T2,T10,T13
1	1	Covered	T13,T14,T40

---

Branch Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	83	3	3	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	83	(reg2hw_i.adc_en_ctl.oneshot_mode.q) ? 
-2-:	83	(reg2hw_i.adc_en_ctl.adc_enable.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T9,T11
0	1	Covered	T1,T2,T3
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T2,T10,T14

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T1,T10,T14

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T2,T6,T8

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T2,T6,T8

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T1,T2,T14

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T1,T2,T8

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T2,T6,T8

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T2,T6,T8

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T2,T6,T8

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T2,T6,T8

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T1,T6,T8

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T1,T6,T8

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T8,T10,T11

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T8,T10,T11

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T2,T6,T7

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T2,T6,T7

---

Assert Coverage for Module : adc_ctrl_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	33	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	33	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxFilters_A	35041362	34706610	0	0
gen_filter_match[0].MatchCheck00_A	35041362	9975457	0	0
gen_filter_match[0].MatchCheck01_A	35041362	3231991	0	0
gen_filter_match[0].MatchCheck10_A	35041362	3092147	0	0
gen_filter_match[0].MatchCheck11_A	35041362	18407015	0	0
gen_filter_match[1].MatchCheck00_A	35041362	11637228	0	0
gen_filter_match[1].MatchCheck01_A	35041362	710375	0	0
gen_filter_match[1].MatchCheck10_A	35041362	1133738	0	0
gen_filter_match[1].MatchCheck11_A	35041362	21225269	0	0
gen_filter_match[2].MatchCheck00_A	35041362	12228482	0	0
gen_filter_match[2].MatchCheck01_A	35041362	662231	0	0
gen_filter_match[2].MatchCheck10_A	35041362	794406	0	0
gen_filter_match[2].MatchCheck11_A	35041362	21021491	0	0
gen_filter_match[3].MatchCheck00_A	35041362	13141724	0	0
gen_filter_match[3].MatchCheck01_A	35041362	341731	0	0
gen_filter_match[3].MatchCheck10_A	35041362	259114	0	0
gen_filter_match[3].MatchCheck11_A	35041362	20964041	0	0
gen_filter_match[4].MatchCheck00_A	35041362	13076100	0	0
gen_filter_match[4].MatchCheck01_A	35041362	32539	0	0
gen_filter_match[4].MatchCheck10_A	35041362	32880	0	0
gen_filter_match[4].MatchCheck11_A	35041362	21565091	0	0
gen_filter_match[5].MatchCheck00_A	35041362	13337986	0	0
gen_filter_match[5].MatchCheck01_A	35041362	82420	0	0
gen_filter_match[5].MatchCheck10_A	35041362	32716	0	0
gen_filter_match[5].MatchCheck11_A	35041362	21253488	0	0
gen_filter_match[6].MatchCheck00_A	35041362	13326015	0	0
gen_filter_match[6].MatchCheck01_A	35041362	72931	0	0
gen_filter_match[6].MatchCheck10_A	35041362	65560	0	0
gen_filter_match[6].MatchCheck11_A	35041362	21242104	0	0
gen_filter_match[7].MatchCheck00_A	35041362	12659478	0	0
gen_filter_match[7].MatchCheck01_A	35041362	169413	0	0
gen_filter_match[7].MatchCheck10_A	35041362	212894	0	0
gen_filter_match[7].MatchCheck11_A	35041362	21664825	0	0

MaxFilters_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35041362	34706610	0	0
T1	33399	33328	0	0
T2	71391	71323	0	0
T3	1037	952	0	0
T4	87	8	0	0
T5	64	10	0	0
T6	32642	32579	0	0
T7	64059	64004	0	0
T8	97902	97838	0	0
T16	86	8	0	0
T17	1541	19	0	0

gen_filter_match[0].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35041362	9975457	0	0
T1	33399	33328	0	0
T2	71391	4	0	0
T3	1037	952	0	0
T4	87	8	0	0
T5	64	10	0	0
T6	32642	3	0	0
T7	64059	4	0	0
T8	97902	4	0	0
T16	86	8	0	0
T17	1541	19	0	0

gen_filter_match[0].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35041362	3231991	0	0
T2	71391	38512	0	0
T3	1037	0	0	0
T6	32642	0	0	0
T7	64059	0	0	0
T8	97902	0	0	0
T9	23940	0	0	0
T10	53244	37802	0	0
T11	7646	0	0	0
T12	4584	0	0	0
T17	1541	0	0	0
T36	0	15768	0	0
T40	0	39877	0	0
T41	0	34492	0	0
T45	0	238236	0	0
T46	0	32916	0	0
T105	0	32303	0	0
T106	0	32072	0	0
T107	0	32062	0	0

gen_filter_match[0].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35041362	3092147	0	0
T7	64059	1	0	0
T8	97902	0	0	0
T9	23940	0	0	0
T10	53244	0	0	0
T11	7646	3542	0	0
T12	4584	0	0	0
T13	120338	0	0	0
T14	103726	0	0	0
T15	0	33093	0	0
T17	1541	0	0	0
T27	5440	0	0	0
T33	0	32738	0	0
T80	0	33137	0	0
T108	0	33121	0	0
T109	0	3	0	0
T110	0	37952	0	0
T111	0	33500	0	0
T112	0	32336	0	0

gen_filter_match[0].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35041362	18407015	0	0
T2	71391	32807	0	0
T3	1037	0	0	0
T6	32642	32576	0	0
T7	64059	63999	0	0
T8	97902	97834	0	0
T9	23940	678	0	0
T10	53244	0	0	0
T11	7646	393	0	0
T12	4584	0	0	0
T13	0	120250	0	0
T14	0	32788	0	0
T17	1541	0	0	0
T40	0	35115	0	0
T113	0	32037	0	0

gen_filter_match[1].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35041362	11637228	0	0
T1	33399	33328	0	0
T2	71391	4	0	0
T3	1037	952	0	0
T4	87	8	0	0
T5	64	10	0	0
T6	32642	32579	0	0
T7	64059	4	0	0
T8	97902	32629	0	0
T16	86	8	0	0
T17	1541	19	0	0

gen_filter_match[1].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35041362	710375	0	0
T10	53244	9435	0	0
T11	7646	0	0	0
T12	4584	0	0	0
T13	120338	0	0	0
T14	103726	0	0	0
T15	33162	0	0	0
T27	5440	0	0	0
T28	67696	0	0	0
T29	4979	0	0	0
T30	960	0	0	0
T35	0	6310	0	0
T105	0	33256	0	0
T114	0	38272	0	0
T115	0	33804	0	0
T116	0	31683	0	0
T117	0	35656	0	0
T118	0	4881	0	0
T119	0	16468	0	0
T120	0	16401	0	0

gen_filter_match[1].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35041362	1133738	0	0
T7	64059	2	0	0
T8	97902	0	0	0
T9	23940	0	0	0
T10	53244	0	0	0
T11	7646	0	0	0
T12	4584	0	0	0
T13	120338	0	0	0
T14	103726	38151	0	0
T17	1541	0	0	0
T19	0	1	0	0
T27	5440	0	0	0
T40	0	35115	0	0
T80	0	37876	0	0
T106	0	32468	0	0
T109	0	3	0	0
T121	0	42066	0	0
T122	0	33013	0	0
T123	0	1	0	0

gen_filter_match[1].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35041362	21225269	0	0
T2	71391	71319	0	0
T3	1037	0	0	0
T6	32642	0	0	0
T7	64059	63998	0	0
T8	97902	65209	0	0
T9	23940	0	0	0
T10	53244	0	0	0
T11	7646	0	0	0
T12	4584	0	0	0
T13	0	120250	0	0
T14	0	65485	0	0
T15	0	33093	0	0
T17	1541	0	0	0
T28	0	34114	0	0
T40	0	33493	0	0
T104	0	37243	0	0
T113	0	32037	0	0

gen_filter_match[2].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35041362	12228482	0	0
T1	33399	33328	0	0
T2	71391	38516	0	0
T3	1037	952	0	0
T4	87	8	0	0
T5	64	10	0	0
T6	32642	32579	0	0
T7	64059	4	0	0
T8	97902	64625	0	0
T16	86	8	0	0
T17	1541	19	0	0

gen_filter_match[2].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35041362	662231	0	0
T8	97902	1	0	0
T9	23940	0	0	0
T10	53244	0	0	0
T11	7646	0	0	0
T12	4584	0	0	0
T13	120338	0	0	0
T14	103726	0	0	0
T15	33162	0	0	0
T17	1541	0	0	0
T27	5440	0	0	0
T35	0	1966	0	0
T107	0	1	0	0
T115	0	32934	0	0
T124	0	32055	0	0
T125	0	34972	0	0
T126	0	35556	0	0
T127	0	32336	0	0
T128	0	34113	0	0
T129	0	32821	0	0

gen_filter_match[2].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35041362	794406	0	0
T7	64059	2	0	0
T8	97902	0	0	0
T9	23940	0	0	0
T10	53244	0	0	0
T11	7646	0	0	0
T12	4584	0	0	0
T13	120338	0	0	0
T14	103726	0	0	0
T17	1541	0	0	0
T19	0	4	0	0
T27	5440	0	0	0
T36	0	12379	0	0
T40	0	2	0	0
T104	0	34100	0	0
T107	0	1	0	0
T109	0	2	0	0
T115	0	1	0	0
T122	0	37130	0	0
T123	0	1	0	0

gen_filter_match[2].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35041362	21021491	0	0
T2	71391	32807	0	0
T3	1037	0	0	0
T6	32642	0	0	0
T7	64059	63998	0	0
T8	97902	33212	0	0
T9	23940	0	0	0
T10	53244	0	0	0
T11	7646	0	0	0
T12	4584	0	0	0
T13	0	120250	0	0
T14	0	38151	0	0
T15	0	33093	0	0
T17	1541	0	0	0
T28	0	33511	0	0
T40	0	108483	0	0
T45	0	238237	0	0
T113	0	32468	0	0

gen_filter_match[3].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35041362	13141724	0	0
T1	33399	4	0	0
T2	71391	71323	0	0
T3	1037	952	0	0
T4	87	8	0	0
T5	64	10	0	0
T6	32642	3	0	0
T7	64059	4	0	0
T8	97902	65212	0	0
T16	86	8	0	0
T17	1541	19	0	0

gen_filter_match[3].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35041362	341731	0	0
T8	97902	1	0	0
T9	23940	0	0	0
T10	53244	0	0	0
T11	7646	0	0	0
T12	4584	0	0	0
T13	120338	0	0	0
T14	103726	0	0	0
T15	33162	0	0	0
T17	1541	0	0	0
T27	5440	0	0	0
T108	0	33008	0	0
T130	0	34432	0	0
T131	0	31757	0	0
T132	0	32909	0	0
T133	0	1	0	0
T134	0	2	0	0
T135	0	35001	0	0
T136	0	32334	0	0
T137	0	40739	0	0

gen_filter_match[3].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35041362	259114	0	0
T7	64059	2	0	0
T8	97902	0	0	0
T9	23940	0	0	0
T10	53244	0	0	0
T11	7646	0	0	0
T12	4584	0	0	0
T13	120338	0	0	0
T14	103726	0	0	0
T17	1541	0	0	0
T18	0	3	0	0
T19	0	4	0	0
T27	5440	0	0	0
T40	0	1	0	0
T109	0	2	0	0
T110	0	37738	0	0
T115	0	1	0	0
T123	0	2	0	0
T138	0	1	0	0
T139	0	1	0	0

gen_filter_match[3].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35041362	20964041	0	0
T1	33399	33324	0	0
T2	71391	0	0	0
T3	1037	0	0	0
T6	32642	32576	0	0
T7	64059	63998	0	0
T8	97902	32625	0	0
T9	23940	0	0	0
T10	53244	0	0	0
T11	0	3543	0	0
T13	0	120250	0	0
T14	0	103636	0	0
T16	86	0	0	0
T17	1541	0	0	0
T40	0	39876	0	0
T104	0	31825	0	0
T113	0	32037	0	0

gen_filter_match[4].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35041362	13076100	0	0
T1	33399	4	0	0
T2	71391	71323	0	0
T3	1037	952	0	0
T4	87	8	0	0
T5	64	10	0	0
T6	32642	32579	0	0
T7	64059	5	0	0
T8	97902	33215	0	0
T16	86	8	0	0
T17	1541	19	0	0

gen_filter_match[4].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35041362	32539	0	0
T8	97902	1	0	0
T9	23940	0	0	0
T10	53244	0	0	0
T11	7646	0	0	0
T12	4584	0	0	0
T13	120338	0	0	0
T14	103726	0	0	0
T15	33162	0	0	0
T17	1541	0	0	0
T27	5440	0	0	0
T140	0	32524	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	3	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	0	2	0	0

gen_filter_match[4].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35041362	32880	0	0
T7	64059	1	0	0
T8	97902	2	0	0
T9	23940	0	0	0
T10	53244	0	0	0
T11	7646	0	0	0
T12	4584	0	0	0
T13	120338	0	0	0
T14	103726	0	0	0
T17	1541	0	0	0
T18	0	5	0	0
T27	5440	0	0	0
T40	0	2	0	0
T105	0	1	0	0
T107	0	1	0	0
T109	0	3	0	0
T123	0	2	0	0
T138	0	1	0	0
T139	0	1	0	0

gen_filter_match[4].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35041362	21565091	0	0
T1	33399	33324	0	0
T2	71391	0	0	0
T3	1037	0	0	0
T6	32642	0	0	0
T7	64059	63998	0	0
T8	97902	64620	0	0
T9	23940	0	0	0
T10	53244	9435	0	0
T13	0	120250	0	0
T14	0	70939	0	0
T16	86	0	0	0
T17	1541	0	0	0
T28	0	33511	0	0
T40	0	73368	0	0
T45	0	238237	0	0
T113	0	32770	0	0

gen_filter_match[5].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35041362	13337986	0	0
T1	33399	4	0	0
T2	71391	4	0	0
T3	1037	952	0	0
T4	87	8	0	0
T5	64	10	0	0
T6	32642	3	0	0
T7	64059	5	0	0
T8	97902	4	0	0
T16	86	8	0	0
T17	1541	19	0	0

gen_filter_match[5].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35041362	82420	0	0
T38	22887	0	0	0
T107	97702	1	0	0
T111	99266	0	0	0
T124	68597	0	0	0
T140	32578	0	0	0
T141	0	2	0	0
T142	0	1	0	0
T144	0	1	0	0
T146	0	1	0	0
T149	0	1	0	0
T150	0	33060	0	0
T151	0	1	0	0
T152	0	7167	0	0
T153	0	42182	0	0
T154	107806	0	0	0
T155	798	0	0	0
T156	4805	0	0	0
T157	65936	0	0	0
T158	901	0	0	0

gen_filter_match[5].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35041362	32716	0	0
T7	64059	1	0	0
T8	97902	1	0	0
T9	23940	0	0	0
T10	53244	1	0	0
T11	7646	0	0	0
T12	4584	0	0	0
T13	120338	0	0	0
T14	103726	0	0	0
T17	1541	0	0	0
T18	0	5	0	0
T27	5440	0	0	0
T40	0	2	0	0
T78	0	1	0	0
T107	0	1	0	0
T109	0	2	0	0
T138	0	1	0	0
T139	0	1	0	0

gen_filter_match[5].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35041362	21253488	0	0
T1	33399	33324	0	0
T2	71391	71319	0	0
T3	1037	0	0	0
T6	32642	32576	0	0
T7	64059	63998	0	0
T8	97902	97833	0	0
T9	23940	0	0	0
T10	53244	37801	0	0
T11	0	3543	0	0
T13	0	120250	0	0
T14	0	38151	0	0
T16	86	0	0	0
T17	1541	0	0	0
T28	0	67625	0	0

gen_filter_match[6].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35041362	13326015	0	0
T1	33399	33328	0	0
T2	71391	32811	0	0
T3	1037	952	0	0
T4	87	8	0	0
T5	64	10	0	0
T6	32642	3	0	0
T7	64059	5	0	0
T8	97902	65212	0	0
T16	86	8	0	0
T17	1541	19	0	0

gen_filter_match[6].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35041362	72931	0	0
T8	97902	1	0	0
T9	23940	0	0	0
T10	53244	0	0	0
T11	7646	0	0	0
T12	4584	0	0	0
T13	120338	0	0	0
T14	103726	0	0	0
T15	33162	0	0	0
T17	1541	0	0	0
T27	5440	0	0	0
T141	0	2	0	0
T142	0	1	0	0
T143	0	3	0	0
T145	0	1	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T162	0	37794	0	0
T163	0	35124	0	0

gen_filter_match[6].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35041362	65560	0	0
T7	64059	2	0	0
T8	97902	1	0	0
T9	23940	0	0	0
T10	53244	1	0	0
T11	7646	0	0	0
T12	4584	0	0	0
T13	120338	0	0	0
T14	103726	0	0	0
T17	1541	0	0	0
T27	5440	0	0	0
T35	0	1	0	0
T40	0	3	0	0
T45	0	1	0	0
T78	0	1	0	0
T105	0	1	0	0
T109	0	2	0	0
T138	0	1	0	0

gen_filter_match[6].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35041362	21242104	0	0
T2	71391	38512	0	0
T3	1037	0	0	0
T6	32642	32576	0	0
T7	64059	63997	0	0
T8	97902	32624	0	0
T9	23940	0	0	0
T10	53244	37801	0	0
T11	7646	0	0	0
T12	4584	0	0	0
T13	0	120250	0	0
T14	0	70848	0	0
T17	1541	0	0	0
T28	0	33511	0	0
T40	0	108482	0	0
T41	0	34492	0	0

gen_filter_match[7].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35041362	12659478	0	0
T1	33399	33328	0	0
T2	71391	32811	0	0
T3	1037	952	0	0
T4	87	8	0	0
T5	64	10	0	0
T6	32642	32579	0	0
T7	64059	5	0	0
T8	97902	33215	0	0
T16	86	8	0	0
T17	1541	19	0	0

gen_filter_match[7].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35041362	169413	0	0
T8	97902	1	0	0
T9	23940	0	0	0
T10	53244	0	0	0
T11	7646	0	0	0
T12	4584	0	0	0
T13	120338	0	0	0
T14	103726	0	0	0
T15	33162	0	0	0
T17	1541	0	0	0
T27	5440	0	0	0
T133	0	1	0	0
T141	0	2	0	0
T144	0	1	0	0
T146	0	1	0	0
T149	0	1	0	0
T159	0	1	0	0
T164	0	71484	0	0
T165	0	2	0	0
T166	0	1	0	0

gen_filter_match[7].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35041362	212894	0	0
T7	64059	2	0	0
T8	97902	2	0	0
T9	23940	0	0	0
T10	53244	1	0	0
T11	7646	0	0	0
T12	4584	0	0	0
T13	120338	0	0	0
T14	103726	0	0	0
T17	1541	0	0	0
T27	5440	0	0	0
T35	0	2	0	0
T40	0	1	0	0
T78	0	1	0	0
T109	0	2	0	0
T113	0	32770	0	0
T138	0	1	0	0
T167	0	32454	0	0

gen_filter_match[7].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35041362	21664825	0	0
T2	71391	38512	0	0
T3	1037	0	0	0
T6	32642	0	0	0
T7	64059	63997	0	0
T8	97902	64620	0	0
T9	23940	0	0	0
T10	53244	47236	0	0
T11	7646	0	0	0
T12	4584	0	0	0
T13	0	120250	0	0
T14	0	32697	0	0
T15	0	33093	0	0
T17	1541	0	0	0
T40	0	35114	0	0
T104	0	31825	0	0
T168	0	32807	0	0