Line Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Module :
prim_pulse_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T4,T1,T2 |
1 | 0 | Covered | T4,T1,T2 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T4,T1,T2 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T1,T2 |
Branch Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Module :
prim_pulse_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
351124 |
0 |
0 |
T1 |
5839128 |
42 |
0 |
0 |
T2 |
4627404 |
93 |
0 |
0 |
T3 |
16192321 |
42 |
0 |
0 |
T5 |
8185271 |
42 |
0 |
0 |
T6 |
5662346 |
1360 |
0 |
0 |
T7 |
5458260 |
102 |
0 |
0 |
T8 |
6203752 |
126 |
0 |
0 |
T9 |
4456193 |
42 |
0 |
0 |
T10 |
4540734 |
263 |
0 |
0 |
T11 |
17329923 |
84 |
0 |
0 |
T12 |
445580 |
108 |
0 |
0 |
T13 |
0 |
108 |
0 |
0 |
T37 |
0 |
20 |
0 |
0 |
T38 |
0 |
20 |
0 |
0 |
T39 |
2588 |
1 |
0 |
0 |
T40 |
25068 |
56 |
0 |
0 |
T41 |
90 |
0 |
0 |
0 |
T42 |
63635 |
101 |
0 |
0 |
T43 |
32933 |
0 |
0 |
0 |
T44 |
32914 |
0 |
0 |
0 |
T45 |
672 |
5 |
0 |
0 |
T46 |
0 |
1 |
0 |
0 |
T48 |
0 |
56 |
0 |
0 |
T53 |
31405 |
0 |
0 |
0 |
T54 |
911 |
6 |
0 |
0 |
T55 |
99315 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
353969 |
0 |
0 |
T1 |
5839128 |
42 |
0 |
0 |
T2 |
4385907 |
93 |
0 |
0 |
T3 |
15404051 |
42 |
0 |
0 |
T5 |
7834767 |
42 |
0 |
0 |
T6 |
5412901 |
1360 |
0 |
0 |
T7 |
5173209 |
102 |
0 |
0 |
T8 |
6067187 |
126 |
0 |
0 |
T9 |
4301818 |
42 |
0 |
0 |
T10 |
4381335 |
263 |
0 |
0 |
T11 |
16549904 |
84 |
0 |
0 |
T12 |
102428 |
108 |
0 |
0 |
T13 |
0 |
108 |
0 |
0 |
T37 |
0 |
20 |
0 |
0 |
T38 |
0 |
20 |
0 |
0 |
T39 |
129487 |
5 |
0 |
0 |
T40 |
313361 |
56 |
0 |
0 |
T41 |
7293 |
0 |
0 |
0 |
T42 |
763629 |
101 |
0 |
0 |
T43 |
159736 |
0 |
0 |
0 |
T44 |
51026 |
0 |
0 |
0 |
T45 |
63913 |
5 |
0 |
0 |
T46 |
0 |
5 |
0 |
0 |
T48 |
0 |
56 |
0 |
0 |
T53 |
109922 |
0 |
0 |
0 |
T54 |
219089 |
6 |
0 |
0 |
T55 |
134077 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 5 | 2 | 40.00 |
Logical | 5 | 2 | 40.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Unreachable | |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Unreachable | |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 5 | 2 | 40.00 |
Logical | 5 | 2 | 40.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Unreachable | |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Unreachable | |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 6 | 75.00 |
Logical | 8 | 6 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T39,T46,T47 |
1 | 0 | Covered | T39,T46,T47 |
1 | 1 | Not Covered | |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T39,T46,T47 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T39,T46,T47 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
81 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T39 |
2588 |
1 |
0 |
0 |
T40 |
25068 |
0 |
0 |
0 |
T41 |
90 |
0 |
0 |
0 |
T42 |
63635 |
0 |
0 |
0 |
T43 |
32933 |
0 |
0 |
0 |
T44 |
32914 |
0 |
0 |
0 |
T45 |
672 |
0 |
0 |
0 |
T46 |
0 |
1 |
0 |
0 |
T49 |
0 |
1 |
0 |
0 |
T50 |
0 |
1 |
0 |
0 |
T51 |
0 |
1 |
0 |
0 |
T53 |
31405 |
0 |
0 |
0 |
T54 |
911 |
0 |
0 |
0 |
T55 |
99315 |
0 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T57 |
0 |
1 |
0 |
0 |
T130 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
364 |
0 |
0 |
T14 |
0 |
5 |
0 |
0 |
T39 |
129487 |
5 |
0 |
0 |
T40 |
313361 |
0 |
0 |
0 |
T41 |
7293 |
0 |
0 |
0 |
T42 |
763629 |
0 |
0 |
0 |
T43 |
159736 |
0 |
0 |
0 |
T44 |
51026 |
0 |
0 |
0 |
T45 |
63913 |
0 |
0 |
0 |
T46 |
0 |
5 |
0 |
0 |
T47 |
0 |
5 |
0 |
0 |
T49 |
0 |
5 |
0 |
0 |
T50 |
0 |
5 |
0 |
0 |
T51 |
0 |
5 |
0 |
0 |
T52 |
0 |
10 |
0 |
0 |
T53 |
109922 |
0 |
0 |
0 |
T54 |
219089 |
0 |
0 |
0 |
T55 |
134077 |
0 |
0 |
0 |
T56 |
0 |
10 |
0 |
0 |
T57 |
0 |
8 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
39211 |
0 |
0 |
T1 |
34146 |
3 |
0 |
0 |
T2 |
1053 |
41 |
0 |
0 |
T3 |
32843 |
3 |
0 |
0 |
T5 |
41235 |
3 |
0 |
0 |
T6 |
24943 |
381 |
0 |
0 |
T7 |
1143 |
41 |
0 |
0 |
T8 |
97541 |
9 |
0 |
0 |
T9 |
41164 |
3 |
0 |
0 |
T10 |
40869 |
100 |
0 |
0 |
T11 |
67826 |
6 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
39355 |
0 |
0 |
T1 |
290250 |
3 |
0 |
0 |
T2 |
242550 |
41 |
0 |
0 |
T3 |
821113 |
3 |
0 |
0 |
T5 |
391739 |
3 |
0 |
0 |
T6 |
274388 |
381 |
0 |
0 |
T7 |
286194 |
41 |
0 |
0 |
T8 |
234106 |
9 |
0 |
0 |
T9 |
195539 |
3 |
0 |
0 |
T10 |
200268 |
100 |
0 |
0 |
T11 |
847845 |
6 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
39303 |
0 |
0 |
T1 |
290250 |
3 |
0 |
0 |
T2 |
242550 |
41 |
0 |
0 |
T3 |
821113 |
3 |
0 |
0 |
T5 |
391739 |
3 |
0 |
0 |
T6 |
274388 |
381 |
0 |
0 |
T7 |
286194 |
41 |
0 |
0 |
T8 |
234106 |
9 |
0 |
0 |
T9 |
195539 |
3 |
0 |
0 |
T10 |
200268 |
100 |
0 |
0 |
T11 |
847845 |
6 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
39310 |
0 |
0 |
T1 |
34146 |
3 |
0 |
0 |
T2 |
1053 |
41 |
0 |
0 |
T3 |
32843 |
3 |
0 |
0 |
T5 |
41235 |
3 |
0 |
0 |
T6 |
24943 |
381 |
0 |
0 |
T7 |
1143 |
41 |
0 |
0 |
T8 |
97541 |
9 |
0 |
0 |
T9 |
41164 |
3 |
0 |
0 |
T10 |
40869 |
100 |
0 |
0 |
T11 |
67826 |
6 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
18367 |
0 |
0 |
T1 |
34146 |
2 |
0 |
0 |
T2 |
1053 |
20 |
0 |
0 |
T3 |
32843 |
2 |
0 |
0 |
T5 |
41235 |
2 |
0 |
0 |
T6 |
24943 |
190 |
0 |
0 |
T7 |
1143 |
1 |
0 |
0 |
T8 |
97541 |
6 |
0 |
0 |
T9 |
41164 |
2 |
0 |
0 |
T10 |
40869 |
30 |
0 |
0 |
T11 |
67826 |
4 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
18475 |
0 |
0 |
T1 |
290250 |
2 |
0 |
0 |
T2 |
242550 |
20 |
0 |
0 |
T3 |
821113 |
2 |
0 |
0 |
T5 |
391739 |
2 |
0 |
0 |
T6 |
274388 |
190 |
0 |
0 |
T7 |
286194 |
1 |
0 |
0 |
T8 |
234106 |
6 |
0 |
0 |
T9 |
195539 |
2 |
0 |
0 |
T10 |
200268 |
30 |
0 |
0 |
T11 |
847845 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
18454 |
0 |
0 |
T1 |
290250 |
2 |
0 |
0 |
T2 |
242550 |
20 |
0 |
0 |
T3 |
821113 |
2 |
0 |
0 |
T5 |
391739 |
2 |
0 |
0 |
T6 |
274388 |
190 |
0 |
0 |
T7 |
286194 |
1 |
0 |
0 |
T8 |
234106 |
6 |
0 |
0 |
T9 |
195539 |
2 |
0 |
0 |
T10 |
200268 |
30 |
0 |
0 |
T11 |
847845 |
4 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
18454 |
0 |
0 |
T1 |
34146 |
2 |
0 |
0 |
T2 |
1053 |
20 |
0 |
0 |
T3 |
32843 |
2 |
0 |
0 |
T5 |
41235 |
2 |
0 |
0 |
T6 |
24943 |
190 |
0 |
0 |
T7 |
1143 |
1 |
0 |
0 |
T8 |
97541 |
6 |
0 |
0 |
T9 |
41164 |
2 |
0 |
0 |
T10 |
40869 |
30 |
0 |
0 |
T11 |
67826 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T4,T1,T3 |
1 | 0 | Covered | T4,T1,T3 |
1 | 1 | Covered | T6,T8,T11 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T4,T1,T3 |
1 | 0 | Covered | T6,T8,T11 |
1 | 1 | Covered | T4,T1,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
14500 |
0 |
0 |
T1 |
34146 |
1 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
1 |
0 |
0 |
T4 |
86 |
1 |
0 |
0 |
T5 |
41235 |
1 |
0 |
0 |
T6 |
24943 |
190 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
3 |
0 |
0 |
T9 |
41164 |
1 |
0 |
0 |
T10 |
40869 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
14656 |
0 |
0 |
T1 |
290250 |
1 |
0 |
0 |
T2 |
242550 |
0 |
0 |
0 |
T3 |
821113 |
1 |
0 |
0 |
T4 |
10932 |
1 |
0 |
0 |
T5 |
391739 |
1 |
0 |
0 |
T6 |
274388 |
190 |
0 |
0 |
T7 |
286194 |
0 |
0 |
0 |
T8 |
234106 |
3 |
0 |
0 |
T9 |
195539 |
1 |
0 |
0 |
T10 |
200268 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T4,T1,T3 |
1 | 0 | Covered | T4,T1,T3 |
1 | 1 | Covered | T6,T8,T11 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T4,T1,T3 |
1 | 0 | Covered | T6,T8,T11 |
1 | 1 | Covered | T4,T1,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
14605 |
0 |
0 |
T1 |
290250 |
1 |
0 |
0 |
T2 |
242550 |
0 |
0 |
0 |
T3 |
821113 |
1 |
0 |
0 |
T4 |
10932 |
1 |
0 |
0 |
T5 |
391739 |
1 |
0 |
0 |
T6 |
274388 |
190 |
0 |
0 |
T7 |
286194 |
0 |
0 |
0 |
T8 |
234106 |
3 |
0 |
0 |
T9 |
195539 |
1 |
0 |
0 |
T10 |
200268 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
14605 |
0 |
0 |
T1 |
34146 |
1 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
1 |
0 |
0 |
T4 |
86 |
1 |
0 |
0 |
T5 |
41235 |
1 |
0 |
0 |
T6 |
24943 |
190 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
3 |
0 |
0 |
T9 |
41164 |
1 |
0 |
0 |
T10 |
40869 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T4,T1,T3 |
1 | 0 | Covered | T4,T1,T3 |
1 | 1 | Covered | T6,T8,T11 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T4,T1,T3 |
1 | 0 | Covered | T6,T8,T11 |
1 | 1 | Covered | T4,T1,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
14492 |
0 |
0 |
T1 |
34146 |
1 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
1 |
0 |
0 |
T4 |
86 |
1 |
0 |
0 |
T5 |
41235 |
1 |
0 |
0 |
T6 |
24943 |
190 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
3 |
0 |
0 |
T9 |
41164 |
1 |
0 |
0 |
T10 |
40869 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
14647 |
0 |
0 |
T1 |
290250 |
1 |
0 |
0 |
T2 |
242550 |
0 |
0 |
0 |
T3 |
821113 |
1 |
0 |
0 |
T4 |
10932 |
1 |
0 |
0 |
T5 |
391739 |
1 |
0 |
0 |
T6 |
274388 |
190 |
0 |
0 |
T7 |
286194 |
0 |
0 |
0 |
T8 |
234106 |
3 |
0 |
0 |
T9 |
195539 |
1 |
0 |
0 |
T10 |
200268 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T4,T1,T3 |
1 | 0 | Covered | T4,T1,T3 |
1 | 1 | Covered | T6,T8,T11 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T4,T1,T3 |
1 | 0 | Covered | T6,T8,T11 |
1 | 1 | Covered | T4,T1,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
14598 |
0 |
0 |
T1 |
290250 |
1 |
0 |
0 |
T2 |
242550 |
0 |
0 |
0 |
T3 |
821113 |
1 |
0 |
0 |
T4 |
10932 |
1 |
0 |
0 |
T5 |
391739 |
1 |
0 |
0 |
T6 |
274388 |
190 |
0 |
0 |
T7 |
286194 |
0 |
0 |
0 |
T8 |
234106 |
3 |
0 |
0 |
T9 |
195539 |
1 |
0 |
0 |
T10 |
200268 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
14598 |
0 |
0 |
T1 |
34146 |
1 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
1 |
0 |
0 |
T4 |
86 |
1 |
0 |
0 |
T5 |
41235 |
1 |
0 |
0 |
T6 |
24943 |
190 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
3 |
0 |
0 |
T9 |
41164 |
1 |
0 |
0 |
T10 |
40869 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T1,T3,T5 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
20402 |
0 |
0 |
T1 |
34146 |
2 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
2 |
0 |
0 |
T5 |
41235 |
2 |
0 |
0 |
T6 |
24943 |
268 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
6 |
0 |
0 |
T9 |
41164 |
2 |
0 |
0 |
T10 |
40869 |
2 |
0 |
0 |
T11 |
67826 |
4 |
0 |
0 |
T12 |
0 |
6 |
0 |
0 |
T13 |
0 |
6 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
20509 |
0 |
0 |
T1 |
290250 |
2 |
0 |
0 |
T2 |
242550 |
0 |
0 |
0 |
T3 |
821113 |
2 |
0 |
0 |
T5 |
391739 |
2 |
0 |
0 |
T6 |
274388 |
268 |
0 |
0 |
T7 |
286194 |
0 |
0 |
0 |
T8 |
234106 |
6 |
0 |
0 |
T9 |
195539 |
2 |
0 |
0 |
T10 |
200268 |
2 |
0 |
0 |
T11 |
847845 |
4 |
0 |
0 |
T12 |
0 |
6 |
0 |
0 |
T13 |
0 |
6 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T1,T3,T5 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
20491 |
0 |
0 |
T1 |
290250 |
2 |
0 |
0 |
T2 |
242550 |
0 |
0 |
0 |
T3 |
821113 |
2 |
0 |
0 |
T5 |
391739 |
2 |
0 |
0 |
T6 |
274388 |
268 |
0 |
0 |
T7 |
286194 |
0 |
0 |
0 |
T8 |
234106 |
6 |
0 |
0 |
T9 |
195539 |
2 |
0 |
0 |
T10 |
200268 |
2 |
0 |
0 |
T11 |
847845 |
4 |
0 |
0 |
T12 |
0 |
6 |
0 |
0 |
T13 |
0 |
6 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
20491 |
0 |
0 |
T1 |
34146 |
2 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
2 |
0 |
0 |
T5 |
41235 |
2 |
0 |
0 |
T6 |
24943 |
268 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
6 |
0 |
0 |
T9 |
41164 |
2 |
0 |
0 |
T10 |
40869 |
2 |
0 |
0 |
T11 |
67826 |
4 |
0 |
0 |
T12 |
0 |
6 |
0 |
0 |
T13 |
0 |
6 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T8,T11,T12 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T8,T11,T12 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
1956 |
0 |
0 |
T1 |
34146 |
1 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
1 |
0 |
0 |
T5 |
41235 |
1 |
0 |
0 |
T6 |
24943 |
1 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
3 |
0 |
0 |
T9 |
41164 |
1 |
0 |
0 |
T10 |
40869 |
1 |
0 |
0 |
T11 |
67826 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2063 |
0 |
0 |
T1 |
290250 |
1 |
0 |
0 |
T2 |
242550 |
0 |
0 |
0 |
T3 |
821113 |
1 |
0 |
0 |
T5 |
391739 |
1 |
0 |
0 |
T6 |
274388 |
1 |
0 |
0 |
T7 |
286194 |
0 |
0 |
0 |
T8 |
234106 |
3 |
0 |
0 |
T9 |
195539 |
1 |
0 |
0 |
T10 |
200268 |
1 |
0 |
0 |
T11 |
847845 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T8,T11,T12 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T8,T11,T12 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2046 |
0 |
0 |
T1 |
290250 |
1 |
0 |
0 |
T2 |
242550 |
0 |
0 |
0 |
T3 |
821113 |
1 |
0 |
0 |
T5 |
391739 |
1 |
0 |
0 |
T6 |
274388 |
1 |
0 |
0 |
T7 |
286194 |
0 |
0 |
0 |
T8 |
234106 |
3 |
0 |
0 |
T9 |
195539 |
1 |
0 |
0 |
T10 |
200268 |
1 |
0 |
0 |
T11 |
847845 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
2046 |
0 |
0 |
T1 |
34146 |
1 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
1 |
0 |
0 |
T5 |
41235 |
1 |
0 |
0 |
T6 |
24943 |
1 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
3 |
0 |
0 |
T9 |
41164 |
1 |
0 |
0 |
T10 |
40869 |
1 |
0 |
0 |
T11 |
67826 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T8,T11,T12 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T8,T11,T12 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
1842 |
0 |
0 |
T1 |
34146 |
1 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
1 |
0 |
0 |
T5 |
41235 |
1 |
0 |
0 |
T6 |
24943 |
0 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
3 |
0 |
0 |
T9 |
41164 |
1 |
0 |
0 |
T10 |
40869 |
1 |
0 |
0 |
T11 |
67826 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1946 |
0 |
0 |
T1 |
290250 |
1 |
0 |
0 |
T2 |
242550 |
0 |
0 |
0 |
T3 |
821113 |
1 |
0 |
0 |
T5 |
391739 |
1 |
0 |
0 |
T6 |
274388 |
0 |
0 |
0 |
T7 |
286194 |
0 |
0 |
0 |
T8 |
234106 |
3 |
0 |
0 |
T9 |
195539 |
1 |
0 |
0 |
T10 |
200268 |
1 |
0 |
0 |
T11 |
847845 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T8,T11,T12 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T8,T11,T12 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1925 |
0 |
0 |
T1 |
290250 |
1 |
0 |
0 |
T2 |
242550 |
0 |
0 |
0 |
T3 |
821113 |
1 |
0 |
0 |
T5 |
391739 |
1 |
0 |
0 |
T6 |
274388 |
0 |
0 |
0 |
T7 |
286194 |
0 |
0 |
0 |
T8 |
234106 |
3 |
0 |
0 |
T9 |
195539 |
1 |
0 |
0 |
T10 |
200268 |
1 |
0 |
0 |
T11 |
847845 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
1925 |
0 |
0 |
T1 |
34146 |
1 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
1 |
0 |
0 |
T5 |
41235 |
1 |
0 |
0 |
T6 |
24943 |
0 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
3 |
0 |
0 |
T9 |
41164 |
1 |
0 |
0 |
T10 |
40869 |
1 |
0 |
0 |
T11 |
67826 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T8,T11,T12 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T8,T11,T12 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
1792 |
0 |
0 |
T1 |
34146 |
1 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
1 |
0 |
0 |
T5 |
41235 |
1 |
0 |
0 |
T6 |
24943 |
0 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
3 |
0 |
0 |
T9 |
41164 |
1 |
0 |
0 |
T10 |
40869 |
1 |
0 |
0 |
T11 |
67826 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1893 |
0 |
0 |
T1 |
290250 |
1 |
0 |
0 |
T2 |
242550 |
0 |
0 |
0 |
T3 |
821113 |
1 |
0 |
0 |
T5 |
391739 |
1 |
0 |
0 |
T6 |
274388 |
0 |
0 |
0 |
T7 |
286194 |
0 |
0 |
0 |
T8 |
234106 |
3 |
0 |
0 |
T9 |
195539 |
1 |
0 |
0 |
T10 |
200268 |
1 |
0 |
0 |
T11 |
847845 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T8,T11,T12 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T8,T11,T12 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1876 |
0 |
0 |
T1 |
290250 |
1 |
0 |
0 |
T2 |
242550 |
0 |
0 |
0 |
T3 |
821113 |
1 |
0 |
0 |
T5 |
391739 |
1 |
0 |
0 |
T6 |
274388 |
0 |
0 |
0 |
T7 |
286194 |
0 |
0 |
0 |
T8 |
234106 |
3 |
0 |
0 |
T9 |
195539 |
1 |
0 |
0 |
T10 |
200268 |
1 |
0 |
0 |
T11 |
847845 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
1876 |
0 |
0 |
T1 |
34146 |
1 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
1 |
0 |
0 |
T5 |
41235 |
1 |
0 |
0 |
T6 |
24943 |
0 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
3 |
0 |
0 |
T9 |
41164 |
1 |
0 |
0 |
T10 |
40869 |
1 |
0 |
0 |
T11 |
67826 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T8,T11,T12 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T8,T11,T12 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
1784 |
0 |
0 |
T1 |
34146 |
1 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
1 |
0 |
0 |
T5 |
41235 |
1 |
0 |
0 |
T6 |
24943 |
0 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
3 |
0 |
0 |
T9 |
41164 |
1 |
0 |
0 |
T10 |
40869 |
1 |
0 |
0 |
T11 |
67826 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1889 |
0 |
0 |
T1 |
290250 |
1 |
0 |
0 |
T2 |
242550 |
0 |
0 |
0 |
T3 |
821113 |
1 |
0 |
0 |
T5 |
391739 |
1 |
0 |
0 |
T6 |
274388 |
0 |
0 |
0 |
T7 |
286194 |
0 |
0 |
0 |
T8 |
234106 |
3 |
0 |
0 |
T9 |
195539 |
1 |
0 |
0 |
T10 |
200268 |
1 |
0 |
0 |
T11 |
847845 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T8,T11,T12 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T8,T11,T12 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1871 |
0 |
0 |
T1 |
290250 |
1 |
0 |
0 |
T2 |
242550 |
0 |
0 |
0 |
T3 |
821113 |
1 |
0 |
0 |
T5 |
391739 |
1 |
0 |
0 |
T6 |
274388 |
0 |
0 |
0 |
T7 |
286194 |
0 |
0 |
0 |
T8 |
234106 |
3 |
0 |
0 |
T9 |
195539 |
1 |
0 |
0 |
T10 |
200268 |
1 |
0 |
0 |
T11 |
847845 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
1871 |
0 |
0 |
T1 |
34146 |
1 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
1 |
0 |
0 |
T5 |
41235 |
1 |
0 |
0 |
T6 |
24943 |
0 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
3 |
0 |
0 |
T9 |
41164 |
1 |
0 |
0 |
T10 |
40869 |
1 |
0 |
0 |
T11 |
67826 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T8,T11,T12 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T8,T11,T12 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
1813 |
0 |
0 |
T1 |
34146 |
1 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
1 |
0 |
0 |
T5 |
41235 |
1 |
0 |
0 |
T6 |
24943 |
0 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
3 |
0 |
0 |
T9 |
41164 |
1 |
0 |
0 |
T10 |
40869 |
1 |
0 |
0 |
T11 |
67826 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1916 |
0 |
0 |
T1 |
290250 |
1 |
0 |
0 |
T2 |
242550 |
0 |
0 |
0 |
T3 |
821113 |
1 |
0 |
0 |
T5 |
391739 |
1 |
0 |
0 |
T6 |
274388 |
0 |
0 |
0 |
T7 |
286194 |
0 |
0 |
0 |
T8 |
234106 |
3 |
0 |
0 |
T9 |
195539 |
1 |
0 |
0 |
T10 |
200268 |
1 |
0 |
0 |
T11 |
847845 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T8,T11,T12 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T8,T11,T12 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1898 |
0 |
0 |
T1 |
290250 |
1 |
0 |
0 |
T2 |
242550 |
0 |
0 |
0 |
T3 |
821113 |
1 |
0 |
0 |
T5 |
391739 |
1 |
0 |
0 |
T6 |
274388 |
0 |
0 |
0 |
T7 |
286194 |
0 |
0 |
0 |
T8 |
234106 |
3 |
0 |
0 |
T9 |
195539 |
1 |
0 |
0 |
T10 |
200268 |
1 |
0 |
0 |
T11 |
847845 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
1898 |
0 |
0 |
T1 |
34146 |
1 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
1 |
0 |
0 |
T5 |
41235 |
1 |
0 |
0 |
T6 |
24943 |
0 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
3 |
0 |
0 |
T9 |
41164 |
1 |
0 |
0 |
T10 |
40869 |
1 |
0 |
0 |
T11 |
67826 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T8,T11,T12 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T8,T11,T12 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
1785 |
0 |
0 |
T1 |
34146 |
1 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
1 |
0 |
0 |
T5 |
41235 |
1 |
0 |
0 |
T6 |
24943 |
0 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
3 |
0 |
0 |
T9 |
41164 |
1 |
0 |
0 |
T10 |
40869 |
1 |
0 |
0 |
T11 |
67826 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1891 |
0 |
0 |
T1 |
290250 |
1 |
0 |
0 |
T2 |
242550 |
0 |
0 |
0 |
T3 |
821113 |
1 |
0 |
0 |
T5 |
391739 |
1 |
0 |
0 |
T6 |
274388 |
0 |
0 |
0 |
T7 |
286194 |
0 |
0 |
0 |
T8 |
234106 |
3 |
0 |
0 |
T9 |
195539 |
1 |
0 |
0 |
T10 |
200268 |
1 |
0 |
0 |
T11 |
847845 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T8,T11,T12 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T8,T11,T12 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1877 |
0 |
0 |
T1 |
290250 |
1 |
0 |
0 |
T2 |
242550 |
0 |
0 |
0 |
T3 |
821113 |
1 |
0 |
0 |
T5 |
391739 |
1 |
0 |
0 |
T6 |
274388 |
0 |
0 |
0 |
T7 |
286194 |
0 |
0 |
0 |
T8 |
234106 |
3 |
0 |
0 |
T9 |
195539 |
1 |
0 |
0 |
T10 |
200268 |
1 |
0 |
0 |
T11 |
847845 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
1877 |
0 |
0 |
T1 |
34146 |
1 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
1 |
0 |
0 |
T5 |
41235 |
1 |
0 |
0 |
T6 |
24943 |
0 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
3 |
0 |
0 |
T9 |
41164 |
1 |
0 |
0 |
T10 |
40869 |
1 |
0 |
0 |
T11 |
67826 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T8,T11,T12 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T8,T11,T12 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
1822 |
0 |
0 |
T1 |
34146 |
1 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
1 |
0 |
0 |
T5 |
41235 |
1 |
0 |
0 |
T6 |
24943 |
0 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
3 |
0 |
0 |
T9 |
41164 |
1 |
0 |
0 |
T10 |
40869 |
1 |
0 |
0 |
T11 |
67826 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1926 |
0 |
0 |
T1 |
290250 |
1 |
0 |
0 |
T2 |
242550 |
0 |
0 |
0 |
T3 |
821113 |
1 |
0 |
0 |
T5 |
391739 |
1 |
0 |
0 |
T6 |
274388 |
0 |
0 |
0 |
T7 |
286194 |
0 |
0 |
0 |
T8 |
234106 |
3 |
0 |
0 |
T9 |
195539 |
1 |
0 |
0 |
T10 |
200268 |
1 |
0 |
0 |
T11 |
847845 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T8,T11,T12 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T8,T11,T12 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1908 |
0 |
0 |
T1 |
290250 |
1 |
0 |
0 |
T2 |
242550 |
0 |
0 |
0 |
T3 |
821113 |
1 |
0 |
0 |
T5 |
391739 |
1 |
0 |
0 |
T6 |
274388 |
0 |
0 |
0 |
T7 |
286194 |
0 |
0 |
0 |
T8 |
234106 |
3 |
0 |
0 |
T9 |
195539 |
1 |
0 |
0 |
T10 |
200268 |
1 |
0 |
0 |
T11 |
847845 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
1908 |
0 |
0 |
T1 |
34146 |
1 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
1 |
0 |
0 |
T5 |
41235 |
1 |
0 |
0 |
T6 |
24943 |
0 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
3 |
0 |
0 |
T9 |
41164 |
1 |
0 |
0 |
T10 |
40869 |
1 |
0 |
0 |
T11 |
67826 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T8,T11,T12 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T8,T11,T12 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
1785 |
0 |
0 |
T1 |
34146 |
1 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
1 |
0 |
0 |
T5 |
41235 |
1 |
0 |
0 |
T6 |
24943 |
0 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
3 |
0 |
0 |
T9 |
41164 |
1 |
0 |
0 |
T10 |
40869 |
1 |
0 |
0 |
T11 |
67826 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1894 |
0 |
0 |
T1 |
290250 |
1 |
0 |
0 |
T2 |
242550 |
0 |
0 |
0 |
T3 |
821113 |
1 |
0 |
0 |
T5 |
391739 |
1 |
0 |
0 |
T6 |
274388 |
0 |
0 |
0 |
T7 |
286194 |
0 |
0 |
0 |
T8 |
234106 |
3 |
0 |
0 |
T9 |
195539 |
1 |
0 |
0 |
T10 |
200268 |
1 |
0 |
0 |
T11 |
847845 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T8,T11,T12 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T8,T11,T12 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1875 |
0 |
0 |
T1 |
290250 |
1 |
0 |
0 |
T2 |
242550 |
0 |
0 |
0 |
T3 |
821113 |
1 |
0 |
0 |
T5 |
391739 |
1 |
0 |
0 |
T6 |
274388 |
0 |
0 |
0 |
T7 |
286194 |
0 |
0 |
0 |
T8 |
234106 |
3 |
0 |
0 |
T9 |
195539 |
1 |
0 |
0 |
T10 |
200268 |
1 |
0 |
0 |
T11 |
847845 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
1875 |
0 |
0 |
T1 |
34146 |
1 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
1 |
0 |
0 |
T5 |
41235 |
1 |
0 |
0 |
T6 |
24943 |
0 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
3 |
0 |
0 |
T9 |
41164 |
1 |
0 |
0 |
T10 |
40869 |
1 |
0 |
0 |
T11 |
67826 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T8,T11,T12 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T8,T11,T12 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
1940 |
0 |
0 |
T1 |
34146 |
1 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
1 |
0 |
0 |
T5 |
41235 |
1 |
0 |
0 |
T6 |
24943 |
1 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
3 |
0 |
0 |
T9 |
41164 |
1 |
0 |
0 |
T10 |
40869 |
1 |
0 |
0 |
T11 |
67826 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2046 |
0 |
0 |
T1 |
290250 |
1 |
0 |
0 |
T2 |
242550 |
0 |
0 |
0 |
T3 |
821113 |
1 |
0 |
0 |
T5 |
391739 |
1 |
0 |
0 |
T6 |
274388 |
1 |
0 |
0 |
T7 |
286194 |
0 |
0 |
0 |
T8 |
234106 |
3 |
0 |
0 |
T9 |
195539 |
1 |
0 |
0 |
T10 |
200268 |
1 |
0 |
0 |
T11 |
847845 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T8,T11,T12 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T8,T11,T12 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2028 |
0 |
0 |
T1 |
290250 |
1 |
0 |
0 |
T2 |
242550 |
0 |
0 |
0 |
T3 |
821113 |
1 |
0 |
0 |
T5 |
391739 |
1 |
0 |
0 |
T6 |
274388 |
1 |
0 |
0 |
T7 |
286194 |
0 |
0 |
0 |
T8 |
234106 |
3 |
0 |
0 |
T9 |
195539 |
1 |
0 |
0 |
T10 |
200268 |
1 |
0 |
0 |
T11 |
847845 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
2028 |
0 |
0 |
T1 |
34146 |
1 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
1 |
0 |
0 |
T5 |
41235 |
1 |
0 |
0 |
T6 |
24943 |
1 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
3 |
0 |
0 |
T9 |
41164 |
1 |
0 |
0 |
T10 |
40869 |
1 |
0 |
0 |
T11 |
67826 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T8,T11,T12 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T8,T11,T12 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
1830 |
0 |
0 |
T1 |
34146 |
1 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
1 |
0 |
0 |
T5 |
41235 |
1 |
0 |
0 |
T6 |
24943 |
0 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
3 |
0 |
0 |
T9 |
41164 |
1 |
0 |
0 |
T10 |
40869 |
1 |
0 |
0 |
T11 |
67826 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1940 |
0 |
0 |
T1 |
290250 |
1 |
0 |
0 |
T2 |
242550 |
0 |
0 |
0 |
T3 |
821113 |
1 |
0 |
0 |
T5 |
391739 |
1 |
0 |
0 |
T6 |
274388 |
0 |
0 |
0 |
T7 |
286194 |
0 |
0 |
0 |
T8 |
234106 |
3 |
0 |
0 |
T9 |
195539 |
1 |
0 |
0 |
T10 |
200268 |
1 |
0 |
0 |
T11 |
847845 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T8,T11,T12 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T8,T11,T12 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1924 |
0 |
0 |
T1 |
290250 |
1 |
0 |
0 |
T2 |
242550 |
0 |
0 |
0 |
T3 |
821113 |
1 |
0 |
0 |
T5 |
391739 |
1 |
0 |
0 |
T6 |
274388 |
0 |
0 |
0 |
T7 |
286194 |
0 |
0 |
0 |
T8 |
234106 |
3 |
0 |
0 |
T9 |
195539 |
1 |
0 |
0 |
T10 |
200268 |
1 |
0 |
0 |
T11 |
847845 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
1924 |
0 |
0 |
T1 |
34146 |
1 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
1 |
0 |
0 |
T5 |
41235 |
1 |
0 |
0 |
T6 |
24943 |
0 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
3 |
0 |
0 |
T9 |
41164 |
1 |
0 |
0 |
T10 |
40869 |
1 |
0 |
0 |
T11 |
67826 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T8,T11,T12 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T8,T11,T12 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
1845 |
0 |
0 |
T1 |
34146 |
1 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
1 |
0 |
0 |
T5 |
41235 |
1 |
0 |
0 |
T6 |
24943 |
0 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
3 |
0 |
0 |
T9 |
41164 |
1 |
0 |
0 |
T10 |
40869 |
1 |
0 |
0 |
T11 |
67826 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1954 |
0 |
0 |
T1 |
290250 |
1 |
0 |
0 |
T2 |
242550 |
0 |
0 |
0 |
T3 |
821113 |
1 |
0 |
0 |
T5 |
391739 |
1 |
0 |
0 |
T6 |
274388 |
0 |
0 |
0 |
T7 |
286194 |
0 |
0 |
0 |
T8 |
234106 |
3 |
0 |
0 |
T9 |
195539 |
1 |
0 |
0 |
T10 |
200268 |
1 |
0 |
0 |
T11 |
847845 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T8,T11,T12 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T8,T11,T12 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1936 |
0 |
0 |
T1 |
290250 |
1 |
0 |
0 |
T2 |
242550 |
0 |
0 |
0 |
T3 |
821113 |
1 |
0 |
0 |
T5 |
391739 |
1 |
0 |
0 |
T6 |
274388 |
0 |
0 |
0 |
T7 |
286194 |
0 |
0 |
0 |
T8 |
234106 |
3 |
0 |
0 |
T9 |
195539 |
1 |
0 |
0 |
T10 |
200268 |
1 |
0 |
0 |
T11 |
847845 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
1936 |
0 |
0 |
T1 |
34146 |
1 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
1 |
0 |
0 |
T5 |
41235 |
1 |
0 |
0 |
T6 |
24943 |
0 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
3 |
0 |
0 |
T9 |
41164 |
1 |
0 |
0 |
T10 |
40869 |
1 |
0 |
0 |
T11 |
67826 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T8,T11,T12 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T8,T11,T12 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
1813 |
0 |
0 |
T1 |
34146 |
1 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
1 |
0 |
0 |
T5 |
41235 |
1 |
0 |
0 |
T6 |
24943 |
0 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
3 |
0 |
0 |
T9 |
41164 |
1 |
0 |
0 |
T10 |
40869 |
1 |
0 |
0 |
T11 |
67826 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1914 |
0 |
0 |
T1 |
290250 |
1 |
0 |
0 |
T2 |
242550 |
0 |
0 |
0 |
T3 |
821113 |
1 |
0 |
0 |
T5 |
391739 |
1 |
0 |
0 |
T6 |
274388 |
0 |
0 |
0 |
T7 |
286194 |
0 |
0 |
0 |
T8 |
234106 |
3 |
0 |
0 |
T9 |
195539 |
1 |
0 |
0 |
T10 |
200268 |
1 |
0 |
0 |
T11 |
847845 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T8,T11,T12 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T8,T11,T12 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1898 |
0 |
0 |
T1 |
290250 |
1 |
0 |
0 |
T2 |
242550 |
0 |
0 |
0 |
T3 |
821113 |
1 |
0 |
0 |
T5 |
391739 |
1 |
0 |
0 |
T6 |
274388 |
0 |
0 |
0 |
T7 |
286194 |
0 |
0 |
0 |
T8 |
234106 |
3 |
0 |
0 |
T9 |
195539 |
1 |
0 |
0 |
T10 |
200268 |
1 |
0 |
0 |
T11 |
847845 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
1898 |
0 |
0 |
T1 |
34146 |
1 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
1 |
0 |
0 |
T5 |
41235 |
1 |
0 |
0 |
T6 |
24943 |
0 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
3 |
0 |
0 |
T9 |
41164 |
1 |
0 |
0 |
T10 |
40869 |
1 |
0 |
0 |
T11 |
67826 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T8,T11,T12 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T8,T11,T12 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
1815 |
0 |
0 |
T1 |
34146 |
1 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
1 |
0 |
0 |
T5 |
41235 |
1 |
0 |
0 |
T6 |
24943 |
0 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
3 |
0 |
0 |
T9 |
41164 |
1 |
0 |
0 |
T10 |
40869 |
1 |
0 |
0 |
T11 |
67826 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1921 |
0 |
0 |
T1 |
290250 |
1 |
0 |
0 |
T2 |
242550 |
0 |
0 |
0 |
T3 |
821113 |
1 |
0 |
0 |
T5 |
391739 |
1 |
0 |
0 |
T6 |
274388 |
0 |
0 |
0 |
T7 |
286194 |
0 |
0 |
0 |
T8 |
234106 |
3 |
0 |
0 |
T9 |
195539 |
1 |
0 |
0 |
T10 |
200268 |
1 |
0 |
0 |
T11 |
847845 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T8,T11,T12 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T8,T11,T12 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1902 |
0 |
0 |
T1 |
290250 |
1 |
0 |
0 |
T2 |
242550 |
0 |
0 |
0 |
T3 |
821113 |
1 |
0 |
0 |
T5 |
391739 |
1 |
0 |
0 |
T6 |
274388 |
0 |
0 |
0 |
T7 |
286194 |
0 |
0 |
0 |
T8 |
234106 |
3 |
0 |
0 |
T9 |
195539 |
1 |
0 |
0 |
T10 |
200268 |
1 |
0 |
0 |
T11 |
847845 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
1902 |
0 |
0 |
T1 |
34146 |
1 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
1 |
0 |
0 |
T5 |
41235 |
1 |
0 |
0 |
T6 |
24943 |
0 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
3 |
0 |
0 |
T9 |
41164 |
1 |
0 |
0 |
T10 |
40869 |
1 |
0 |
0 |
T11 |
67826 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T8,T11,T12 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T8,T11,T12 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
1823 |
0 |
0 |
T1 |
34146 |
1 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
1 |
0 |
0 |
T5 |
41235 |
1 |
0 |
0 |
T6 |
24943 |
0 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
3 |
0 |
0 |
T9 |
41164 |
1 |
0 |
0 |
T10 |
40869 |
1 |
0 |
0 |
T11 |
67826 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1924 |
0 |
0 |
T1 |
290250 |
1 |
0 |
0 |
T2 |
242550 |
0 |
0 |
0 |
T3 |
821113 |
1 |
0 |
0 |
T5 |
391739 |
1 |
0 |
0 |
T6 |
274388 |
0 |
0 |
0 |
T7 |
286194 |
0 |
0 |
0 |
T8 |
234106 |
3 |
0 |
0 |
T9 |
195539 |
1 |
0 |
0 |
T10 |
200268 |
1 |
0 |
0 |
T11 |
847845 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T8,T11,T12 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T8,T11,T12 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1908 |
0 |
0 |
T1 |
290250 |
1 |
0 |
0 |
T2 |
242550 |
0 |
0 |
0 |
T3 |
821113 |
1 |
0 |
0 |
T5 |
391739 |
1 |
0 |
0 |
T6 |
274388 |
0 |
0 |
0 |
T7 |
286194 |
0 |
0 |
0 |
T8 |
234106 |
3 |
0 |
0 |
T9 |
195539 |
1 |
0 |
0 |
T10 |
200268 |
1 |
0 |
0 |
T11 |
847845 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
1908 |
0 |
0 |
T1 |
34146 |
1 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
1 |
0 |
0 |
T5 |
41235 |
1 |
0 |
0 |
T6 |
24943 |
0 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
3 |
0 |
0 |
T9 |
41164 |
1 |
0 |
0 |
T10 |
40869 |
1 |
0 |
0 |
T11 |
67826 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T8,T11,T12 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T8,T11,T12 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
1800 |
0 |
0 |
T1 |
34146 |
1 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
1 |
0 |
0 |
T5 |
41235 |
1 |
0 |
0 |
T6 |
24943 |
0 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
3 |
0 |
0 |
T9 |
41164 |
1 |
0 |
0 |
T10 |
40869 |
1 |
0 |
0 |
T11 |
67826 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1898 |
0 |
0 |
T1 |
290250 |
1 |
0 |
0 |
T2 |
242550 |
0 |
0 |
0 |
T3 |
821113 |
1 |
0 |
0 |
T5 |
391739 |
1 |
0 |
0 |
T6 |
274388 |
0 |
0 |
0 |
T7 |
286194 |
0 |
0 |
0 |
T8 |
234106 |
3 |
0 |
0 |
T9 |
195539 |
1 |
0 |
0 |
T10 |
200268 |
1 |
0 |
0 |
T11 |
847845 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T8,T11,T12 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T8,T11,T12 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1881 |
0 |
0 |
T1 |
290250 |
1 |
0 |
0 |
T2 |
242550 |
0 |
0 |
0 |
T3 |
821113 |
1 |
0 |
0 |
T5 |
391739 |
1 |
0 |
0 |
T6 |
274388 |
0 |
0 |
0 |
T7 |
286194 |
0 |
0 |
0 |
T8 |
234106 |
3 |
0 |
0 |
T9 |
195539 |
1 |
0 |
0 |
T10 |
200268 |
1 |
0 |
0 |
T11 |
847845 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
1881 |
0 |
0 |
T1 |
34146 |
1 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
1 |
0 |
0 |
T5 |
41235 |
1 |
0 |
0 |
T6 |
24943 |
0 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
3 |
0 |
0 |
T9 |
41164 |
1 |
0 |
0 |
T10 |
40869 |
1 |
0 |
0 |
T11 |
67826 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T8,T11,T12 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T8,T11,T12 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
1804 |
0 |
0 |
T1 |
34146 |
1 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
1 |
0 |
0 |
T5 |
41235 |
1 |
0 |
0 |
T6 |
24943 |
0 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
3 |
0 |
0 |
T9 |
41164 |
1 |
0 |
0 |
T10 |
40869 |
1 |
0 |
0 |
T11 |
67826 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1906 |
0 |
0 |
T1 |
290250 |
1 |
0 |
0 |
T2 |
242550 |
0 |
0 |
0 |
T3 |
821113 |
1 |
0 |
0 |
T5 |
391739 |
1 |
0 |
0 |
T6 |
274388 |
0 |
0 |
0 |
T7 |
286194 |
0 |
0 |
0 |
T8 |
234106 |
3 |
0 |
0 |
T9 |
195539 |
1 |
0 |
0 |
T10 |
200268 |
1 |
0 |
0 |
T11 |
847845 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T8,T11,T12 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T8,T11,T12 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1891 |
0 |
0 |
T1 |
290250 |
1 |
0 |
0 |
T2 |
242550 |
0 |
0 |
0 |
T3 |
821113 |
1 |
0 |
0 |
T5 |
391739 |
1 |
0 |
0 |
T6 |
274388 |
0 |
0 |
0 |
T7 |
286194 |
0 |
0 |
0 |
T8 |
234106 |
3 |
0 |
0 |
T9 |
195539 |
1 |
0 |
0 |
T10 |
200268 |
1 |
0 |
0 |
T11 |
847845 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
1891 |
0 |
0 |
T1 |
34146 |
1 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
1 |
0 |
0 |
T5 |
41235 |
1 |
0 |
0 |
T6 |
24943 |
0 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
3 |
0 |
0 |
T9 |
41164 |
1 |
0 |
0 |
T10 |
40869 |
1 |
0 |
0 |
T11 |
67826 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T5,T9 |
1 | 0 | Covered | T1,T5,T9 |
1 | 1 | Covered | T11,T12,T13 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T5,T9 |
1 | 0 | Covered | T11,T12,T13 |
1 | 1 | Covered | T1,T5,T9 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
1270 |
0 |
0 |
T1 |
34146 |
1 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
0 |
0 |
0 |
T5 |
41235 |
1 |
0 |
0 |
T6 |
24943 |
0 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
0 |
0 |
0 |
T9 |
41164 |
1 |
0 |
0 |
T10 |
40869 |
1 |
0 |
0 |
T11 |
67826 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T34 |
0 |
1 |
0 |
0 |
T39 |
0 |
2 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1370 |
0 |
0 |
T1 |
290250 |
1 |
0 |
0 |
T2 |
242550 |
0 |
0 |
0 |
T3 |
821113 |
0 |
0 |
0 |
T5 |
391739 |
1 |
0 |
0 |
T6 |
274388 |
0 |
0 |
0 |
T7 |
286194 |
0 |
0 |
0 |
T8 |
234106 |
0 |
0 |
0 |
T9 |
195539 |
1 |
0 |
0 |
T10 |
200268 |
1 |
0 |
0 |
T11 |
847845 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T34 |
0 |
1 |
0 |
0 |
T39 |
0 |
2 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T5,T9 |
1 | 0 | Covered | T1,T5,T9 |
1 | 1 | Covered | T11,T12,T13 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T5,T9 |
1 | 0 | Covered | T11,T12,T13 |
1 | 1 | Covered | T1,T5,T9 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1350 |
0 |
0 |
T1 |
290250 |
1 |
0 |
0 |
T2 |
242550 |
0 |
0 |
0 |
T3 |
821113 |
0 |
0 |
0 |
T5 |
391739 |
1 |
0 |
0 |
T6 |
274388 |
0 |
0 |
0 |
T7 |
286194 |
0 |
0 |
0 |
T8 |
234106 |
0 |
0 |
0 |
T9 |
195539 |
1 |
0 |
0 |
T10 |
200268 |
1 |
0 |
0 |
T11 |
847845 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T34 |
0 |
1 |
0 |
0 |
T39 |
0 |
2 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
1350 |
0 |
0 |
T1 |
34146 |
1 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
0 |
0 |
0 |
T5 |
41235 |
1 |
0 |
0 |
T6 |
24943 |
0 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
0 |
0 |
0 |
T9 |
41164 |
1 |
0 |
0 |
T10 |
40869 |
1 |
0 |
0 |
T11 |
67826 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T34 |
0 |
1 |
0 |
0 |
T39 |
0 |
2 |
0 |
0 |
T48 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T1,T3,T5 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34737939 |
67529 |
0 |
0 |
T1 |
34146 |
71 |
0 |
0 |
T2 |
1053 |
0 |
0 |
0 |
T3 |
32843 |
76 |
0 |
0 |
T5 |
41235 |
74 |
0 |
0 |
T6 |
24943 |
0 |
0 |
0 |
T7 |
1143 |
0 |
0 |
0 |
T8 |
97541 |
228 |
0 |
0 |
T9 |
41164 |
68 |
0 |
0 |
T10 |
40869 |
62 |
0 |
0 |
T11 |
67826 |
166 |
0 |
0 |
T12 |
0 |
231 |
0 |
0 |
T13 |
0 |
210 |
0 |
0 |
T48 |
0 |
156 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
67639 |
0 |
0 |
T1 |
290250 |
71 |
0 |
0 |
T2 |
242550 |
0 |
0 |
0 |
T3 |
821113 |
76 |
0 |
0 |
T5 |
391739 |
74 |
0 |
0 |
T6 |
274388 |
0 |
0 |
0 |
T7 |
286194 |
0 |
0 |
0 |
T8 |
234106 |
228 |
0 |
0 |
T9 |
195539 |
68 |
0 |
0 |
T10 |
200268 |
62 |
0 |
0 |
T11 |
847845 |
166 |
0 |
0 |
T12 |
0 |
231 |
0 |
0 |
T13 |
0 |
210 |
0 |
0 |
T48 |
0 |
156 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_adc_ctrl_core.u_oneshot_done_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_adc_ctrl_core.u_oneshot_done_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T2,T6,T7 |
1 | 0 | Covered | T2,T6,T7 |
1 | 1 | Covered | T2,T6,T7 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T2,T6,T7 |
1 | 0 | Covered | T2,T6,T7 |
1 | 1 | Covered | T2,T6,T7 |
Branch Coverage for Instance : tb.dut.u_adc_ctrl_core.u_oneshot_done_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_adc_ctrl_core.u_oneshot_done_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
6578 |
0 |
0 |
T2 |
242550 |
11 |
0 |
0 |
T3 |
821113 |
0 |
0 |
0 |
T5 |
391739 |
0 |
0 |
0 |
T6 |
274388 |
58 |
0 |
0 |
T7 |
286194 |
20 |
0 |
0 |
T8 |
234106 |
0 |
0 |
0 |
T9 |
195539 |
0 |
0 |
0 |
T10 |
200268 |
27 |
0 |
0 |
T11 |
847845 |
0 |
0 |
0 |
T12 |
445580 |
0 |
0 |
0 |
T37 |
0 |
20 |
0 |
0 |
T38 |
0 |
20 |
0 |
0 |
T40 |
0 |
56 |
0 |
0 |
T42 |
0 |
101 |
0 |
0 |
T45 |
0 |
5 |
0 |
0 |
T54 |
0 |
6 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34659749 |
6581 |
0 |
0 |
T2 |
1053 |
11 |
0 |
0 |
T3 |
32843 |
0 |
0 |
0 |
T5 |
41235 |
0 |
0 |
0 |
T6 |
24943 |
58 |
0 |
0 |
T7 |
1143 |
20 |
0 |
0 |
T8 |
97541 |
0 |
0 |
0 |
T9 |
41164 |
0 |
0 |
0 |
T10 |
40869 |
27 |
0 |
0 |
T11 |
67826 |
0 |
0 |
0 |
T12 |
102428 |
0 |
0 |
0 |
T37 |
0 |
20 |
0 |
0 |
T38 |
0 |
20 |
0 |
0 |
T40 |
0 |
56 |
0 |
0 |
T42 |
0 |
101 |
0 |
0 |
T45 |
0 |
5 |
0 |
0 |
T54 |
0 |
6 |
0 |
0 |