Unified Coverage Report :: Module :: adc_ctrl_core

Module : adc_ctrl_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_adc_ctrl_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.83	100.00	99.76		100.00	99.37	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_ctrl_fsm	99.75	100.00	100.00		100.00	98.73	100.00
u_adc_ctrl_intr	99.00	100.00	96.00			100.00	100.00
u_oneshot_done_sync	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
TOTAL		63	63	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	73	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	213	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	8	8
63	8	8
72	1	1
73	1	1
74	1	1
75	1	1
83	1	1
86	1	1
87	1	1
88	1	1
89	1	1
104	8	8
107	8	8
117	8	8
121	8	8
137	1	1
138	1	1
140	1	1
141	1	1
145	1	1
213	1	1

---

Cond Coverage for Module : adc_ctrl_core

	Total	Covered	Percent
Conditions	293	293	100.00
Logical	293	293	100.00
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION (reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done : (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0))
             -----------------1----------------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T6,T7

 LINE       83
 SUB-EXPRESSION (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0)
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][0].cond)) ? ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v)) : ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v)))

-1-	Status	Tests
0	Covered	T8,T10,T11
1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T11
0	1	Covered	T8,T10,T11
1	0	Covered	T8,T10,T11

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][1].cond)) ? ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v)) : ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v)))

-1-	Status	Tests
0	Covered	T1,T3,T8
1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T9,T10
1	0	Covered	T2,T5,T6
1	1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T8

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][2].cond)) ? ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v)) : ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v)))

-1-	Status	Tests
0	Covered	T12,T13,T48
1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T48
0	1	Covered	T12,T13,T48
1	0	Covered	T12,T13,T48

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][3].cond)) ? ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v)) : ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v)))

-1-	Status	Tests
0	Covered	T1,T3,T8
1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T9,T11
1	0	Covered	T2,T5,T6
1	1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T8

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][4].cond)) ? ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v)) : ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v)))

-1-	Status	Tests
0	Covered	T8,T10,T12
1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T12
0	1	Covered	T8,T10,T12
1	0	Covered	T8,T10,T12

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][5].cond)) ? ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v)) : ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v)))

-1-	Status	Tests
0	Covered	T3,T8,T11
1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T9
1	0	Covered	T1,T2,T5
1	1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T11
0	1	Covered	T3,T8,T11
1	0	Covered	T3,T8,T11

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][6].cond)) ? ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v)) : ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v)))

-1-	Status	Tests
0	Covered	T8,T10,T12
1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T12
0	1	Covered	T8,T10,T12
1	0	Covered	T8,T10,T12

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][7].cond)) ? ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v)) : ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v)))

-1-	Status	Tests
0	Covered	T1,T5,T8
1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T11
1	0	Covered	T2,T3,T6
1	1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T8
0	1	Covered	T1,T5,T8
1	0	Covered	T1,T5,T8

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][0].cond)) ? ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v)) : ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v)))

-1-	Status	Tests
0	Covered	T3,T8,T10
1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T8
1	0	Covered	T1,T2,T5
1	1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T10
0	1	Covered	T3,T8,T10
1	0	Covered	T3,T8,T10

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][1].cond)) ? ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v)) : ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v)))

-1-	Status	Tests
0	Covered	T1,T3,T8
1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Covered	T2,T5,T6
1	1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T8

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][2].cond)) ? ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v)) : ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v)))

-1-	Status	Tests
0	Covered	T12,T13,T48
1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T48
0	1	Covered	T12,T13,T48
1	0	Covered	T12,T13,T48

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][3].cond)) ? ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v)) : ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v)))

-1-	Status	Tests
0	Covered	T1,T3,T8
1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Covered	T2,T5,T6
1	1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T8

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][4].cond)) ? ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v)) : ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v)))

-1-	Status	Tests
0	Covered	T8,T10,T12
1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T12
0	1	Covered	T8,T10,T12
1	0	Covered	T8,T10,T12

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][5].cond)) ? ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v)) : ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v)))

-1-	Status	Tests
0	Covered	T3,T8,T11
1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T8
1	0	Covered	T1,T2,T5
1	1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T11
0	1	Covered	T3,T8,T11
1	0	Covered	T3,T8,T11

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][6].cond)) ? ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v)) : ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v)))

-1-	Status	Tests
0	Covered	T8,T10,T12
1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T12
0	1	Covered	T8,T10,T12
1	0	Covered	T8,T10,T12

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][7].cond)) ? ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v)) : ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v)))

-1-	Status	Tests
0	Covered	T1,T5,T8
1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T11
1	0	Covered	T2,T3,T6
1	1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T8
0	1	Covered	T1,T5,T8
1	0	Covered	T1,T5,T8

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][0].en, aon_filter_ctl[1][0].en})) & 
      2  (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en)) & 
      3  (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T2
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T1,T5,T8
1	1	1	Covered	T1,T3,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T5
0	1	Covered	T1,T3,T5
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[0] & aon_filter_ctl[0][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T3,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T8
0	1	Covered	T1,T5,T6
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[0] & aon_filter_ctl[1][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T8
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T5,T6

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][1].en, aon_filter_ctl[1][1].en})) & 
      2  (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en)) & 
      3  (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T2
1	0	1	Covered	T5,T8,T9
1	1	0	Covered	T5,T8,T9
1	1	1	Covered	T5,T8,T9

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T8,T9
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[1] & aon_filter_ctl[0][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Covered	T4,T1,T2
1	1	Covered	T5,T8,T9

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T8,T9
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[1] & aon_filter_ctl[1][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Covered	T4,T1,T2
1	1	Covered	T5,T8,T9

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][2].en, aon_filter_ctl[1][2].en})) & 
      2  (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en)) & 
      3  (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T2
1	0	1	Covered	T5,T8,T9
1	1	0	Covered	T5,T8,T9
1	1	1	Covered	T5,T8,T9

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T8,T9
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[2] & aon_filter_ctl[0][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Covered	T4,T1,T2
1	1	Covered	T5,T8,T9

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T8,T9
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[2] & aon_filter_ctl[1][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Covered	T4,T1,T2
1	1	Covered	T5,T8,T9

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][3].en, aon_filter_ctl[1][3].en})) & 
      2  (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en)) & 
      3  (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T2
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T1,T3,T5
1	1	1	Covered	T1,T3,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T5
0	1	Covered	T1,T3,T5
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[3] & aon_filter_ctl[0][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T3,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T5
0	1	Covered	T1,T3,T5
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[3] & aon_filter_ctl[1][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T3,T5

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][4].en, aon_filter_ctl[1][4].en})) & 
      2  (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en)) & 
      3  (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T2
1	0	1	Covered	T5,T8,T9
1	1	0	Covered	T5,T8,T9
1	1	1	Covered	T5,T8,T9

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T8,T9
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[4] & aon_filter_ctl[0][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Covered	T4,T1,T2
1	1	Covered	T5,T8,T9

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T8,T9
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[4] & aon_filter_ctl[1][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Covered	T4,T1,T2
1	1	Covered	T5,T8,T9

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][5].en, aon_filter_ctl[1][5].en})) & 
      2  (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en)) & 
      3  (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T2
1	0	1	Covered	T5,T9,T11
1	1	0	Covered	T5,T8,T9
1	1	1	Covered	T5,T8,T9

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T8,T9
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[5] & aon_filter_ctl[0][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Covered	T4,T1,T2
1	1	Covered	T5,T8,T9

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T8,T9
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[5] & aon_filter_ctl[1][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Covered	T4,T1,T2
1	1	Covered	T5,T8,T9

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][6].en, aon_filter_ctl[1][6].en})) & 
      2  (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en)) & 
      3  (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T2
1	0	1	Covered	T3,T5,T9
1	1	0	Covered	T3,T5,T8
1	1	1	Covered	T3,T5,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T8
0	1	Covered	T3,T5,T8
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[6] & aon_filter_ctl[0][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T8
1	0	Covered	T4,T1,T2
1	1	Covered	T3,T5,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T8
0	1	Covered	T3,T5,T8
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[6] & aon_filter_ctl[1][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T8
1	0	Covered	T4,T1,T2
1	1	Covered	T3,T5,T8

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][7].en, aon_filter_ctl[1][7].en})) & 
      2  (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en)) & 
      3  (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T2
1	0	1	Covered	T1,T5,T8
1	1	0	Covered	T1,T5,T8
1	1	1	Covered	T1,T5,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T8
0	1	Covered	T1,T5,T8
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[7] & aon_filter_ctl[0][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T8
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T5,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T8
0	1	Covered	T1,T5,T8
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[7] & aon_filter_ctl[1][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T8
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T5,T8

 LINE       121
 EXPRESSION (adc_ctrl_done && match[0])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

 LINE       121
 EXPRESSION (adc_ctrl_done && match[1])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Covered	T1,T3,T5
1	1	Covered	T5,T8,T9

 LINE       121
 EXPRESSION (adc_ctrl_done && match[2])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Covered	T1,T3,T5
1	1	Covered	T5,T8,T9

 LINE       121
 EXPRESSION (adc_ctrl_done && match[3])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T3,T5

 LINE       121
 EXPRESSION (adc_ctrl_done && match[4])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Covered	T1,T3,T5
1	1	Covered	T5,T8,T9

 LINE       121
 EXPRESSION (adc_ctrl_done && match[5])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Covered	T1,T3,T5
1	1	Covered	T5,T8,T9

 LINE       121
 EXPRESSION (adc_ctrl_done && match[6])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T8
1	0	Covered	T1,T3,T5
1	1	Covered	T3,T5,T8

 LINE       121
 EXPRESSION (adc_ctrl_done && match[7])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T8
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T5,T8

 LINE       140
 EXPRESSION (aon_fsm_trans | reg2hw_i.filter_status.trans.q)
             ------1------   ---------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Covered	T1,T5,T9
1	0	Covered	T1,T5,T9

 LINE       145
 EXPRESSION (((|(reg2hw_i.filter_status.match.q & reg2hw_i.adc_wakeup_ctl.match_en.q))) || (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q))
             -------------------------------------1------------------------------------    ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Covered	T11,T13,T34
1	0	Covered	T1,T5,T9

 LINE       145
 SUB-EXPRESSION (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q)
                 ---------------1--------------   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T48
1	0	Covered	T1,T5,T9
1	1	Covered	T11,T13,T34

---

Branch Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	83	3	3	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	83	(reg2hw_i.adc_en_ctl.oneshot_mode.q) ? 
-2-:	83	(reg2hw_i.adc_en_ctl.adc_enable.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T6,T7
0	1	Covered	T1,T2,T3
0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T8,T10,T11

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T3,T8,T10

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T1,T3,T8

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T1,T3,T8

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T12,T13,T48

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T12,T13,T48

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T1,T3,T8

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T1,T3,T8

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T8,T10,T12

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T8,T10,T12

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T3,T8,T11

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T3,T8,T11

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T8,T10,T12

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T8,T10,T12

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T1,T5,T8

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T1,T5,T8

---

Assert Coverage for Module : adc_ctrl_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	33	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	33	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxFilters_A	34659749	34340800	0	0
gen_filter_match[0].MatchCheck00_A	34659749	9886790	0	0
gen_filter_match[0].MatchCheck01_A	34659749	2677235	0	0
gen_filter_match[0].MatchCheck10_A	34659749	2627525	0	0
gen_filter_match[0].MatchCheck11_A	34659749	19149250	0	0
gen_filter_match[1].MatchCheck00_A	34659749	11880850	0	0
gen_filter_match[1].MatchCheck01_A	34659749	1439493	0	0
gen_filter_match[1].MatchCheck10_A	34659749	1323248	0	0
gen_filter_match[1].MatchCheck11_A	34659749	19697209	0	0
gen_filter_match[2].MatchCheck00_A	34659749	12341762	0	0
gen_filter_match[2].MatchCheck01_A	34659749	441264	0	0
gen_filter_match[2].MatchCheck10_A	34659749	785405	0	0
gen_filter_match[2].MatchCheck11_A	34659749	20772369	0	0
gen_filter_match[3].MatchCheck00_A	34659749	12310338	0	0
gen_filter_match[3].MatchCheck01_A	34659749	235406	0	0
gen_filter_match[3].MatchCheck10_A	34659749	391162	0	0
gen_filter_match[3].MatchCheck11_A	34659749	21403894	0	0
gen_filter_match[4].MatchCheck00_A	34659749	13983352	0	0
gen_filter_match[4].MatchCheck01_A	34659749	34371	0	0
gen_filter_match[4].MatchCheck10_A	34659749	33380	0	0
gen_filter_match[4].MatchCheck11_A	34659749	20289697	0	0
gen_filter_match[5].MatchCheck00_A	34659749	11915149	0	0
gen_filter_match[5].MatchCheck01_A	34659749	36080	0	0
gen_filter_match[5].MatchCheck10_A	34659749	101966	0	0
gen_filter_match[5].MatchCheck11_A	34659749	22287605	0	0
gen_filter_match[6].MatchCheck00_A	34659749	13188083	0	0
gen_filter_match[6].MatchCheck01_A	34659749	66076	0	0
gen_filter_match[6].MatchCheck10_A	34659749	32680	0	0
gen_filter_match[6].MatchCheck11_A	34659749	21053961	0	0
gen_filter_match[7].MatchCheck00_A	34659749	13240668	0	0
gen_filter_match[7].MatchCheck01_A	34659749	139855	0	0
gen_filter_match[7].MatchCheck10_A	34659749	73368	0	0
gen_filter_match[7].MatchCheck11_A	34659749	20886909	0	0

MaxFilters_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34659749	34340800	0	0
T1	34146	34076	0	0
T2	1053	1003	0	0
T3	32843	32771	0	0
T4	86	10	0	0
T5	41235	41157	0	0
T6	24943	21843	0	0
T7	1143	1088	0	0
T8	97541	97491	0	0
T9	41164	41071	0	0
T10	40869	40561	0	0

gen_filter_match[0].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34659749	9886790	0	0
T1	34146	4	0	0
T2	1053	1003	0	0
T3	32843	3	0	0
T4	86	10	0	0
T5	41235	4	0	0
T6	24943	20857	0	0
T7	1143	1088	0	0
T8	97541	65330	0	0
T9	41164	3	0	0
T10	40869	40561	0	0

gen_filter_match[0].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34659749	2677235	0	0
T34	32848	0	0	0
T37	1181	0	0	0
T38	1212	0	0	0
T39	2588	0	0	0
T40	25068	0	0	0
T41	90	0	0	0
T42	63635	0	0	0
T43	32933	0	0	0
T44	32914	0	0	0
T48	65577	32569	0	0
T65	0	66034	0	0
T131	0	40170	0	0
T132	0	31947	0	0
T133	0	32251	0	0
T134	0	39368	0	0
T135	0	36121	0	0
T136	0	32935	0	0
T137	0	38537	0	0
T138	0	32019	0	0

gen_filter_match[0].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34659749	2627525	0	0
T3	32843	32768	0	0
T5	41235	0	0	0
T6	24943	0	0	0
T7	1143	0	0	0
T8	97541	0	0	0
T9	41164	0	0	0
T10	40869	0	0	0
T11	67826	0	0	0
T12	102428	0	0	0
T13	101384	0	0	0
T34	0	32600	0	0
T42	0	33636	0	0
T132	0	33294	0	0
T137	0	35888	0	0
T139	0	32894	0	0
T140	0	34462	0	0
T141	0	32013	0	0
T142	0	32887	0	0
T143	0	32999	0	0

gen_filter_match[0].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34659749	19149250	0	0
T1	34146	34072	0	0
T2	1053	0	0	0
T3	32843	0	0	0
T5	41235	41153	0	0
T6	24943	986	0	0
T7	1143	0	0	0
T8	97541	32161	0	0
T9	41164	41068	0	0
T10	40869	0	0	0
T11	67826	36502	0	0
T12	0	102354	0	0
T40	0	463	0	0
T42	0	844	0	0
T48	0	32926	0	0

gen_filter_match[1].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34659749	11880850	0	0
T1	34146	34076	0	0
T2	1053	1003	0	0
T3	32843	32771	0	0
T4	86	10	0	0
T5	41235	4	0	0
T6	24943	21843	0	0
T7	1143	1088	0	0
T8	97541	4	0	0
T9	41164	3	0	0
T10	40869	40561	0	0

gen_filter_match[1].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34659749	1439493	0	0
T8	97541	64865	0	0
T9	41164	0	0	0
T10	40869	0	0	0
T11	67826	0	0	0
T12	102428	0	0	0
T13	101384	0	0	0
T34	32848	0	0	0
T37	1181	0	0	0
T38	1212	0	0	0
T48	65577	0	0	0
T56	0	7603	0	0
T89	0	35045	0	0
T140	0	32530	0	0
T144	0	32067	0	0
T145	0	40991	0	0
T146	0	34116	0	0
T147	0	54927	0	0
T148	0	36235	0	0
T149	0	2	0	0

gen_filter_match[1].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34659749	1323248	0	0
T11	67826	36502	0	0
T12	102428	67784	0	0
T13	101384	0	0	0
T34	32848	0	0	0
T35	0	33763	0	0
T37	1181	0	0	0
T38	1212	0	0	0
T39	2588	0	0	0
T40	25068	0	0	0
T41	90	0	0	0
T48	65577	0	0	0
T55	0	33389	0	0
T133	0	32900	0	0
T138	0	33515	0	0
T150	0	33250	0	0
T151	0	32137	0	0
T152	0	1	0	0
T153	0	34143	0	0

gen_filter_match[1].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34659749	19697209	0	0
T5	41235	41153	0	0
T6	24943	0	0	0
T7	1143	0	0	0
T8	97541	32622	0	0
T9	41164	41068	0	0
T10	40869	0	0	0
T11	67826	31261	0	0
T12	102428	34570	0	0
T13	101384	35409	0	0
T34	0	32600	0	0
T42	0	33637	0	0
T43	0	32854	0	0
T44	0	32814	0	0
T48	65577	0	0	0

gen_filter_match[2].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34659749	12341762	0	0
T1	34146	34076	0	0
T2	1053	1003	0	0
T3	32843	32771	0	0
T4	86	10	0	0
T5	41235	4	0	0
T6	24943	21843	0	0
T7	1143	1088	0	0
T8	97541	32165	0	0
T9	41164	3	0	0
T10	40869	8565	0	0

gen_filter_match[2].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34659749	441264	0	0
T49	8755	2984	0	0
T90	0	33208	0	0
T144	0	1	0	0
T149	0	31840	0	0
T151	32227	0	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	0	33713	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	35348	0	0
T160	65214	0	0	0
T161	33147	0	0	0
T162	668	0	0	0
T163	98785	0	0	0
T164	39651	0	0	0
T165	37975	0	0	0
T166	5955	0	0	0
T167	66931	0	0	0

gen_filter_match[2].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34659749	785405	0	0
T35	67300	0	0	0
T46	6470	4831	0	0
T47	8475	0	0	0
T66	0	32230	0	0
T131	40233	0	0	0
T136	0	32658	0	0
T139	97348	32030	0	0
T144	0	1	0	0
T152	0	1	0	0
T154	0	1	0	0
T163	0	1	0	0
T167	0	32511	0	0
T168	0	34478	0	0
T169	1113	0	0	0
T170	78793	0	0	0
T171	969	0	0	0
T172	864	0	0	0
T173	32883	0	0	0

gen_filter_match[2].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34659749	20772369	0	0
T5	41235	41153	0	0
T6	24943	0	0	0
T7	1143	0	0	0
T8	97541	65326	0	0
T9	41164	41068	0	0
T10	40869	31996	0	0
T11	67826	31261	0	0
T12	102428	68873	0	0
T13	101384	69359	0	0
T42	0	33637	0	0
T48	65577	65495	0	0
T53	0	31336	0	0

gen_filter_match[3].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34659749	12310338	0	0
T1	34146	4	0	0
T2	1053	1003	0	0
T3	32843	3	0	0
T4	86	10	0	0
T5	41235	4	0	0
T6	24943	21843	0	0
T7	1143	1088	0	0
T8	97541	4	0	0
T9	41164	3	0	0
T10	40869	8565	0	0

gen_filter_match[3].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34659749	235406	0	0
T50	27787	0	0	0
T144	0	31693	0	0
T149	0	3	0	0
T151	32227	0	0	0
T154	0	1	0	0
T155	0	2	0	0
T157	0	1	0	0
T163	98785	1	0	0
T164	39651	0	0	0
T165	37975	0	0	0
T166	5955	0	0	0
T167	66931	0	0	0
T174	0	32954	0	0
T175	0	962	0	0
T176	0	32484	0	0
T177	0	32051	0	0
T178	33143	0	0	0
T179	619	0	0	0
T180	32694	0	0	0

gen_filter_match[3].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34659749	391162	0	0
T11	67826	1	0	0
T12	102428	0	0	0
T13	101384	0	0	0
T34	32848	0	0	0
T37	1181	0	0	0
T38	1212	0	0	0
T39	2588	0	0	0
T40	25068	0	0	0
T41	90	0	0	0
T47	0	6902	0	0
T48	65577	0	0	0
T55	0	1	0	0
T140	0	1	0	0
T152	0	1	0	0
T154	0	1	0	0
T163	0	1	0	0
T164	0	1	0	0
T168	0	1	0	0
T180	0	1	0	0

gen_filter_match[3].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34659749	21403894	0	0
T1	34146	34072	0	0
T2	1053	0	0	0
T3	32843	32768	0	0
T5	41235	41153	0	0
T6	24943	0	0	0
T7	1143	0	0	0
T8	97541	97487	0	0
T9	41164	41068	0	0
T10	40869	31996	0	0
T11	67826	31260	0	0
T12	0	68051	0	0
T13	0	101297	0	0
T48	0	32569	0	0

gen_filter_match[4].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34659749	13983352	0	0
T1	34146	34076	0	0
T2	1053	1003	0	0
T3	32843	32771	0	0
T4	86	10	0	0
T5	41235	4	0	0
T6	24943	21843	0	0
T7	1143	1088	0	0
T8	97541	4	0	0
T9	41164	3	0	0
T10	40869	8565	0	0

gen_filter_match[4].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34659749	34371	0	0
T135	111173	0	0	0
T136	65649	0	0	0
T137	74484	0	0	0
T138	65612	0	0	0
T140	100512	1	0	0
T141	64804	0	0	0
T142	32960	0	0	0
T167	0	34360	0	0
T181	0	2	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	1	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0
T189	913	0	0	0
T190	1223	0	0	0
T191	898	0	0	0

gen_filter_match[4].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34659749	33380	0	0
T46	6470	0	0	0
T47	8475	0	0	0
T55	99315	1	0	0
T65	66108	0	0	0
T131	40233	0	0	0
T139	97348	0	0	0
T140	0	1	0	0
T145	0	1	0	0
T150	98555	0	0	0
T152	0	1	0	0
T163	0	1	0	0
T164	0	1	0	0
T168	0	1	0	0
T169	1113	0	0	0
T170	78793	0	0	0
T171	969	0	0	0
T180	0	1	0	0
T192	0	1	0	0
T193	0	1	0	0

gen_filter_match[4].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34659749	20289697	0	0
T5	41235	41153	0	0
T6	24943	0	0	0
T7	1143	0	0	0
T8	97541	97487	0	0
T9	41164	41068	0	0
T10	40869	31996	0	0
T11	67826	0	0	0
T12	102428	34303	0	0
T13	101384	65888	0	0
T43	0	32854	0	0
T48	65577	32926	0	0
T53	0	31336	0	0
T55	0	32704	0	0

gen_filter_match[5].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34659749	11915149	0	0
T1	34146	34076	0	0
T2	1053	1003	0	0
T3	32843	32771	0	0
T4	86	10	0	0
T5	41235	4	0	0
T6	24943	21843	0	0
T7	1143	1088	0	0
T8	97541	64787	0	0
T9	41164	3	0	0
T10	40869	40561	0	0

gen_filter_match[5].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34659749	36080	0	0
T50	27787	0	0	0
T90	0	1	0	0
T149	0	2	0	0
T151	32227	0	0	0
T157	0	1	0	0
T158	0	1	0	0
T163	98785	1	0	0
T164	39651	0	0	0
T165	37975	0	0	0
T166	5955	0	0	0
T167	66931	0	0	0
T178	33143	0	0	0
T179	619	0	0	0
T180	32694	0	0	0
T182	0	3	0	0
T183	0	1	0	0
T185	0	1	0	0
T186	0	2	0	0
T194	0	36064	0	0

gen_filter_match[5].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34659749	101966	0	0
T11	67826	1	0	0
T12	102428	0	0	0
T13	101384	0	0	0
T34	32848	1	0	0
T37	1181	0	0	0
T38	1212	0	0	0
T39	2588	0	0	0
T40	25068	0	0	0
T41	90	0	0	0
T48	65577	32926	0	0
T65	0	1	0	0
T152	0	1	0	0
T154	0	1	0	0
T164	0	1	0	0
T168	0	1	0	0
T180	0	1	0	0
T192	0	1	0	0

gen_filter_match[5].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34659749	22287605	0	0
T5	41235	41153	0	0
T6	24943	0	0	0
T7	1143	0	0	0
T8	97541	32704	0	0
T9	41164	41068	0	0
T10	40869	0	0	0
T11	67826	67762	0	0
T12	102428	67784	0	0
T13	101384	31938	0	0
T34	0	32599	0	0
T39	0	2066	0	0
T43	0	32854	0	0
T44	0	32814	0	0
T48	65577	0	0	0

gen_filter_match[6].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34659749	13188083	0	0
T1	34146	34076	0	0
T2	1053	1003	0	0
T3	32843	3	0	0
T4	86	10	0	0
T5	41235	4	0	0
T6	24943	21843	0	0
T7	1143	1088	0	0
T8	97541	65330	0	0
T9	41164	3	0	0
T10	40869	8565	0	0

gen_filter_match[6].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34659749	66076	0	0
T11	67826	1	0	0
T12	102428	0	0	0
T13	101384	0	0	0
T34	32848	0	0	0
T37	1181	0	0	0
T38	1212	0	0	0
T39	2588	0	0	0
T40	25068	0	0	0
T41	90	0	0	0
T48	65577	0	0	0
T90	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T163	0	1	0	0
T185	0	1	0	0
T186	0	1	0	0
T195	0	33410	0	0
T196	0	3	0	0
T197	0	2	0	0

gen_filter_match[6].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34659749	32680	0	0
T11	67826	1	0	0
T12	102428	0	0	0
T13	101384	0	0	0
T34	32848	0	0	0
T37	1181	0	0	0
T38	1212	0	0	0
T39	2588	0	0	0
T40	25068	0	0	0
T41	90	0	0	0
T42	0	1	0	0
T48	65577	0	0	0
T55	0	1	0	0
T65	0	1	0	0
T140	0	1	0	0
T154	0	1	0	0
T163	0	1	0	0
T164	0	1	0	0
T180	0	1	0	0
T192	0	1	0	0

gen_filter_match[6].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34659749	21053961	0	0
T3	32843	32768	0	0
T5	41235	41153	0	0
T6	24943	0	0	0
T7	1143	0	0	0
T8	97541	32161	0	0
T9	41164	41068	0	0
T10	40869	31996	0	0
T11	67826	36501	0	0
T12	102428	68873	0	0
T13	101384	67347	0	0
T42	0	33636	0	0
T48	0	32926	0	0

gen_filter_match[7].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34659749	13240668	0	0
T1	34146	4	0	0
T2	1053	1003	0	0
T3	32843	32771	0	0
T4	86	10	0	0
T5	41235	4	0	0
T6	24943	21843	0	0
T7	1143	1088	0	0
T8	97541	65330	0	0
T9	41164	3	0	0
T10	40869	40561	0	0

gen_filter_match[7].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34659749	139855	0	0
T11	67826	1	0	0
T12	102428	0	0	0
T13	101384	0	0	0
T34	32848	0	0	0
T37	1181	0	0	0
T38	1212	0	0	0
T39	2588	0	0	0
T40	25068	0	0	0
T41	90	0	0	0
T48	65577	0	0	0
T55	0	1	0	0
T90	0	1	0	0
T134	0	34399	0	0
T140	0	1	0	0
T144	0	1	0	0
T149	0	4	0	0
T163	0	1	0	0
T181	0	1	0	0
T198	0	1	0	0

gen_filter_match[7].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34659749	73368	0	0
T11	67826	1	0	0
T12	102428	0	0	0
T13	101384	0	0	0
T34	32848	0	0	0
T37	1181	0	0	0
T38	1212	0	0	0
T39	2588	0	0	0
T40	25068	0	0	0
T41	90	0	0	0
T42	0	1	0	0
T48	65577	0	0	0
T55	0	2	0	0
T65	0	1	0	0
T140	0	1	0	0
T160	0	1	0	0
T163	0	1	0	0
T164	0	1	0	0
T180	0	1	0	0
T192	0	1	0	0

gen_filter_match[7].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34659749	20886909	0	0
T1	34146	34072	0	0
T2	1053	0	0	0
T3	32843	0	0	0
T5	41235	41153	0	0
T6	24943	0	0	0
T7	1143	0	0	0
T8	97541	32161	0	0
T9	41164	41068	0	0
T10	40869	0	0	0
T11	67826	36501	0	0
T13	0	65888	0	0
T42	0	33636	0	0
T48	0	32569	0	0
T55	0	65825	0	0
T65	0	33692	0	0