Line Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Module :
prim_pulse_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_pulse_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
347265 |
0 |
0 |
T1 |
660723 |
29 |
0 |
0 |
T2 |
10848623 |
105 |
0 |
0 |
T3 |
7212998 |
70 |
0 |
0 |
T4 |
15912719 |
70 |
0 |
0 |
T5 |
3652407 |
35 |
0 |
0 |
T6 |
4151304 |
70 |
0 |
0 |
T7 |
5508435 |
25 |
0 |
0 |
T8 |
9016677 |
35 |
0 |
0 |
T9 |
4068702 |
39 |
0 |
0 |
T10 |
2918056 |
61 |
0 |
0 |
T11 |
14322857 |
64 |
0 |
0 |
T12 |
0 |
96 |
0 |
0 |
T13 |
0 |
64 |
0 |
0 |
T14 |
0 |
32 |
0 |
0 |
T34 |
3716 |
45 |
0 |
0 |
T35 |
22043 |
46 |
0 |
0 |
T36 |
7048 |
0 |
0 |
0 |
T37 |
1173 |
0 |
0 |
0 |
T38 |
66 |
0 |
0 |
0 |
T39 |
5460 |
0 |
0 |
0 |
T40 |
39618 |
0 |
0 |
0 |
T41 |
96484 |
0 |
0 |
0 |
T42 |
36434 |
0 |
0 |
0 |
T43 |
79582 |
0 |
0 |
0 |
T54 |
0 |
50 |
0 |
0 |
T109 |
0 |
20 |
0 |
0 |
T132 |
0 |
20 |
0 |
0 |
T133 |
0 |
9 |
0 |
0 |
T134 |
0 |
20 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
350243 |
0 |
0 |
T1 |
331350 |
29 |
0 |
0 |
T2 |
10471110 |
105 |
0 |
0 |
T3 |
6961998 |
70 |
0 |
0 |
T4 |
15201173 |
70 |
0 |
0 |
T5 |
3524742 |
35 |
0 |
0 |
T6 |
4059921 |
70 |
0 |
0 |
T7 |
5219641 |
25 |
0 |
0 |
T8 |
8613490 |
35 |
0 |
0 |
T9 |
3870943 |
39 |
0 |
0 |
T10 |
2766846 |
61 |
0 |
0 |
T11 |
14322857 |
64 |
0 |
0 |
T12 |
0 |
96 |
0 |
0 |
T13 |
0 |
64 |
0 |
0 |
T14 |
0 |
32 |
0 |
0 |
T34 |
446051 |
45 |
0 |
0 |
T35 |
105811 |
46 |
0 |
0 |
T36 |
345418 |
0 |
0 |
0 |
T37 |
569355 |
0 |
0 |
0 |
T38 |
16022 |
0 |
0 |
0 |
T39 |
573466 |
0 |
0 |
0 |
T40 |
990484 |
0 |
0 |
0 |
T41 |
241213 |
0 |
0 |
0 |
T42 |
874471 |
0 |
0 |
0 |
T43 |
994795 |
0 |
0 |
0 |
T54 |
0 |
51 |
0 |
0 |
T109 |
0 |
20 |
0 |
0 |
T132 |
0 |
20 |
0 |
0 |
T133 |
0 |
9 |
0 |
0 |
T134 |
0 |
20 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 5 | 2 | 40.00 |
Logical | 5 | 2 | 40.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Unreachable | |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 5 | 2 | 40.00 |
Logical | 5 | 2 | 40.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Unreachable | |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 6 | 75.00 |
Logical | 8 | 6 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T34,T45,T15 |
1 | 0 | Covered | T34,T45,T15 |
1 | 1 | Not Covered | |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T34,T45,T15 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T34,T45,T15 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
81 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
0 |
1 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T34 |
3716 |
1 |
0 |
0 |
T35 |
22043 |
0 |
0 |
0 |
T36 |
7048 |
0 |
0 |
0 |
T37 |
1173 |
0 |
0 |
0 |
T38 |
66 |
0 |
0 |
0 |
T39 |
5460 |
0 |
0 |
0 |
T40 |
39618 |
0 |
0 |
0 |
T41 |
96484 |
0 |
0 |
0 |
T42 |
36434 |
0 |
0 |
0 |
T43 |
79582 |
0 |
0 |
0 |
T45 |
0 |
1 |
0 |
0 |
T46 |
0 |
1 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
T48 |
0 |
1 |
0 |
0 |
T49 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
369 |
0 |
0 |
T15 |
0 |
5 |
0 |
0 |
T16 |
0 |
5 |
0 |
0 |
T17 |
0 |
9 |
0 |
0 |
T18 |
0 |
5 |
0 |
0 |
T34 |
446051 |
3 |
0 |
0 |
T35 |
105811 |
0 |
0 |
0 |
T36 |
345418 |
0 |
0 |
0 |
T37 |
569355 |
0 |
0 |
0 |
T38 |
16022 |
0 |
0 |
0 |
T39 |
573466 |
0 |
0 |
0 |
T40 |
990484 |
0 |
0 |
0 |
T41 |
241213 |
0 |
0 |
0 |
T42 |
874471 |
0 |
0 |
0 |
T43 |
994795 |
0 |
0 |
0 |
T45 |
0 |
10 |
0 |
0 |
T46 |
0 |
10 |
0 |
0 |
T47 |
0 |
10 |
0 |
0 |
T48 |
0 |
9 |
0 |
0 |
T49 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
38161 |
0 |
0 |
T1 |
659 |
25 |
0 |
0 |
T2 |
99348 |
9 |
0 |
0 |
T3 |
66054 |
6 |
0 |
0 |
T4 |
64685 |
6 |
0 |
0 |
T5 |
33156 |
3 |
0 |
0 |
T6 |
65271 |
6 |
0 |
0 |
T7 |
577 |
21 |
0 |
0 |
T8 |
36652 |
3 |
0 |
0 |
T9 |
8413 |
39 |
0 |
0 |
T10 |
1218 |
41 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
38310 |
0 |
0 |
T1 |
330032 |
25 |
0 |
0 |
T2 |
476861 |
9 |
0 |
0 |
T3 |
317054 |
6 |
0 |
0 |
T4 |
776231 |
6 |
0 |
0 |
T5 |
160821 |
3 |
0 |
0 |
T6 |
156654 |
6 |
0 |
0 |
T7 |
289371 |
21 |
0 |
0 |
T8 |
439839 |
3 |
0 |
0 |
T9 |
206172 |
39 |
0 |
0 |
T10 |
152428 |
41 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
38268 |
0 |
0 |
T1 |
330032 |
25 |
0 |
0 |
T2 |
476861 |
9 |
0 |
0 |
T3 |
317054 |
6 |
0 |
0 |
T4 |
776231 |
6 |
0 |
0 |
T5 |
160821 |
3 |
0 |
0 |
T6 |
156654 |
6 |
0 |
0 |
T7 |
289371 |
21 |
0 |
0 |
T8 |
439839 |
3 |
0 |
0 |
T9 |
206172 |
39 |
0 |
0 |
T10 |
152428 |
41 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
38275 |
0 |
0 |
T1 |
659 |
25 |
0 |
0 |
T2 |
99348 |
9 |
0 |
0 |
T3 |
66054 |
6 |
0 |
0 |
T4 |
64685 |
6 |
0 |
0 |
T5 |
33156 |
3 |
0 |
0 |
T6 |
65271 |
6 |
0 |
0 |
T7 |
577 |
21 |
0 |
0 |
T8 |
36652 |
3 |
0 |
0 |
T9 |
8413 |
39 |
0 |
0 |
T10 |
1218 |
41 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
18032 |
0 |
0 |
T1 |
659 |
12 |
0 |
0 |
T2 |
99348 |
6 |
0 |
0 |
T3 |
66054 |
4 |
0 |
0 |
T4 |
64685 |
4 |
0 |
0 |
T5 |
33156 |
2 |
0 |
0 |
T6 |
65271 |
4 |
0 |
0 |
T7 |
577 |
10 |
0 |
0 |
T8 |
36652 |
2 |
0 |
0 |
T9 |
8413 |
19 |
0 |
0 |
T10 |
1218 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
18142 |
0 |
0 |
T1 |
330032 |
12 |
0 |
0 |
T2 |
476861 |
6 |
0 |
0 |
T3 |
317054 |
4 |
0 |
0 |
T4 |
776231 |
4 |
0 |
0 |
T5 |
160821 |
2 |
0 |
0 |
T6 |
156654 |
4 |
0 |
0 |
T7 |
289371 |
10 |
0 |
0 |
T8 |
439839 |
2 |
0 |
0 |
T9 |
206172 |
19 |
0 |
0 |
T10 |
152428 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
18130 |
0 |
0 |
T1 |
330032 |
12 |
0 |
0 |
T2 |
476861 |
6 |
0 |
0 |
T3 |
317054 |
4 |
0 |
0 |
T4 |
776231 |
4 |
0 |
0 |
T5 |
160821 |
2 |
0 |
0 |
T6 |
156654 |
4 |
0 |
0 |
T7 |
289371 |
10 |
0 |
0 |
T8 |
439839 |
2 |
0 |
0 |
T9 |
206172 |
19 |
0 |
0 |
T10 |
152428 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
18130 |
0 |
0 |
T1 |
659 |
12 |
0 |
0 |
T2 |
99348 |
6 |
0 |
0 |
T3 |
66054 |
4 |
0 |
0 |
T4 |
64685 |
4 |
0 |
0 |
T5 |
33156 |
2 |
0 |
0 |
T6 |
65271 |
4 |
0 |
0 |
T7 |
577 |
10 |
0 |
0 |
T8 |
36652 |
2 |
0 |
0 |
T9 |
8413 |
19 |
0 |
0 |
T10 |
1218 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
13925 |
0 |
0 |
T2 |
99348 |
3 |
0 |
0 |
T3 |
66054 |
2 |
0 |
0 |
T4 |
64685 |
2 |
0 |
0 |
T5 |
33156 |
1 |
0 |
0 |
T6 |
65271 |
2 |
0 |
0 |
T7 |
577 |
0 |
0 |
0 |
T8 |
36652 |
1 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
0 |
0 |
0 |
T11 |
64809 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
14083 |
0 |
0 |
T2 |
476861 |
3 |
0 |
0 |
T3 |
317054 |
2 |
0 |
0 |
T4 |
776231 |
2 |
0 |
0 |
T5 |
160821 |
1 |
0 |
0 |
T6 |
156654 |
2 |
0 |
0 |
T7 |
289371 |
0 |
0 |
0 |
T8 |
439839 |
1 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
0 |
0 |
0 |
T11 |
777712 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
14043 |
0 |
0 |
T2 |
476861 |
3 |
0 |
0 |
T3 |
317054 |
2 |
0 |
0 |
T4 |
776231 |
2 |
0 |
0 |
T5 |
160821 |
1 |
0 |
0 |
T6 |
156654 |
2 |
0 |
0 |
T7 |
289371 |
0 |
0 |
0 |
T8 |
439839 |
1 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
0 |
0 |
0 |
T11 |
777712 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
14044 |
0 |
0 |
T2 |
99348 |
3 |
0 |
0 |
T3 |
66054 |
2 |
0 |
0 |
T4 |
64685 |
2 |
0 |
0 |
T5 |
33156 |
1 |
0 |
0 |
T6 |
65271 |
2 |
0 |
0 |
T7 |
577 |
0 |
0 |
0 |
T8 |
36652 |
1 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
0 |
0 |
0 |
T11 |
64809 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
13924 |
0 |
0 |
T2 |
99348 |
3 |
0 |
0 |
T3 |
66054 |
2 |
0 |
0 |
T4 |
64685 |
2 |
0 |
0 |
T5 |
33156 |
1 |
0 |
0 |
T6 |
65271 |
2 |
0 |
0 |
T7 |
577 |
0 |
0 |
0 |
T8 |
36652 |
1 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
0 |
0 |
0 |
T11 |
64809 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
14085 |
0 |
0 |
T2 |
476861 |
3 |
0 |
0 |
T3 |
317054 |
2 |
0 |
0 |
T4 |
776231 |
2 |
0 |
0 |
T5 |
160821 |
1 |
0 |
0 |
T6 |
156654 |
2 |
0 |
0 |
T7 |
289371 |
0 |
0 |
0 |
T8 |
439839 |
1 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
0 |
0 |
0 |
T11 |
777712 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
14047 |
0 |
0 |
T2 |
476861 |
3 |
0 |
0 |
T3 |
317054 |
2 |
0 |
0 |
T4 |
776231 |
2 |
0 |
0 |
T5 |
160821 |
1 |
0 |
0 |
T6 |
156654 |
2 |
0 |
0 |
T7 |
289371 |
0 |
0 |
0 |
T8 |
439839 |
1 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
0 |
0 |
0 |
T11 |
777712 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
14050 |
0 |
0 |
T2 |
99348 |
3 |
0 |
0 |
T3 |
66054 |
2 |
0 |
0 |
T4 |
64685 |
2 |
0 |
0 |
T5 |
33156 |
1 |
0 |
0 |
T6 |
65271 |
2 |
0 |
0 |
T7 |
577 |
0 |
0 |
0 |
T8 |
36652 |
1 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
0 |
0 |
0 |
T11 |
64809 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
19577 |
0 |
0 |
T2 |
99348 |
6 |
0 |
0 |
T3 |
66054 |
4 |
0 |
0 |
T4 |
64685 |
4 |
0 |
0 |
T5 |
33156 |
2 |
0 |
0 |
T6 |
65271 |
4 |
0 |
0 |
T7 |
577 |
0 |
0 |
0 |
T8 |
36652 |
2 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
0 |
0 |
0 |
T11 |
64809 |
4 |
0 |
0 |
T12 |
0 |
6 |
0 |
0 |
T13 |
0 |
4 |
0 |
0 |
T14 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
19685 |
0 |
0 |
T2 |
476861 |
6 |
0 |
0 |
T3 |
317054 |
4 |
0 |
0 |
T4 |
776231 |
4 |
0 |
0 |
T5 |
160821 |
2 |
0 |
0 |
T6 |
156654 |
4 |
0 |
0 |
T7 |
289371 |
0 |
0 |
0 |
T8 |
439839 |
2 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
0 |
0 |
0 |
T11 |
777712 |
4 |
0 |
0 |
T12 |
0 |
6 |
0 |
0 |
T13 |
0 |
4 |
0 |
0 |
T14 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
19675 |
0 |
0 |
T2 |
476861 |
6 |
0 |
0 |
T3 |
317054 |
4 |
0 |
0 |
T4 |
776231 |
4 |
0 |
0 |
T5 |
160821 |
2 |
0 |
0 |
T6 |
156654 |
4 |
0 |
0 |
T7 |
289371 |
0 |
0 |
0 |
T8 |
439839 |
2 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
0 |
0 |
0 |
T11 |
777712 |
4 |
0 |
0 |
T12 |
0 |
6 |
0 |
0 |
T13 |
0 |
4 |
0 |
0 |
T14 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
19675 |
0 |
0 |
T2 |
99348 |
6 |
0 |
0 |
T3 |
66054 |
4 |
0 |
0 |
T4 |
64685 |
4 |
0 |
0 |
T5 |
33156 |
2 |
0 |
0 |
T6 |
65271 |
4 |
0 |
0 |
T7 |
577 |
0 |
0 |
0 |
T8 |
36652 |
2 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
0 |
0 |
0 |
T11 |
64809 |
4 |
0 |
0 |
T12 |
0 |
6 |
0 |
0 |
T13 |
0 |
4 |
0 |
0 |
T14 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
1983 |
0 |
0 |
T2 |
99348 |
3 |
0 |
0 |
T3 |
66054 |
2 |
0 |
0 |
T4 |
64685 |
2 |
0 |
0 |
T5 |
33156 |
1 |
0 |
0 |
T6 |
65271 |
2 |
0 |
0 |
T7 |
577 |
0 |
0 |
0 |
T8 |
36652 |
1 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
0 |
0 |
0 |
T11 |
64809 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2095 |
0 |
0 |
T2 |
476861 |
3 |
0 |
0 |
T3 |
317054 |
2 |
0 |
0 |
T4 |
776231 |
2 |
0 |
0 |
T5 |
160821 |
1 |
0 |
0 |
T6 |
156654 |
2 |
0 |
0 |
T7 |
289371 |
0 |
0 |
0 |
T8 |
439839 |
1 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
0 |
0 |
0 |
T11 |
777712 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2086 |
0 |
0 |
T2 |
476861 |
3 |
0 |
0 |
T3 |
317054 |
2 |
0 |
0 |
T4 |
776231 |
2 |
0 |
0 |
T5 |
160821 |
1 |
0 |
0 |
T6 |
156654 |
2 |
0 |
0 |
T7 |
289371 |
0 |
0 |
0 |
T8 |
439839 |
1 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
0 |
0 |
0 |
T11 |
777712 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
2087 |
0 |
0 |
T2 |
99348 |
3 |
0 |
0 |
T3 |
66054 |
2 |
0 |
0 |
T4 |
64685 |
2 |
0 |
0 |
T5 |
33156 |
1 |
0 |
0 |
T6 |
65271 |
2 |
0 |
0 |
T7 |
577 |
0 |
0 |
0 |
T8 |
36652 |
1 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
0 |
0 |
0 |
T11 |
64809 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
1903 |
0 |
0 |
T2 |
99348 |
3 |
0 |
0 |
T3 |
66054 |
2 |
0 |
0 |
T4 |
64685 |
2 |
0 |
0 |
T5 |
33156 |
1 |
0 |
0 |
T6 |
65271 |
2 |
0 |
0 |
T7 |
577 |
0 |
0 |
0 |
T8 |
36652 |
1 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
0 |
0 |
0 |
T11 |
64809 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2016 |
0 |
0 |
T2 |
476861 |
3 |
0 |
0 |
T3 |
317054 |
2 |
0 |
0 |
T4 |
776231 |
2 |
0 |
0 |
T5 |
160821 |
1 |
0 |
0 |
T6 |
156654 |
2 |
0 |
0 |
T7 |
289371 |
0 |
0 |
0 |
T8 |
439839 |
1 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
0 |
0 |
0 |
T11 |
777712 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2007 |
0 |
0 |
T2 |
476861 |
3 |
0 |
0 |
T3 |
317054 |
2 |
0 |
0 |
T4 |
776231 |
2 |
0 |
0 |
T5 |
160821 |
1 |
0 |
0 |
T6 |
156654 |
2 |
0 |
0 |
T7 |
289371 |
0 |
0 |
0 |
T8 |
439839 |
1 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
0 |
0 |
0 |
T11 |
777712 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
2007 |
0 |
0 |
T2 |
99348 |
3 |
0 |
0 |
T3 |
66054 |
2 |
0 |
0 |
T4 |
64685 |
2 |
0 |
0 |
T5 |
33156 |
1 |
0 |
0 |
T6 |
65271 |
2 |
0 |
0 |
T7 |
577 |
0 |
0 |
0 |
T8 |
36652 |
1 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
0 |
0 |
0 |
T11 |
64809 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
1892 |
0 |
0 |
T2 |
99348 |
3 |
0 |
0 |
T3 |
66054 |
2 |
0 |
0 |
T4 |
64685 |
2 |
0 |
0 |
T5 |
33156 |
1 |
0 |
0 |
T6 |
65271 |
2 |
0 |
0 |
T7 |
577 |
0 |
0 |
0 |
T8 |
36652 |
1 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
0 |
0 |
0 |
T11 |
64809 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2002 |
0 |
0 |
T2 |
476861 |
3 |
0 |
0 |
T3 |
317054 |
2 |
0 |
0 |
T4 |
776231 |
2 |
0 |
0 |
T5 |
160821 |
1 |
0 |
0 |
T6 |
156654 |
2 |
0 |
0 |
T7 |
289371 |
0 |
0 |
0 |
T8 |
439839 |
1 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
0 |
0 |
0 |
T11 |
777712 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1992 |
0 |
0 |
T2 |
476861 |
3 |
0 |
0 |
T3 |
317054 |
2 |
0 |
0 |
T4 |
776231 |
2 |
0 |
0 |
T5 |
160821 |
1 |
0 |
0 |
T6 |
156654 |
2 |
0 |
0 |
T7 |
289371 |
0 |
0 |
0 |
T8 |
439839 |
1 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
0 |
0 |
0 |
T11 |
777712 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
1993 |
0 |
0 |
T2 |
99348 |
3 |
0 |
0 |
T3 |
66054 |
2 |
0 |
0 |
T4 |
64685 |
2 |
0 |
0 |
T5 |
33156 |
1 |
0 |
0 |
T6 |
65271 |
2 |
0 |
0 |
T7 |
577 |
0 |
0 |
0 |
T8 |
36652 |
1 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
0 |
0 |
0 |
T11 |
64809 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
1886 |
0 |
0 |
T2 |
99348 |
3 |
0 |
0 |
T3 |
66054 |
2 |
0 |
0 |
T4 |
64685 |
2 |
0 |
0 |
T5 |
33156 |
1 |
0 |
0 |
T6 |
65271 |
2 |
0 |
0 |
T7 |
577 |
0 |
0 |
0 |
T8 |
36652 |
1 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
0 |
0 |
0 |
T11 |
64809 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1995 |
0 |
0 |
T2 |
476861 |
3 |
0 |
0 |
T3 |
317054 |
2 |
0 |
0 |
T4 |
776231 |
2 |
0 |
0 |
T5 |
160821 |
1 |
0 |
0 |
T6 |
156654 |
2 |
0 |
0 |
T7 |
289371 |
0 |
0 |
0 |
T8 |
439839 |
1 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
0 |
0 |
0 |
T11 |
777712 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1985 |
0 |
0 |
T2 |
476861 |
3 |
0 |
0 |
T3 |
317054 |
2 |
0 |
0 |
T4 |
776231 |
2 |
0 |
0 |
T5 |
160821 |
1 |
0 |
0 |
T6 |
156654 |
2 |
0 |
0 |
T7 |
289371 |
0 |
0 |
0 |
T8 |
439839 |
1 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
0 |
0 |
0 |
T11 |
777712 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
1986 |
0 |
0 |
T2 |
99348 |
3 |
0 |
0 |
T3 |
66054 |
2 |
0 |
0 |
T4 |
64685 |
2 |
0 |
0 |
T5 |
33156 |
1 |
0 |
0 |
T6 |
65271 |
2 |
0 |
0 |
T7 |
577 |
0 |
0 |
0 |
T8 |
36652 |
1 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
0 |
0 |
0 |
T11 |
64809 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
1882 |
0 |
0 |
T2 |
99348 |
3 |
0 |
0 |
T3 |
66054 |
2 |
0 |
0 |
T4 |
64685 |
2 |
0 |
0 |
T5 |
33156 |
1 |
0 |
0 |
T6 |
65271 |
2 |
0 |
0 |
T7 |
577 |
0 |
0 |
0 |
T8 |
36652 |
1 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
0 |
0 |
0 |
T11 |
64809 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1993 |
0 |
0 |
T2 |
476861 |
3 |
0 |
0 |
T3 |
317054 |
2 |
0 |
0 |
T4 |
776231 |
2 |
0 |
0 |
T5 |
160821 |
1 |
0 |
0 |
T6 |
156654 |
2 |
0 |
0 |
T7 |
289371 |
0 |
0 |
0 |
T8 |
439839 |
1 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
0 |
0 |
0 |
T11 |
777712 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1984 |
0 |
0 |
T2 |
476861 |
3 |
0 |
0 |
T3 |
317054 |
2 |
0 |
0 |
T4 |
776231 |
2 |
0 |
0 |
T5 |
160821 |
1 |
0 |
0 |
T6 |
156654 |
2 |
0 |
0 |
T7 |
289371 |
0 |
0 |
0 |
T8 |
439839 |
1 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
0 |
0 |
0 |
T11 |
777712 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
1984 |
0 |
0 |
T2 |
99348 |
3 |
0 |
0 |
T3 |
66054 |
2 |
0 |
0 |
T4 |
64685 |
2 |
0 |
0 |
T5 |
33156 |
1 |
0 |
0 |
T6 |
65271 |
2 |
0 |
0 |
T7 |
577 |
0 |
0 |
0 |
T8 |
36652 |
1 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
0 |
0 |
0 |
T11 |
64809 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
1897 |
0 |
0 |
T2 |
99348 |
3 |
0 |
0 |
T3 |
66054 |
2 |
0 |
0 |
T4 |
64685 |
2 |
0 |
0 |
T5 |
33156 |
1 |
0 |
0 |
T6 |
65271 |
2 |
0 |
0 |
T7 |
577 |
0 |
0 |
0 |
T8 |
36652 |
1 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
0 |
0 |
0 |
T11 |
64809 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2005 |
0 |
0 |
T2 |
476861 |
3 |
0 |
0 |
T3 |
317054 |
2 |
0 |
0 |
T4 |
776231 |
2 |
0 |
0 |
T5 |
160821 |
1 |
0 |
0 |
T6 |
156654 |
2 |
0 |
0 |
T7 |
289371 |
0 |
0 |
0 |
T8 |
439839 |
1 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
0 |
0 |
0 |
T11 |
777712 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1995 |
0 |
0 |
T2 |
476861 |
3 |
0 |
0 |
T3 |
317054 |
2 |
0 |
0 |
T4 |
776231 |
2 |
0 |
0 |
T5 |
160821 |
1 |
0 |
0 |
T6 |
156654 |
2 |
0 |
0 |
T7 |
289371 |
0 |
0 |
0 |
T8 |
439839 |
1 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
0 |
0 |
0 |
T11 |
777712 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
1996 |
0 |
0 |
T2 |
99348 |
3 |
0 |
0 |
T3 |
66054 |
2 |
0 |
0 |
T4 |
64685 |
2 |
0 |
0 |
T5 |
33156 |
1 |
0 |
0 |
T6 |
65271 |
2 |
0 |
0 |
T7 |
577 |
0 |
0 |
0 |
T8 |
36652 |
1 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
0 |
0 |
0 |
T11 |
64809 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
1858 |
0 |
0 |
T2 |
99348 |
3 |
0 |
0 |
T3 |
66054 |
2 |
0 |
0 |
T4 |
64685 |
2 |
0 |
0 |
T5 |
33156 |
1 |
0 |
0 |
T6 |
65271 |
2 |
0 |
0 |
T7 |
577 |
0 |
0 |
0 |
T8 |
36652 |
1 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
0 |
0 |
0 |
T11 |
64809 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1967 |
0 |
0 |
T2 |
476861 |
3 |
0 |
0 |
T3 |
317054 |
2 |
0 |
0 |
T4 |
776231 |
2 |
0 |
0 |
T5 |
160821 |
1 |
0 |
0 |
T6 |
156654 |
2 |
0 |
0 |
T7 |
289371 |
0 |
0 |
0 |
T8 |
439839 |
1 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
0 |
0 |
0 |
T11 |
777712 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1957 |
0 |
0 |
T2 |
476861 |
3 |
0 |
0 |
T3 |
317054 |
2 |
0 |
0 |
T4 |
776231 |
2 |
0 |
0 |
T5 |
160821 |
1 |
0 |
0 |
T6 |
156654 |
2 |
0 |
0 |
T7 |
289371 |
0 |
0 |
0 |
T8 |
439839 |
1 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
0 |
0 |
0 |
T11 |
777712 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
1957 |
0 |
0 |
T2 |
99348 |
3 |
0 |
0 |
T3 |
66054 |
2 |
0 |
0 |
T4 |
64685 |
2 |
0 |
0 |
T5 |
33156 |
1 |
0 |
0 |
T6 |
65271 |
2 |
0 |
0 |
T7 |
577 |
0 |
0 |
0 |
T8 |
36652 |
1 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
0 |
0 |
0 |
T11 |
64809 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
1880 |
0 |
0 |
T2 |
99348 |
3 |
0 |
0 |
T3 |
66054 |
2 |
0 |
0 |
T4 |
64685 |
2 |
0 |
0 |
T5 |
33156 |
1 |
0 |
0 |
T6 |
65271 |
2 |
0 |
0 |
T7 |
577 |
0 |
0 |
0 |
T8 |
36652 |
1 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
0 |
0 |
0 |
T11 |
64809 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1989 |
0 |
0 |
T2 |
476861 |
3 |
0 |
0 |
T3 |
317054 |
2 |
0 |
0 |
T4 |
776231 |
2 |
0 |
0 |
T5 |
160821 |
1 |
0 |
0 |
T6 |
156654 |
2 |
0 |
0 |
T7 |
289371 |
0 |
0 |
0 |
T8 |
439839 |
1 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
0 |
0 |
0 |
T11 |
777712 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1978 |
0 |
0 |
T2 |
476861 |
3 |
0 |
0 |
T3 |
317054 |
2 |
0 |
0 |
T4 |
776231 |
2 |
0 |
0 |
T5 |
160821 |
1 |
0 |
0 |
T6 |
156654 |
2 |
0 |
0 |
T7 |
289371 |
0 |
0 |
0 |
T8 |
439839 |
1 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
0 |
0 |
0 |
T11 |
777712 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
1979 |
0 |
0 |
T2 |
99348 |
3 |
0 |
0 |
T3 |
66054 |
2 |
0 |
0 |
T4 |
64685 |
2 |
0 |
0 |
T5 |
33156 |
1 |
0 |
0 |
T6 |
65271 |
2 |
0 |
0 |
T7 |
577 |
0 |
0 |
0 |
T8 |
36652 |
1 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
0 |
0 |
0 |
T11 |
64809 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
1987 |
0 |
0 |
T2 |
99348 |
3 |
0 |
0 |
T3 |
66054 |
2 |
0 |
0 |
T4 |
64685 |
2 |
0 |
0 |
T5 |
33156 |
1 |
0 |
0 |
T6 |
65271 |
2 |
0 |
0 |
T7 |
577 |
0 |
0 |
0 |
T8 |
36652 |
1 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
0 |
0 |
0 |
T11 |
64809 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2095 |
0 |
0 |
T2 |
476861 |
3 |
0 |
0 |
T3 |
317054 |
2 |
0 |
0 |
T4 |
776231 |
2 |
0 |
0 |
T5 |
160821 |
1 |
0 |
0 |
T6 |
156654 |
2 |
0 |
0 |
T7 |
289371 |
0 |
0 |
0 |
T8 |
439839 |
1 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
0 |
0 |
0 |
T11 |
777712 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2085 |
0 |
0 |
T2 |
476861 |
3 |
0 |
0 |
T3 |
317054 |
2 |
0 |
0 |
T4 |
776231 |
2 |
0 |
0 |
T5 |
160821 |
1 |
0 |
0 |
T6 |
156654 |
2 |
0 |
0 |
T7 |
289371 |
0 |
0 |
0 |
T8 |
439839 |
1 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
0 |
0 |
0 |
T11 |
777712 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
2086 |
0 |
0 |
T2 |
99348 |
3 |
0 |
0 |
T3 |
66054 |
2 |
0 |
0 |
T4 |
64685 |
2 |
0 |
0 |
T5 |
33156 |
1 |
0 |
0 |
T6 |
65271 |
2 |
0 |
0 |
T7 |
577 |
0 |
0 |
0 |
T8 |
36652 |
1 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
0 |
0 |
0 |
T11 |
64809 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
1885 |
0 |
0 |
T2 |
99348 |
3 |
0 |
0 |
T3 |
66054 |
2 |
0 |
0 |
T4 |
64685 |
2 |
0 |
0 |
T5 |
33156 |
1 |
0 |
0 |
T6 |
65271 |
2 |
0 |
0 |
T7 |
577 |
0 |
0 |
0 |
T8 |
36652 |
1 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
0 |
0 |
0 |
T11 |
64809 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1993 |
0 |
0 |
T2 |
476861 |
3 |
0 |
0 |
T3 |
317054 |
2 |
0 |
0 |
T4 |
776231 |
2 |
0 |
0 |
T5 |
160821 |
1 |
0 |
0 |
T6 |
156654 |
2 |
0 |
0 |
T7 |
289371 |
0 |
0 |
0 |
T8 |
439839 |
1 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
0 |
0 |
0 |
T11 |
777712 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1981 |
0 |
0 |
T2 |
476861 |
3 |
0 |
0 |
T3 |
317054 |
2 |
0 |
0 |
T4 |
776231 |
2 |
0 |
0 |
T5 |
160821 |
1 |
0 |
0 |
T6 |
156654 |
2 |
0 |
0 |
T7 |
289371 |
0 |
0 |
0 |
T8 |
439839 |
1 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
0 |
0 |
0 |
T11 |
777712 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
1982 |
0 |
0 |
T2 |
99348 |
3 |
0 |
0 |
T3 |
66054 |
2 |
0 |
0 |
T4 |
64685 |
2 |
0 |
0 |
T5 |
33156 |
1 |
0 |
0 |
T6 |
65271 |
2 |
0 |
0 |
T7 |
577 |
0 |
0 |
0 |
T8 |
36652 |
1 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
0 |
0 |
0 |
T11 |
64809 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
1880 |
0 |
0 |
T2 |
99348 |
3 |
0 |
0 |
T3 |
66054 |
2 |
0 |
0 |
T4 |
64685 |
2 |
0 |
0 |
T5 |
33156 |
1 |
0 |
0 |
T6 |
65271 |
2 |
0 |
0 |
T7 |
577 |
0 |
0 |
0 |
T8 |
36652 |
1 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
0 |
0 |
0 |
T11 |
64809 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1989 |
0 |
0 |
T2 |
476861 |
3 |
0 |
0 |
T3 |
317054 |
2 |
0 |
0 |
T4 |
776231 |
2 |
0 |
0 |
T5 |
160821 |
1 |
0 |
0 |
T6 |
156654 |
2 |
0 |
0 |
T7 |
289371 |
0 |
0 |
0 |
T8 |
439839 |
1 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
0 |
0 |
0 |
T11 |
777712 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1979 |
0 |
0 |
T2 |
476861 |
3 |
0 |
0 |
T3 |
317054 |
2 |
0 |
0 |
T4 |
776231 |
2 |
0 |
0 |
T5 |
160821 |
1 |
0 |
0 |
T6 |
156654 |
2 |
0 |
0 |
T7 |
289371 |
0 |
0 |
0 |
T8 |
439839 |
1 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
0 |
0 |
0 |
T11 |
777712 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
1980 |
0 |
0 |
T2 |
99348 |
3 |
0 |
0 |
T3 |
66054 |
2 |
0 |
0 |
T4 |
64685 |
2 |
0 |
0 |
T5 |
33156 |
1 |
0 |
0 |
T6 |
65271 |
2 |
0 |
0 |
T7 |
577 |
0 |
0 |
0 |
T8 |
36652 |
1 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
0 |
0 |
0 |
T11 |
64809 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
1925 |
0 |
0 |
T2 |
99348 |
3 |
0 |
0 |
T3 |
66054 |
2 |
0 |
0 |
T4 |
64685 |
2 |
0 |
0 |
T5 |
33156 |
1 |
0 |
0 |
T6 |
65271 |
2 |
0 |
0 |
T7 |
577 |
0 |
0 |
0 |
T8 |
36652 |
1 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
0 |
0 |
0 |
T11 |
64809 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2035 |
0 |
0 |
T2 |
476861 |
3 |
0 |
0 |
T3 |
317054 |
2 |
0 |
0 |
T4 |
776231 |
2 |
0 |
0 |
T5 |
160821 |
1 |
0 |
0 |
T6 |
156654 |
2 |
0 |
0 |
T7 |
289371 |
0 |
0 |
0 |
T8 |
439839 |
1 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
0 |
0 |
0 |
T11 |
777712 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2025 |
0 |
0 |
T2 |
476861 |
3 |
0 |
0 |
T3 |
317054 |
2 |
0 |
0 |
T4 |
776231 |
2 |
0 |
0 |
T5 |
160821 |
1 |
0 |
0 |
T6 |
156654 |
2 |
0 |
0 |
T7 |
289371 |
0 |
0 |
0 |
T8 |
439839 |
1 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
0 |
0 |
0 |
T11 |
777712 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
2025 |
0 |
0 |
T2 |
99348 |
3 |
0 |
0 |
T3 |
66054 |
2 |
0 |
0 |
T4 |
64685 |
2 |
0 |
0 |
T5 |
33156 |
1 |
0 |
0 |
T6 |
65271 |
2 |
0 |
0 |
T7 |
577 |
0 |
0 |
0 |
T8 |
36652 |
1 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
0 |
0 |
0 |
T11 |
64809 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
1891 |
0 |
0 |
T2 |
99348 |
3 |
0 |
0 |
T3 |
66054 |
2 |
0 |
0 |
T4 |
64685 |
2 |
0 |
0 |
T5 |
33156 |
1 |
0 |
0 |
T6 |
65271 |
2 |
0 |
0 |
T7 |
577 |
0 |
0 |
0 |
T8 |
36652 |
1 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
0 |
0 |
0 |
T11 |
64809 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2003 |
0 |
0 |
T2 |
476861 |
3 |
0 |
0 |
T3 |
317054 |
2 |
0 |
0 |
T4 |
776231 |
2 |
0 |
0 |
T5 |
160821 |
1 |
0 |
0 |
T6 |
156654 |
2 |
0 |
0 |
T7 |
289371 |
0 |
0 |
0 |
T8 |
439839 |
1 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
0 |
0 |
0 |
T11 |
777712 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1992 |
0 |
0 |
T2 |
476861 |
3 |
0 |
0 |
T3 |
317054 |
2 |
0 |
0 |
T4 |
776231 |
2 |
0 |
0 |
T5 |
160821 |
1 |
0 |
0 |
T6 |
156654 |
2 |
0 |
0 |
T7 |
289371 |
0 |
0 |
0 |
T8 |
439839 |
1 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
0 |
0 |
0 |
T11 |
777712 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
1992 |
0 |
0 |
T2 |
99348 |
3 |
0 |
0 |
T3 |
66054 |
2 |
0 |
0 |
T4 |
64685 |
2 |
0 |
0 |
T5 |
33156 |
1 |
0 |
0 |
T6 |
65271 |
2 |
0 |
0 |
T7 |
577 |
0 |
0 |
0 |
T8 |
36652 |
1 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
0 |
0 |
0 |
T11 |
64809 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
1882 |
0 |
0 |
T2 |
99348 |
3 |
0 |
0 |
T3 |
66054 |
2 |
0 |
0 |
T4 |
64685 |
2 |
0 |
0 |
T5 |
33156 |
1 |
0 |
0 |
T6 |
65271 |
2 |
0 |
0 |
T7 |
577 |
0 |
0 |
0 |
T8 |
36652 |
1 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
0 |
0 |
0 |
T11 |
64809 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1998 |
0 |
0 |
T2 |
476861 |
3 |
0 |
0 |
T3 |
317054 |
2 |
0 |
0 |
T4 |
776231 |
2 |
0 |
0 |
T5 |
160821 |
1 |
0 |
0 |
T6 |
156654 |
2 |
0 |
0 |
T7 |
289371 |
0 |
0 |
0 |
T8 |
439839 |
1 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
0 |
0 |
0 |
T11 |
777712 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1987 |
0 |
0 |
T2 |
476861 |
3 |
0 |
0 |
T3 |
317054 |
2 |
0 |
0 |
T4 |
776231 |
2 |
0 |
0 |
T5 |
160821 |
1 |
0 |
0 |
T6 |
156654 |
2 |
0 |
0 |
T7 |
289371 |
0 |
0 |
0 |
T8 |
439839 |
1 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
0 |
0 |
0 |
T11 |
777712 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
1987 |
0 |
0 |
T2 |
99348 |
3 |
0 |
0 |
T3 |
66054 |
2 |
0 |
0 |
T4 |
64685 |
2 |
0 |
0 |
T5 |
33156 |
1 |
0 |
0 |
T6 |
65271 |
2 |
0 |
0 |
T7 |
577 |
0 |
0 |
0 |
T8 |
36652 |
1 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
0 |
0 |
0 |
T11 |
64809 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
1862 |
0 |
0 |
T2 |
99348 |
3 |
0 |
0 |
T3 |
66054 |
2 |
0 |
0 |
T4 |
64685 |
2 |
0 |
0 |
T5 |
33156 |
1 |
0 |
0 |
T6 |
65271 |
2 |
0 |
0 |
T7 |
577 |
0 |
0 |
0 |
T8 |
36652 |
1 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
0 |
0 |
0 |
T11 |
64809 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1972 |
0 |
0 |
T2 |
476861 |
3 |
0 |
0 |
T3 |
317054 |
2 |
0 |
0 |
T4 |
776231 |
2 |
0 |
0 |
T5 |
160821 |
1 |
0 |
0 |
T6 |
156654 |
2 |
0 |
0 |
T7 |
289371 |
0 |
0 |
0 |
T8 |
439839 |
1 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
0 |
0 |
0 |
T11 |
777712 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1961 |
0 |
0 |
T2 |
476861 |
3 |
0 |
0 |
T3 |
317054 |
2 |
0 |
0 |
T4 |
776231 |
2 |
0 |
0 |
T5 |
160821 |
1 |
0 |
0 |
T6 |
156654 |
2 |
0 |
0 |
T7 |
289371 |
0 |
0 |
0 |
T8 |
439839 |
1 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
0 |
0 |
0 |
T11 |
777712 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
1961 |
0 |
0 |
T2 |
99348 |
3 |
0 |
0 |
T3 |
66054 |
2 |
0 |
0 |
T4 |
64685 |
2 |
0 |
0 |
T5 |
33156 |
1 |
0 |
0 |
T6 |
65271 |
2 |
0 |
0 |
T7 |
577 |
0 |
0 |
0 |
T8 |
36652 |
1 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
0 |
0 |
0 |
T11 |
64809 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
1859 |
0 |
0 |
T2 |
99348 |
3 |
0 |
0 |
T3 |
66054 |
2 |
0 |
0 |
T4 |
64685 |
2 |
0 |
0 |
T5 |
33156 |
1 |
0 |
0 |
T6 |
65271 |
2 |
0 |
0 |
T7 |
577 |
0 |
0 |
0 |
T8 |
36652 |
1 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
0 |
0 |
0 |
T11 |
64809 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1967 |
0 |
0 |
T2 |
476861 |
3 |
0 |
0 |
T3 |
317054 |
2 |
0 |
0 |
T4 |
776231 |
2 |
0 |
0 |
T5 |
160821 |
1 |
0 |
0 |
T6 |
156654 |
2 |
0 |
0 |
T7 |
289371 |
0 |
0 |
0 |
T8 |
439839 |
1 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
0 |
0 |
0 |
T11 |
777712 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1961 |
0 |
0 |
T2 |
476861 |
3 |
0 |
0 |
T3 |
317054 |
2 |
0 |
0 |
T4 |
776231 |
2 |
0 |
0 |
T5 |
160821 |
1 |
0 |
0 |
T6 |
156654 |
2 |
0 |
0 |
T7 |
289371 |
0 |
0 |
0 |
T8 |
439839 |
1 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
0 |
0 |
0 |
T11 |
777712 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
1961 |
0 |
0 |
T2 |
99348 |
3 |
0 |
0 |
T3 |
66054 |
2 |
0 |
0 |
T4 |
64685 |
2 |
0 |
0 |
T5 |
33156 |
1 |
0 |
0 |
T6 |
65271 |
2 |
0 |
0 |
T7 |
577 |
0 |
0 |
0 |
T8 |
36652 |
1 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
0 |
0 |
0 |
T11 |
64809 |
2 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T14 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T3,T8,T13 |
1 | 0 | Covered | T3,T8,T13 |
1 | 1 | Covered | T3,T13,T50 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T3,T8,T13 |
1 | 0 | Covered | T3,T13,T50 |
1 | 1 | Covered | T3,T8,T13 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
1339 |
0 |
0 |
T3 |
66054 |
2 |
0 |
0 |
T4 |
64685 |
0 |
0 |
0 |
T5 |
33156 |
0 |
0 |
0 |
T6 |
65271 |
0 |
0 |
0 |
T7 |
577 |
0 |
0 |
0 |
T8 |
36652 |
1 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
0 |
0 |
0 |
T11 |
64809 |
0 |
0 |
0 |
T12 |
97492 |
0 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
2 |
0 |
0 |
T45 |
0 |
2 |
0 |
0 |
T50 |
0 |
2 |
0 |
0 |
T51 |
0 |
2 |
0 |
0 |
T52 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1448 |
0 |
0 |
T3 |
317054 |
2 |
0 |
0 |
T4 |
776231 |
0 |
0 |
0 |
T5 |
160821 |
0 |
0 |
0 |
T6 |
156654 |
0 |
0 |
0 |
T7 |
289371 |
0 |
0 |
0 |
T8 |
439839 |
1 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
0 |
0 |
0 |
T11 |
777712 |
0 |
0 |
0 |
T12 |
180363 |
0 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
2 |
0 |
0 |
T45 |
0 |
2 |
0 |
0 |
T50 |
0 |
2 |
0 |
0 |
T51 |
0 |
2 |
0 |
0 |
T52 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T3,T8,T13 |
1 | 0 | Covered | T3,T8,T13 |
1 | 1 | Covered | T3,T13,T50 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T3,T8,T13 |
1 | 0 | Covered | T3,T13,T50 |
1 | 1 | Covered | T3,T8,T13 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1438 |
0 |
0 |
T3 |
317054 |
2 |
0 |
0 |
T4 |
776231 |
0 |
0 |
0 |
T5 |
160821 |
0 |
0 |
0 |
T6 |
156654 |
0 |
0 |
0 |
T7 |
289371 |
0 |
0 |
0 |
T8 |
439839 |
1 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
0 |
0 |
0 |
T11 |
777712 |
0 |
0 |
0 |
T12 |
180363 |
0 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
2 |
0 |
0 |
T45 |
0 |
2 |
0 |
0 |
T50 |
0 |
2 |
0 |
0 |
T51 |
0 |
2 |
0 |
0 |
T52 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
1438 |
0 |
0 |
T3 |
66054 |
2 |
0 |
0 |
T4 |
64685 |
0 |
0 |
0 |
T5 |
33156 |
0 |
0 |
0 |
T6 |
65271 |
0 |
0 |
0 |
T7 |
577 |
0 |
0 |
0 |
T8 |
36652 |
1 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
0 |
0 |
0 |
T11 |
64809 |
0 |
0 |
0 |
T12 |
97492 |
0 |
0 |
0 |
T13 |
0 |
2 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
0 |
2 |
0 |
0 |
T45 |
0 |
2 |
0 |
0 |
T50 |
0 |
2 |
0 |
0 |
T51 |
0 |
2 |
0 |
0 |
T52 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T4 |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34607467 |
68068 |
0 |
0 |
T2 |
99348 |
247 |
0 |
0 |
T3 |
66054 |
155 |
0 |
0 |
T4 |
64685 |
125 |
0 |
0 |
T5 |
33156 |
82 |
0 |
0 |
T6 |
65271 |
143 |
0 |
0 |
T7 |
577 |
0 |
0 |
0 |
T8 |
36652 |
83 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
0 |
0 |
0 |
T11 |
64809 |
159 |
0 |
0 |
T12 |
0 |
204 |
0 |
0 |
T13 |
0 |
136 |
0 |
0 |
T14 |
0 |
68 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
68177 |
0 |
0 |
T2 |
476861 |
247 |
0 |
0 |
T3 |
317054 |
155 |
0 |
0 |
T4 |
776231 |
125 |
0 |
0 |
T5 |
160821 |
82 |
0 |
0 |
T6 |
156654 |
143 |
0 |
0 |
T7 |
289371 |
0 |
0 |
0 |
T8 |
439839 |
83 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
0 |
0 |
0 |
T11 |
777712 |
159 |
0 |
0 |
T12 |
0 |
204 |
0 |
0 |
T13 |
0 |
136 |
0 |
0 |
T14 |
0 |
68 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_adc_ctrl_core.u_oneshot_done_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_adc_ctrl_core.u_oneshot_done_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T7,T10 |
1 | 0 | Covered | T1,T7,T10 |
1 | 1 | Covered | T1,T7,T10 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T7,T10 |
1 | 0 | Covered | T1,T7,T10 |
1 | 1 | Covered | T1,T7,T10 |
Branch Coverage for Instance : tb.dut.u_adc_ctrl_core.u_oneshot_done_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_adc_ctrl_core.u_oneshot_done_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
6250 |
0 |
0 |
T1 |
330032 |
4 |
0 |
0 |
T2 |
476861 |
0 |
0 |
0 |
T3 |
317054 |
0 |
0 |
0 |
T4 |
776231 |
0 |
0 |
0 |
T5 |
160821 |
0 |
0 |
0 |
T6 |
156654 |
0 |
0 |
0 |
T7 |
289371 |
4 |
0 |
0 |
T8 |
439839 |
0 |
0 |
0 |
T9 |
206172 |
0 |
0 |
0 |
T10 |
152428 |
20 |
0 |
0 |
T34 |
0 |
45 |
0 |
0 |
T35 |
0 |
46 |
0 |
0 |
T54 |
0 |
50 |
0 |
0 |
T109 |
0 |
20 |
0 |
0 |
T132 |
0 |
20 |
0 |
0 |
T133 |
0 |
9 |
0 |
0 |
T134 |
0 |
20 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34522683 |
6255 |
0 |
0 |
T1 |
659 |
4 |
0 |
0 |
T2 |
99348 |
0 |
0 |
0 |
T3 |
66054 |
0 |
0 |
0 |
T4 |
64685 |
0 |
0 |
0 |
T5 |
33156 |
0 |
0 |
0 |
T6 |
65271 |
0 |
0 |
0 |
T7 |
577 |
4 |
0 |
0 |
T8 |
36652 |
0 |
0 |
0 |
T9 |
8413 |
0 |
0 |
0 |
T10 |
1218 |
20 |
0 |
0 |
T34 |
0 |
45 |
0 |
0 |
T35 |
0 |
46 |
0 |
0 |
T54 |
0 |
51 |
0 |
0 |
T109 |
0 |
20 |
0 |
0 |
T132 |
0 |
20 |
0 |
0 |
T133 |
0 |
9 |
0 |
0 |
T134 |
0 |
20 |
0 |
0 |