Unified Coverage Report :: Module :: adc_ctrl_core

Module : adc_ctrl_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_adc_ctrl_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.83	100.00	99.76		100.00	99.37	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_ctrl_fsm	99.75	100.00	100.00		100.00	98.73	100.00
u_adc_ctrl_intr	99.00	100.00	96.00			100.00	100.00
u_oneshot_done_sync	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
TOTAL		63	63	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	73	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	213	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	8	8
63	8	8
72	1	1
73	1	1
74	1	1
75	1	1
83	1	1
86	1	1
87	1	1
88	1	1
89	1	1
104	8	8
107	8	8
117	8	8
121	8	8
137	1	1
138	1	1
140	1	1
141	1	1
145	1	1
213	1	1

---

Cond Coverage for Module : adc_ctrl_core

	Total	Covered	Percent
Conditions	293	293	100.00
Logical	293	293	100.00
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION (reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done : (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0))
             -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T7,T10

 LINE       83
 SUB-EXPRESSION (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0)
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][0].cond)) ? ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v)) : ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v)))

-1-	Status	Tests
0	Covered	T3,T4,T6
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T6
0	1	Covered	T4,T6,T12
1	0	Covered	T3,T4,T6

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][1].cond)) ? ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v)) : ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v)))

-1-	Status	Tests
0	Covered	T12,T50,T51
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T50,T51
0	1	Covered	T12,T50,T51
1	0	Covered	T12,T50,T51

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][2].cond)) ? ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v)) : ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v)))

-1-	Status	Tests
0	Covered	T3,T4,T6
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T6
0	1	Covered	T3,T4,T6
1	0	Covered	T3,T4,T6

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][3].cond)) ? ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v)) : ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v)))

-1-	Status	Tests
0	Covered	T3,T4,T6
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T6
0	1	Covered	T3,T4,T6
1	0	Covered	T3,T4,T6

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][4].cond)) ? ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v)) : ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v)))

-1-	Status	Tests
0	Covered	T4,T6,T8
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T8
0	1	Covered	T4,T6,T8
1	0	Covered	T4,T6,T8

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][5].cond)) ? ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v)) : ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v)))

-1-	Status	Tests
0	Covered	T3,T4,T6
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T6
0	1	Covered	T3,T4,T6
1	0	Covered	T3,T4,T6

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][6].cond)) ? ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v)) : ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v)))

-1-	Status	Tests
0	Covered	T3,T6,T8
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T8
0	1	Covered	T3,T6,T50
1	0	Covered	T3,T6,T8

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][7].cond)) ? ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v)) : ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v)))

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T5,T6

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][0].cond)) ? ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v)) : ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v)))

-1-	Status	Tests
0	Covered	T3,T6,T50
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T50
0	1	Covered	T3,T6,T50
1	0	Covered	T3,T6,T50

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][1].cond)) ? ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v)) : ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v)))

-1-	Status	Tests
0	Covered	T3,T12,T42
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T12,T42
0	1	Covered	T3,T12,T42
1	0	Covered	T3,T12,T42

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][2].cond)) ? ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v)) : ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v)))

-1-	Status	Tests
0	Covered	T3,T4,T6
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T6
0	1	Covered	T3,T4,T6
1	0	Covered	T3,T4,T6

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][3].cond)) ? ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v)) : ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v)))

-1-	Status	Tests
0	Covered	T3,T4,T6
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T6
0	1	Covered	T3,T4,T6
1	0	Covered	T3,T4,T6

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][4].cond)) ? ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v)) : ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v)))

-1-	Status	Tests
0	Covered	T4,T6,T8
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T8
0	1	Covered	T4,T6,T8
1	0	Covered	T4,T6,T8

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][5].cond)) ? ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v)) : ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v)))

-1-	Status	Tests
0	Covered	T3,T4,T6
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T6
0	1	Covered	T3,T4,T6
1	0	Covered	T3,T4,T6

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][6].cond)) ? ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v)) : ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v)))

-1-	Status	Tests
0	Covered	T3,T6,T8
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T8
0	1	Covered	T3,T6,T8
1	0	Covered	T3,T6,T8

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][7].cond)) ? ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v)) : ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v)))

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T5,T6

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][0].en, aon_filter_ctl[1][0].en})) & 
      2  (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en)) & 
      3  (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T2,T4,T5
1	1	1	Covered	T2,T3,T4

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[0] & aon_filter_ctl[0][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[0] & aon_filter_ctl[1][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][1].en, aon_filter_ctl[1][1].en})) & 
      2  (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en)) & 
      3  (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T2,T3,T4
1	1	1	Covered	T2,T3,T4

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[1] & aon_filter_ctl[0][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[1] & aon_filter_ctl[1][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][2].en, aon_filter_ctl[1][2].en})) & 
      2  (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en)) & 
      3  (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T2,T3,T4
1	1	1	Covered	T2,T3,T4

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[2] & aon_filter_ctl[0][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[2] & aon_filter_ctl[1][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][3].en, aon_filter_ctl[1][3].en})) & 
      2  (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en)) & 
      3  (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T5,T6
1	1	0	Covered	T2,T5,T6
1	1	1	Covered	T2,T5,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[3] & aon_filter_ctl[0][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[3] & aon_filter_ctl[1][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T6

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][4].en, aon_filter_ctl[1][4].en})) & 
      2  (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en)) & 
      3  (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T2,T3,T4
1	1	1	Covered	T2,T3,T4

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[4] & aon_filter_ctl[0][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[4] & aon_filter_ctl[1][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][5].en, aon_filter_ctl[1][5].en})) & 
      2  (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en)) & 
      3  (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T4,T5
1	1	0	Covered	T2,T4,T5
1	1	1	Covered	T2,T4,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[5] & aon_filter_ctl[0][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[5] & aon_filter_ctl[1][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][6].en, aon_filter_ctl[1][6].en})) & 
      2  (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en)) & 
      3  (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T2,T3,T4
1	1	1	Covered	T2,T3,T4

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[6] & aon_filter_ctl[0][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[6] & aon_filter_ctl[1][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][7].en, aon_filter_ctl[1][7].en})) & 
      2  (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en)) & 
      3  (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T5
1	1	0	Covered	T2,T3,T5
1	1	1	Covered	T2,T3,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T5
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[7] & aon_filter_ctl[0][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T5
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[7] & aon_filter_ctl[1][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       121
 EXPRESSION (adc_ctrl_done && match[0])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       121
 EXPRESSION (adc_ctrl_done && match[1])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       121
 EXPRESSION (adc_ctrl_done && match[2])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       121
 EXPRESSION (adc_ctrl_done && match[3])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T5,T6

 LINE       121
 EXPRESSION (adc_ctrl_done && match[4])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       121
 EXPRESSION (adc_ctrl_done && match[5])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T4,T5

 LINE       121
 EXPRESSION (adc_ctrl_done && match[6])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       121
 EXPRESSION (adc_ctrl_done && match[7])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T5

 LINE       140
 EXPRESSION (aon_fsm_trans | reg2hw_i.filter_status.trans.q)
             ------1------   ---------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T13,T50
1	0	Covered	T8,T13,T50

 LINE       145
 EXPRESSION (((|(reg2hw_i.filter_status.match.q & reg2hw_i.adc_wakeup_ctl.match_en.q))) || (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q))
             -------------------------------------1------------------------------------    ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T13,T50
1	0	Covered	T3,T8,T13

 LINE       145
 SUB-EXPRESSION (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q)
                 ---------------1--------------   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T13,T50
1	0	Covered	T13,T50,T51
1	1	Covered	T8,T13,T50

---

Branch Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	83	3	3	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	83	(reg2hw_i.adc_en_ctl.oneshot_mode.q) ? 
-2-:	83	(reg2hw_i.adc_en_ctl.adc_enable.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T7,T10
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T6

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T6,T50

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T12,T50,T51

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T12,T42

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T6

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T6

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T6

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T6

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T8

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T8

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T6

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T6

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T6,T8

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T6,T8

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T6

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T6

---

Assert Coverage for Module : adc_ctrl_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	33	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	33	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxFilters_A	34522683	34214900	0	0
gen_filter_match[0].MatchCheck00_A	34522683	8942264	0	0
gen_filter_match[0].MatchCheck01_A	34522683	3067102	0	0
gen_filter_match[0].MatchCheck10_A	34522683	2996955	0	0
gen_filter_match[0].MatchCheck11_A	34522683	19208579	0	0
gen_filter_match[1].MatchCheck00_A	34522683	11333963	0	0
gen_filter_match[1].MatchCheck01_A	34522683	1240183	0	0
gen_filter_match[1].MatchCheck10_A	34522683	1434734	0	0
gen_filter_match[1].MatchCheck11_A	34522683	20206020	0	0
gen_filter_match[2].MatchCheck00_A	34522683	11859999	0	0
gen_filter_match[2].MatchCheck01_A	34522683	575022	0	0
gen_filter_match[2].MatchCheck10_A	34522683	575092	0	0
gen_filter_match[2].MatchCheck11_A	34522683	21204787	0	0
gen_filter_match[3].MatchCheck00_A	34522683	12445852	0	0
gen_filter_match[3].MatchCheck01_A	34522683	358002	0	0
gen_filter_match[3].MatchCheck10_A	34522683	266963	0	0
gen_filter_match[3].MatchCheck11_A	34522683	21144083	0	0
gen_filter_match[4].MatchCheck00_A	34522683	12957313	0	0
gen_filter_match[4].MatchCheck01_A	34522683	99968	0	0
gen_filter_match[4].MatchCheck10_A	34522683	64693	0	0
gen_filter_match[4].MatchCheck11_A	34522683	21092926	0	0
gen_filter_match[5].MatchCheck00_A	34522683	12722363	0	0
gen_filter_match[5].MatchCheck01_A	34522683	12	0	0
gen_filter_match[5].MatchCheck10_A	34522683	102	0	0
gen_filter_match[5].MatchCheck11_A	34522683	21492423	0	0
gen_filter_match[6].MatchCheck00_A	34522683	12209087	0	0
gen_filter_match[6].MatchCheck01_A	34522683	102569	0	0
gen_filter_match[6].MatchCheck10_A	34522683	74759	0	0
gen_filter_match[6].MatchCheck11_A	34522683	21828485	0	0
gen_filter_match[7].MatchCheck00_A	34522683	11239510	0	0
gen_filter_match[7].MatchCheck01_A	34522683	228946	0	0
gen_filter_match[7].MatchCheck10_A	34522683	238342	0	0
gen_filter_match[7].MatchCheck11_A	34522683	22508102	0	0

MaxFilters_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34522683	34214900	0	0
T1	659	602	0	0
T2	99348	99257	0	0
T3	66054	65980	0	0
T4	64685	64624	0	0
T5	33156	33059	0	0
T6	65271	65211	0	0
T7	577	483	0	0
T8	36652	36574	0	0
T9	8413	8328	0	0
T10	1218	1129	0	0

gen_filter_match[0].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34522683	8942264	0	0
T1	659	602	0	0
T2	99348	4	0	0
T3	66054	33016	0	0
T4	64685	3	0	0
T5	33156	4	0	0
T6	65271	32553	0	0
T7	577	483	0	0
T8	36652	36574	0	0
T9	8413	8328	0	0
T10	1218	1129	0	0

gen_filter_match[0].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34522683	3067102	0	0
T4	64685	32789	0	0
T5	33156	0	0	0
T6	65271	0	0	0
T7	577	0	0	0
T8	36652	0	0	0
T9	8413	0	0	0
T10	1218	0	0	0
T11	64809	0	0	0
T12	97492	0	0	0
T13	79389	0	0	0
T32	0	33639	0	0
T33	0	37896	0	0
T48	0	1373	0	0
T50	0	35731	0	0
T130	0	35027	0	0
T136	0	31147	0	0
T137	0	38774	0	0
T138	0	34255	0	0
T139	0	32509	0	0

gen_filter_match[0].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34522683	2996955	0	0
T3	66054	32964	0	0
T4	64685	0	0	0
T5	33156	0	0	0
T6	65271	0	0	0
T7	577	0	0	0
T8	36652	0	0	0
T9	8413	0	0	0
T10	1218	0	0	0
T11	64809	0	0	0
T12	97492	0	0	0
T25	0	70626	0	0
T31	0	1	0	0
T130	0	37338	0	0
T140	0	31491	0	0
T141	0	32750	0	0
T142	0	65058	0	0
T143	0	33121	0	0
T144	0	34410	0	0
T145	0	32722	0	0

gen_filter_match[0].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34522683	19208579	0	0
T2	99348	99253	0	0
T3	66054	0	0	0
T4	64685	31832	0	0
T5	33156	33055	0	0
T6	65271	32658	0	0
T7	577	0	0	0
T8	36652	0	0	0
T9	8413	0	0	0
T10	1218	0	0	0
T11	64809	64716	0	0
T12	0	32798	0	0
T13	0	79296	0	0
T14	0	32264	0	0
T54	0	151	0	0
T146	0	64975	0	0

gen_filter_match[1].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34522683	11333963	0	0
T1	659	602	0	0
T2	99348	4	0	0
T3	66054	3	0	0
T4	64685	32792	0	0
T5	33156	4	0	0
T6	65271	3	0	0
T7	577	483	0	0
T8	36652	4	0	0
T9	8413	8328	0	0
T10	1218	1129	0	0

gen_filter_match[1].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34522683	1240183	0	0
T46	20259	0	0	0
T47	10991	0	0	0
T57	61837	0	0	0
T60	0	32877	0	0
T91	0	1	0	0
T131	122728	0	0	0
T143	33175	0	0	0
T144	66954	0	0	0
T147	32928	32866	0	0
T148	0	33212	0	0
T149	0	32944	0	0
T150	0	34922	0	0
T151	0	32804	0	0
T152	0	38091	0	0
T153	0	32534	0	0
T154	0	33068	0	0
T155	698	0	0	0
T156	62980	0	0	0
T157	98008	0	0	0

gen_filter_match[1].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34522683	1434734	0	0
T3	66054	33013	0	0
T4	64685	0	0	0
T5	33156	0	0	0
T6	65271	0	0	0
T7	577	0	0	0
T8	36652	0	0	0
T9	8413	0	0	0
T10	1218	0	0	0
T11	64809	0	0	0
T12	97492	0	0	0
T17	0	3	0	0
T31	0	1	0	0
T91	0	1	0	0
T130	0	2	0	0
T135	0	33272	0	0
T136	0	33392	0	0
T140	0	32344	0	0
T145	0	33065	0	0
T158	0	34926	0	0

gen_filter_match[1].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34522683	20206020	0	0
T2	99348	99253	0	0
T3	66054	32964	0	0
T4	64685	31832	0	0
T5	33156	33055	0	0
T6	65271	65208	0	0
T7	577	0	0	0
T8	36652	36570	0	0
T9	8413	0	0	0
T10	1218	0	0	0
T11	64809	64716	0	0
T12	0	32926	0	0
T13	0	79296	0	0
T14	0	32264	0	0

gen_filter_match[2].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34522683	11859999	0	0
T1	659	602	0	0
T2	99348	4	0	0
T3	66054	33016	0	0
T4	64685	3	0	0
T5	33156	4	0	0
T6	65271	3	0	0
T7	577	483	0	0
T8	36652	4	0	0
T9	8413	8328	0	0
T10	1218	1129	0	0

gen_filter_match[2].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34522683	575022	0	0
T17	0	41209	0	0
T46	20259	10113	0	0
T47	10991	0	0	0
T58	19510	0	0	0
T91	0	32280	0	0
T131	122728	0	0	0
T148	65670	0	0	0
T149	65880	0	0	0
T159	0	35733	0	0
T160	0	33305	0	0
T161	0	33784	0	0
T162	0	32074	0	0
T163	0	32040	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	1130	0	0	0
T167	100116	0	0	0
T168	17303	0	0	0
T169	123347	0	0	0

gen_filter_match[2].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34522683	575092	0	0
T4	64685	1	0	0
T5	33156	0	0	0
T6	65271	32658	0	0
T7	577	0	0	0
T8	36652	0	0	0
T9	8413	0	0	0
T10	1218	0	0	0
T11	64809	0	0	0
T12	97492	0	0	0
T13	79389	0	0	0
T14	0	1	0	0
T31	0	1	0	0
T32	0	33621	0	0
T144	0	32480	0	0
T148	0	1	0	0
T169	0	1	0	0
T170	0	34261	0	0
T171	0	1	0	0

gen_filter_match[2].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34522683	21204787	0	0
T2	99348	99253	0	0
T3	66054	32964	0	0
T4	64685	64620	0	0
T5	33156	33055	0	0
T6	65271	32550	0	0
T7	577	0	0	0
T8	36652	36570	0	0
T9	8413	0	0	0
T10	1218	0	0	0
T11	64809	64716	0	0
T12	0	32798	0	0
T13	0	79296	0	0
T14	0	32263	0	0

gen_filter_match[3].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34522683	12445852	0	0
T1	659	602	0	0
T2	99348	4	0	0
T3	66054	65980	0	0
T4	64685	64624	0	0
T5	33156	4	0	0
T6	65271	32661	0	0
T7	577	483	0	0
T8	36652	36574	0	0
T9	8413	8328	0	0
T10	1218	1129	0	0

gen_filter_match[3].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34522683	358002	0	0
T19	0	5435	0	0
T33	72952	34969	0	0
T91	0	1	0	0
T130	0	2	0	0
T138	103954	0	0	0
T140	96535	0	0	0
T141	64170	31353	0	0
T142	97879	0	0	0
T172	0	1	0	0
T173	0	3020	0	0
T174	0	33796	0	0
T175	0	32865	0	0
T176	0	34288	0	0
T177	63818	0	0	0
T178	116966	0	0	0
T179	764	0	0	0
T180	1154	0	0	0
T181	59	0	0	0

gen_filter_match[3].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34522683	266963	0	0
T14	32337	1	0	0
T15	0	2	0	0
T17	0	3	0	0
T18	0	2	0	0
T31	0	2	0	0
T50	70228	0	0	0
T51	68185	0	0	0
T54	19385	0	0	0
T79	77	0	0	0
T130	0	2	0	0
T132	1126	0	0	0
T133	589	0	0	0
T134	1144	0	0	0
T139	0	2	0	0
T146	65041	0	0	0
T148	0	1	0	0
T169	0	1	0	0
T182	0	32695	0	0
T183	5919	0	0	0

gen_filter_match[3].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34522683	21144083	0	0
T2	99348	99253	0	0
T3	66054	0	0	0
T4	64685	0	0	0
T5	33156	33055	0	0
T6	65271	32550	0	0
T7	577	0	0	0
T8	36652	0	0	0
T9	8413	0	0	0
T10	1218	0	0	0
T11	64809	64716	0	0
T12	0	64608	0	0
T13	0	79296	0	0
T14	0	32263	0	0
T50	0	70154	0	0
T146	0	64975	0	0
T184	0	32831	0	0

gen_filter_match[4].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34522683	12957313	0	0
T1	659	602	0	0
T2	99348	4	0	0
T3	66054	32967	0	0
T4	64685	3	0	0
T5	33156	4	0	0
T6	65271	3	0	0
T7	577	483	0	0
T8	36652	4	0	0
T9	8413	8328	0	0
T10	1218	1129	0	0

gen_filter_match[4].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34522683	99968	0	0
T21	17434	0	0	0
T185	104550	1	0	0
T186	0	34822	0	0
T187	0	33116	0	0
T188	0	32027	0	0
T189	0	1	0	0
T190	0	1	0	0
T191	98494	0	0	0
T192	65637	0	0	0
T193	25049	0	0	0
T194	704	0	0	0
T195	74486	0	0	0
T196	34419	0	0	0
T197	99726	0	0	0
T198	655	0	0	0

gen_filter_match[4].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34522683	64693	0	0
T4	64685	1	0	0
T5	33156	0	0	0
T6	65271	0	0	0
T7	577	0	0	0
T8	36652	0	0	0
T9	8413	0	0	0
T10	1218	0	0	0
T11	64809	0	0	0
T12	97492	0	0	0
T13	79389	0	0	0
T14	0	1	0	0
T15	0	3	0	0
T31	0	2	0	0
T50	0	1	0	0
T130	0	2	0	0
T139	0	1	0	0
T145	0	1	0	0
T148	0	1	0	0
T169	0	1	0	0

gen_filter_match[4].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34522683	21092926	0	0
T2	99348	99253	0	0
T3	66054	33013	0	0
T4	64685	64620	0	0
T5	33156	33055	0	0
T6	65271	65208	0	0
T7	577	0	0	0
T8	36652	36570	0	0
T9	8413	0	0	0
T10	1218	0	0	0
T11	64809	64716	0	0
T12	0	31682	0	0
T13	0	79296	0	0
T14	0	32263	0	0

gen_filter_match[5].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34522683	12722363	0	0
T1	659	602	0	0
T2	99348	4	0	0
T3	66054	65980	0	0
T4	64685	3	0	0
T5	33156	4	0	0
T6	65271	65211	0	0
T7	577	483	0	0
T8	36652	4	0	0
T9	8413	8328	0	0
T10	1218	1129	0	0

gen_filter_match[5].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34522683	12	0	0
T46	20259	0	0	0
T47	10991	0	0	0
T57	61837	0	0	0
T130	124134	2	0	0
T143	33175	0	0	0
T144	66954	0	0	0
T147	32928	0	0	0
T155	698	0	0	0
T156	62980	0	0	0
T157	98008	0	0	0
T164	0	1	0	0
T189	0	1	0	0
T190	0	1	0	0
T199	0	1	0	0
T200	0	1	0	0
T201	0	1	0	0
T202	0	1	0	0
T203	0	3	0	0

gen_filter_match[5].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34522683	102	0	0
T4	64685	1	0	0
T5	33156	0	0	0
T6	65271	0	0	0
T7	577	0	0	0
T8	36652	0	0	0
T9	8413	0	0	0
T10	1218	0	0	0
T11	64809	0	0	0
T12	97492	0	0	0
T13	79389	0	0	0
T14	0	1	0	0
T15	0	3	0	0
T31	0	1	0	0
T43	0	1	0	0
T50	0	1	0	0
T130	0	2	0	0
T139	0	2	0	0
T169	0	1	0	0
T204	0	1	0	0

gen_filter_match[5].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34522683	21492423	0	0
T2	99348	99253	0	0
T3	66054	0	0	0
T4	64685	64620	0	0
T5	33156	33055	0	0
T6	65271	0	0	0
T7	577	0	0	0
T8	36652	36570	0	0
T9	8413	0	0	0
T10	1218	0	0	0
T11	64809	64716	0	0
T13	0	79296	0	0
T14	0	32263	0	0
T50	0	70153	0	0
T51	0	68094	0	0
T146	0	64975	0	0

gen_filter_match[6].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34522683	12209087	0	0
T1	659	602	0	0
T2	99348	4	0	0
T3	66054	3	0	0
T4	64685	3	0	0
T5	33156	4	0	0
T6	65271	3	0	0
T7	577	483	0	0
T8	36652	4	0	0
T9	8413	8328	0	0
T10	1218	1129	0	0

gen_filter_match[6].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34522683	102569	0	0
T46	20259	0	0	0
T47	10991	0	0	0
T57	61837	0	0	0
T130	124134	2	0	0
T143	33175	0	0	0
T144	66954	0	0	0
T147	32928	0	0	0
T155	698	0	0	0
T156	62980	0	0	0
T157	98008	0	0	0
T164	0	1	0	0
T185	0	1	0	0
T186	0	1	0	0
T199	0	1	0	0
T205	0	38073	0	0
T206	0	1	0	0
T207	0	32286	0	0
T208	0	32200	0	0
T209	0	1	0	0

gen_filter_match[6].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34522683	74759	0	0
T4	64685	1	0	0
T5	33156	0	0	0
T6	65271	0	0	0
T7	577	0	0	0
T8	36652	0	0	0
T9	8413	0	0	0
T10	1218	0	0	0
T11	64809	0	0	0
T12	97492	0	0	0
T13	79389	0	0	0
T14	0	1	0	0
T15	0	3	0	0
T31	0	1	0	0
T43	0	1	0	0
T47	0	5776	0	0
T50	0	1	0	0
T130	0	4	0	0
T148	0	1	0	0
T204	0	1	0	0

gen_filter_match[6].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34522683	21828485	0	0
T2	99348	99253	0	0
T3	66054	65977	0	0
T4	64685	64620	0	0
T5	33156	33055	0	0
T6	65271	65208	0	0
T7	577	0	0	0
T8	36652	36570	0	0
T9	8413	0	0	0
T10	1218	0	0	0
T11	64809	64716	0	0
T12	0	31682	0	0
T13	0	79296	0	0
T14	0	32263	0	0

gen_filter_match[7].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34522683	11239510	0	0
T1	659	602	0	0
T2	99348	4	0	0
T3	66054	32967	0	0
T4	64685	64624	0	0
T5	33156	4	0	0
T6	65271	3	0	0
T7	577	483	0	0
T8	36652	4	0	0
T9	8413	8328	0	0
T10	1218	1129	0	0

gen_filter_match[7].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34522683	228946	0	0
T23	0	1153	0	0
T46	20259	0	0	0
T47	10991	0	0	0
T57	61837	0	0	0
T91	0	32936	0	0
T130	124134	51676	0	0
T143	33175	0	0	0
T144	66954	0	0	0
T147	32928	0	0	0
T155	698	0	0	0
T156	62980	0	0	0
T157	98008	0	0	0
T164	0	1	0	0
T172	0	1	0	0
T186	0	1	0	0
T201	0	1	0	0
T210	0	32715	0	0
T211	0	1	0	0
T212	0	33476	0	0

gen_filter_match[7].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34522683	238342	0	0
T14	32337	1	0	0
T17	0	4	0	0
T31	0	1	0	0
T43	0	1	0	0
T50	70228	1	0	0
T51	68185	0	0	0
T54	19385	0	0	0
T79	77	0	0	0
T132	1126	0	0	0
T133	589	0	0	0
T134	1144	0	0	0
T145	0	1	0	0
T146	65041	0	0	0
T169	0	1	0	0
T171	0	1	0	0
T183	5919	0	0	0
T204	0	1	0	0
T213	0	1	0	0

gen_filter_match[7].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34522683	22508102	0	0
T2	99348	99253	0	0
T3	66054	33013	0	0
T4	64685	0	0	0
T5	33156	33055	0	0
T6	65271	65208	0	0
T7	577	0	0	0
T8	36652	36570	0	0
T9	8413	0	0	0
T10	1218	0	0	0
T11	64809	64716	0	0
T12	0	65724	0	0
T13	0	79296	0	0
T14	0	32263	0	0
T146	0	64975	0	0