Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1139398	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1119953

1

T1

1231

T2

1404

T3

4040

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1976607	1			T1	2453		T2	2521		T3	7546
values[0x0]	140535	1			T1	109		T2	161		T3	355
values[0x1]	142209	1			T1	124		T2	152		T3	365

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	912135	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1347216

1

T1

1498

T2

1685

T3

4869

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7290	1			T1	15		T2	7		T3	8
valid_sources[0x01]	7075	1			T1	16		T2	18		T3	40
valid_sources[0x02]	14242	1			T1	7		T2	11		T3	26
valid_sources[0x03]	7443	1			T1	11		T2	14		T3	7
valid_sources[0x04]	7542	1			T1	15		T3	34		T4	2
valid_sources[0x05]	9998	1			T1	12		T2	6		T3	13
valid_sources[0x06]	6858	1			T1	25		T2	7		T3	90
valid_sources[0x07]	6522	1			T1	11		T2	5		T3	19
valid_sources[0x08]	8216	1			T1	5		T2	12		T3	5
valid_sources[0x09]	8312	1			T1	8		T2	3		T3	21
valid_sources[0x0a]	11118	1			T1	3		T2	16		T3	9
valid_sources[0x0b]	11285	1			T1	14		T2	10		T3	16
valid_sources[0x0c]	7083	1			T1	9		T2	15		T3	15
valid_sources[0x0d]	8025	1			T1	11		T2	11		T3	17
valid_sources[0x0e]	11467	1			T1	8		T2	18		T3	29
valid_sources[0x0f]	6911	1			T1	5		T2	2		T3	7
valid_sources[0x10]	8219	1			T1	3		T2	12		T3	8
valid_sources[0x11]	9456	1			T1	14		T2	25		T3	4
valid_sources[0x12]	10066	1			T1	10		T2	20		T3	7
valid_sources[0x13]	7573	1			T1	12		T2	4		T3	16
valid_sources[0x14]	6661	1			T1	14		T2	3		T3	16
valid_sources[0x15]	8111	1			T1	11		T2	6		T3	17
valid_sources[0x16]	7999	1			T1	4		T2	23		T3	15
valid_sources[0x17]	12858	1			T1	13		T2	9		T3	10
valid_sources[0x18]	7229	1			T1	10		T2	9		T3	8
valid_sources[0x19]	7078	1			T1	3		T2	5		T3	25
valid_sources[0x1a]	16560	1			T1	12		T2	10		T3	9
valid_sources[0x1b]	22597	1			T1	15		T2	17		T3	16
valid_sources[0x1c]	11586	1			T1	12		T2	2		T3	11
valid_sources[0x1d]	11492	1			T1	4		T2	9		T3	8
valid_sources[0x1e]	6967	1			T1	6		T2	2		T3	20
valid_sources[0x1f]	6930	1			T1	13		T2	11		T3	3
valid_sources[0x20]	7437	1			T1	16		T2	5		T3	12
valid_sources[0x21]	11389	1			T1	9		T2	23		T3	26
valid_sources[0x22]	15907	1			T1	4		T2	25		T3	41
valid_sources[0x23]	7127	1			T1	4		T2	3		T3	33
valid_sources[0x24]	9017	1			T1	12		T2	8		T3	38
valid_sources[0x25]	6732	1			T1	7		T2	4		T3	4
valid_sources[0x26]	11389	1			T1	15		T2	10		T3	7
valid_sources[0x27]	6812	1			T1	6		T2	8		T3	30
valid_sources[0x28]	7313	1			T1	13		T2	10		T3	7
valid_sources[0x29]	8095	1			T1	7		T2	17		T3	31
valid_sources[0x2a]	7950	1			T1	10		T2	11		T3	24
valid_sources[0x2b]	7692	1			T1	18		T2	21		T3	9
valid_sources[0x2c]	7074	1			T1	7		T2	6		T3	4
valid_sources[0x2d]	7041	1			T1	7		T2	19		T3	22
valid_sources[0x2e]	8081	1			T1	15		T2	10		T3	18
valid_sources[0x2f]	9007	1			T1	10		T2	12		T3	8
valid_sources[0x30]	8718	1			T1	14		T2	8		T3	4
valid_sources[0x31]	6724	1			T1	13		T2	6		T3	20
valid_sources[0x32]	6996	1			T1	7		T2	37		T3	54
valid_sources[0x33]	6757	1			T1	11		T2	25		T3	4
valid_sources[0x34]	6794	1			T1	8		T2	11		T3	7
valid_sources[0x35]	7486	1			T1	7		T2	6		T3	22
valid_sources[0x36]	6945	1			T1	9		T2	2		T3	21
valid_sources[0x37]	6754	1			T1	6		T2	12		T3	5
valid_sources[0x38]	13186	1			T1	18		T2	4		T3	13
valid_sources[0x39]	7286	1			T1	5		T2	3		T3	17
valid_sources[0x3a]	6649	1			T1	8		T2	7		T3	8
valid_sources[0x3b]	6807	1			T1	6		T2	2		T3	12
valid_sources[0x3c]	6968	1			T1	10		T2	9		T3	36
valid_sources[0x3d]	11766	1			T1	5		T2	2		T3	6
valid_sources[0x3e]	6718	1			T1	9		T2	11		T3	8
valid_sources[0x3f]	8205	1			T1	18		T2	7		T3	8
valid_sources[0x40]	7357	1			T1	3		T2	19		T3	22
valid_sources[0x41]	11321	1			T1	9		T3	15		T4	133
valid_sources[0x42]	8395	1			T1	6		T2	14		T3	89
valid_sources[0x43]	9479	1			T1	17		T2	3		T3	8
valid_sources[0x44]	9301	1			T1	16		T2	11		T3	37
valid_sources[0x45]	7993	1			T1	10		T2	5		T3	46
valid_sources[0x46]	7216	1			T1	10		T2	6		T3	10
valid_sources[0x47]	7062	1			T1	23		T2	6		T3	8
valid_sources[0x48]	8031	1			T1	9		T2	7		T3	7
valid_sources[0x49]	14141	1			T1	5		T2	5		T3	38
valid_sources[0x4a]	15854	1			T1	12		T2	20		T3	12
valid_sources[0x4b]	16142	1			T1	11		T2	4		T3	7
valid_sources[0x4c]	6798	1			T1	11		T2	27		T3	19
valid_sources[0x4d]	15865	1			T1	13		T2	4		T3	14
valid_sources[0x4e]	7014	1			T1	6		T2	2		T3	54
valid_sources[0x4f]	7459	1			T1	8		T2	7		T3	10
valid_sources[0x50]	7301	1			T1	13		T2	6		T3	16
valid_sources[0x51]	7090	1			T1	8		T2	4		T3	70
valid_sources[0x52]	7668	1			T1	11		T2	14		T3	7
valid_sources[0x53]	6941	1			T1	11		T2	3		T3	8
valid_sources[0x54]	7130	1			T1	4		T2	7		T3	36
valid_sources[0x55]	7086	1			T1	18		T2	7		T3	30
valid_sources[0x56]	7858	1			T1	9		T2	26		T3	13
valid_sources[0x57]	14131	1			T1	10		T2	10		T3	26
valid_sources[0x58]	6955	1			T1	11		T2	7		T3	31
valid_sources[0x59]	6549	1			T1	17		T2	4		T3	11
valid_sources[0x5a]	7038	1			T1	7		T2	8		T3	11
valid_sources[0x5b]	15887	1			T1	10		T2	19		T3	79
valid_sources[0x5c]	8235	1			T1	20		T2	23		T3	62
valid_sources[0x5d]	9916	1			T1	7		T2	17		T3	27
valid_sources[0x5e]	7240	1			T1	5		T2	8		T3	12
valid_sources[0x5f]	9683	1			T1	16		T2	4		T3	30
valid_sources[0x60]	6970	1			T1	10		T2	18		T3	9
valid_sources[0x61]	7326	1			T1	10		T2	11		T3	13
valid_sources[0x62]	7122	1			T1	4		T2	9		T3	11
valid_sources[0x63]	10498	1			T1	9		T2	3		T3	32
valid_sources[0x64]	20231	1			T1	15		T2	8		T3	32
valid_sources[0x65]	7798	1			T1	17		T2	24		T3	9
valid_sources[0x66]	7107	1			T1	11		T2	13		T3	4
valid_sources[0x67]	6766	1			T1	12		T2	11		T3	12
valid_sources[0x68]	7779	1			T1	11		T2	15		T3	23
valid_sources[0x69]	9086	1			T1	8		T2	20		T3	9
valid_sources[0x6a]	8166	1			T1	9		T2	14		T3	17
valid_sources[0x6b]	6614	1			T1	6		T2	9		T3	41
valid_sources[0x6c]	7102	1			T1	7		T2	8		T3	22
valid_sources[0x6d]	11346	1			T1	11		T2	7		T3	19
valid_sources[0x6e]	6938	1			T1	6		T2	13		T3	17
valid_sources[0x6f]	9782	1			T1	6		T2	15		T3	9
valid_sources[0x70]	7896	1			T1	4		T2	9		T3	9
valid_sources[0x71]	7213	1			T1	11		T2	3		T3	50
valid_sources[0x72]	6824	1			T1	9		T2	20		T3	102
valid_sources[0x73]	7741	1			T1	12		T3	33		T4	2
valid_sources[0x74]	8899	1			T1	4		T2	20		T3	10
valid_sources[0x75]	8119	1			T1	10		T2	24		T3	9
valid_sources[0x76]	6847	1			T1	9		T2	4		T3	18
valid_sources[0x77]	6804	1			T1	11		T2	5		T3	32
valid_sources[0x78]	13354	1			T1	11		T2	7		T3	8
valid_sources[0x79]	8305	1			T1	11		T2	20		T3	28
valid_sources[0x7a]	6688	1			T1	8		T2	16		T3	20
valid_sources[0x7b]	19843	1			T1	4		T2	11		T3	9
valid_sources[0x7c]	6713	1			T1	10		T2	17		T3	13
valid_sources[0x7d]	8135	1			T1	6		T2	2		T3	27
valid_sources[0x7e]	9550	1			T1	21		T2	1		T3	14
valid_sources[0x7f]	6966	1			T1	17		T2	10		T3	10
valid_sources[0x80]	7210	1			T1	10		T2	13		T3	20

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

984713

1

T1

1143

T2

1251

T3

3779

values[0x0]

all_enables

biggest_size

77822

1

T1

47

T2

93

T3

163

values[0x1]

all_enables

biggest_size

57418

1

T1

41

T2

60

T3

98