Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.67	86.67	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	86.67	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.67	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	6	39	86.67

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	5	11	68.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	28825	1			T1	6		T2	26		T3	19
auto[PWRUP]	98	1			T35	3		T43	2		T12	2
auto[ONEST_0]	56	1			T35	6		T43	1		T193	2
auto[ONEST_021]	19	1			T43	1		T194	1		T195	1
auto[ONEST_1]	86	1			T35	4		T43	2		T50	1
auto[ONEST_DONE]	4	1			T196	1		T197	1		T198	1
auto[LP_0]	113	1			T35	1		T43	1		T50	1
auto[LP_021]	30	1			T35	2		T49	1		T149	1
auto[LP_1]	120	1			T35	1		T43	1		T50	1
auto[LP_EVAL]	67	1			T35	2		T37	1		T50	1
auto[LP_SLP]	468	1			T34	2		T35	5		T43	4
auto[LP_PWRUP]	23	1			T43	1		T49	1		T199	1
auto[NP_0]	119	1			T35	2		T43	2		T50	3
auto[NP_021]	30	1			T35	1		T193	1		T199	1
auto[NP_1]	153	1			T35	7		T37	1		T193	1
auto[NP_EVAL]	37	1			T35	1		T50	2		T52	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

4

1

T200

1

T201

1

T202

1

min

28327

1

T1

6

T2

26

T3

19

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28335	1			T1	6		T2	26		T3	19
pow[0x1]	9	1			T50	1		T79	1		T203	1
pow[0x2]	12	1			T35	1		T194	1		T201	1
pow[0x3]	27	1			T43	1		T50	1		T204	1
pow[0x4]	51	1			T35	1		T50	1		T12	1
pow[0x5]	132	1			T35	5		T50	1		T193	1
pow[0x6]	216	1			T35	2		T43	4		T193	4
pow[0x7]	487	1			T35	8		T43	5		T37	1

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

179

1

T35

1

T43

1

T50

2

min

27903

1

T1

6

T2

26

T3

19

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	5	11	68.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27903	1			T1	6		T2	26		T3	19
pow[0x6]	2	1			T204	1		T79	1		-	-
pow[0x7]	2	1			T193	1		T205	1		-	-
pow[0x8]	5	1			T201	1		T195	1		T197	1
pow[0x9]	13	1			T35	1		T200	1		T201	1
pow[0xa]	12	1			T37	1		T49	1		T204	1
pow[0xb]	29	1			T35	1		T43	1		T50	1
pow[0xc]	63	1			T43	1		T52	1		T12	1
pow[0xd]	148	1			T35	3		T43	1		T50	1
pow[0xe]	252	1			T34	1		T35	4		T43	2
pow[0xf]	536	1			T34	1		T35	11		T43	5