Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2198	1			T6	2		T34	15		T35	43
auto[PWRUP]	129	1			T35	3		T43	4		T193	1
auto[ONEST_0]	73	1			T35	2		T43	1		T37	1
auto[ONEST_021]	21	1			T35	2		T52	1		T136	1
auto[ONEST_1]	87	1			T34	1		T35	2		T43	1
auto[ONEST_DONE]	3	1			T239	1		T355	1		T356	1
auto[LP_0]	115	1			T34	1		T43	1		T193	1
auto[LP_021]	26	1			T49	2		T38	1		T357	1
auto[LP_1]	146	1			T35	6		T37	1		T50	2
auto[LP_EVAL]	63	1			T35	2		T43	1		T37	1
auto[LP_SLP]	461	1			T34	1		T35	12		T43	8
auto[LP_PWRUP]	40	1			T34	1		T35	1		T43	1
auto[NP_0]	208	1			T34	1		T35	9		T43	1
auto[NP_021]	50	1			T35	1		T37	1		T50	1
auto[NP_1]	251	1			T34	4		T35	9		T43	1
auto[NP_EVAL]	42	1			T37	1		T52	1		T14	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

10

1

T52

1

T201

1

T87

1

min

1959

1

T6

2

T34

21

T35

37

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1972	1			T6	2		T34	21		T35	37
pow[0x1]	16	1			T35	1		T199	1		T200	1
pow[0x2]	18	1			T12	1		T200	1		T206	2
pow[0x3]	29	1			T193	1		T204	2		T13	1
pow[0x4]	58	1			T35	2		T50	1		T193	1
pow[0x5]	117	1			T35	1		T43	1		T37	1
pow[0x6]	244	1			T34	2		T35	5		T50	2
pow[0x7]	501	1			T35	13		T43	5		T37	2

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

193

1

T35

7

T43

3

T50

2

min

1380

1

T6

2

T34

16

T35

28

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1389	1			T6	2		T34	16		T35	28
pow[0x1]	16	1			T156	2		T16	1		T19	3
pow[0x2]	22	1			T35	2		T12	1		T149	3
pow[0x3]	55	1			T36	2		T37	1		T12	3
pow[0x4]	73	1			T34	4		T35	4		T36	1
pow[0x6]	2	1			T149	1		T220	1		-	-
pow[0x7]	3	1			T34	1		T204	1		T245	1
pow[0x8]	3	1			T35	1		T37	1		T193	1
pow[0x9]	5	1			T35	1		T358	1		T359	1
pow[0xa]	16	1			T35	1		T194	1		T201	1
pow[0xb]	44	1			T43	2		T12	1		T49	1
pow[0xc]	61	1			T35	2		T50	1		T52	2
pow[0xd]	123	1			T35	3		T43	1		T193	1
pow[0xe]	285	1			T35	10		T43	4		T50	2
pow[0xf]	553	1			T35	17		T43	5		T37	3