Unified Coverage Report :: Module :: adc_ctrl_core

Module : adc_ctrl_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_adc_ctrl_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.83	100.00	99.76		100.00	99.37	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_ctrl_fsm	99.75	100.00	100.00		100.00	98.73	100.00
u_adc_ctrl_intr	99.00	100.00	96.00			100.00	100.00
u_oneshot_done_sync	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
TOTAL		63	63	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	73	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	213	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	8	8
63	8	8
72	1	1
73	1	1
74	1	1
75	1	1
83	1	1
86	1	1
87	1	1
88	1	1
89	1	1
104	8	8
107	8	8
117	8	8
121	8	8
137	1	1
138	1	1
140	1	1
141	1	1
145	1	1
213	1	1

---

Cond Coverage for Module : adc_ctrl_core

	Total	Covered	Percent
Conditions	293	293	100.00
Logical	293	293	100.00
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION (reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done : (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0))
             -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       83
 SUB-EXPRESSION (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0)
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][0].cond)) ? ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v)) : ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v)))

-1-	Status	Tests
0	Covered	T6,T10,T11
1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T10,T11
0	1	Covered	T6,T10,T11
1	0	Covered	T6,T10,T11

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][1].cond)) ? ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v)) : ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v)))

-1-	Status	Tests
0	Covered	T3,T6,T7
1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T7
0	1	Covered	T3,T6,T7
1	0	Covered	T3,T6,T7

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][2].cond)) ? ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v)) : ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v)))

-1-	Status	Tests
0	Covered	T3,T11,T12
1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T11,T12
0	1	Covered	T3,T11,T13
1	0	Covered	T3,T11,T12

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][3].cond)) ? ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v)) : ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v)))

-1-	Status	Tests
0	Covered	T3,T7,T10
1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T10
0	1	Covered	T3,T7,T10
1	0	Covered	T3,T7,T10

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][4].cond)) ? ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v)) : ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v)))

-1-	Status	Tests
0	Covered	T3,T10,T11
1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T11
0	1	Covered	T3,T10,T11
1	0	Covered	T3,T10,T11

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][5].cond)) ? ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v)) : ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v)))

-1-	Status	Tests
0	Covered	T3,T6,T7
1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T7
0	1	Covered	T3,T6,T7
1	0	Covered	T3,T6,T7

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][6].cond)) ? ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v)) : ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v)))

-1-	Status	Tests
0	Covered	T3,T6,T7
1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T7
0	1	Covered	T3,T6,T7
1	0	Covered	T3,T6,T7

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][7].cond)) ? ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v)) : ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v)))

-1-	Status	Tests
0	Covered	T3,T6,T7
1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T7
0	1	Covered	T3,T6,T7
1	0	Covered	T3,T6,T7

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][0].cond)) ? ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v)) : ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v)))

-1-	Status	Tests
0	Covered	T3,T6,T10
1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T10
0	1	Covered	T3,T6,T10
1	0	Covered	T3,T6,T10

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][1].cond)) ? ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v)) : ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v)))

-1-	Status	Tests
0	Covered	T3,T6,T10
1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T10
0	1	Covered	T3,T6,T10
1	0	Covered	T3,T6,T10

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][2].cond)) ? ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v)) : ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v)))

-1-	Status	Tests
0	Covered	T3,T6,T11
1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T11
0	1	Covered	T3,T6,T11
1	0	Covered	T3,T6,T11

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][3].cond)) ? ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v)) : ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v)))

-1-	Status	Tests
0	Covered	T3,T7,T10
1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T10
0	1	Covered	T3,T7,T10
1	0	Covered	T3,T7,T10

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][4].cond)) ? ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v)) : ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v)))

-1-	Status	Tests
0	Covered	T3,T10,T11
1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T11
0	1	Covered	T3,T10,T11
1	0	Covered	T3,T10,T11

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][5].cond)) ? ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v)) : ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v)))

-1-	Status	Tests
0	Covered	T3,T6,T7
1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T7
0	1	Covered	T3,T6,T7
1	0	Covered	T3,T6,T7

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][6].cond)) ? ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v)) : ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v)))

-1-	Status	Tests
0	Covered	T3,T6,T7
1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T7
0	1	Covered	T3,T6,T7
1	0	Covered	T3,T6,T7

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][7].cond)) ? ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v)) : ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v)))

-1-	Status	Tests
0	Covered	T3,T6,T7
1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T7
0	1	Covered	T3,T6,T7
1	0	Covered	T3,T6,T7

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][0].en, aon_filter_ctl[1][0].en})) & 
      2  (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en)) & 
      3  (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T3,T7,T8
1	1	0	Covered	T3,T7,T8
1	1	1	Covered	T1,T3,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T8
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn0_match[0] & aon_filter_ctl[0][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T3,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T8
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn1_match[0] & aon_filter_ctl[1][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T3,T7

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][1].en, aon_filter_ctl[1][1].en})) & 
      2  (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en)) & 
      3  (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T3,T6,T7
1	1	0	Covered	T6,T7,T8
1	1	1	Covered	T3,T6,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T7
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn0_match[1] & aon_filter_ctl[0][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T2,T4
1	1	Covered	T3,T6,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T7
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn1_match[1] & aon_filter_ctl[1][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T2,T4
1	1	Covered	T3,T6,T7

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][2].en, aon_filter_ctl[1][2].en})) & 
      2  (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en)) & 
      3  (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T3,T8,T10
1	1	0	Covered	T3,T7,T8
1	1	1	Covered	T3,T7,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T8
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn0_match[2] & aon_filter_ctl[0][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T4
1	1	Covered	T3,T7,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T8
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn1_match[2] & aon_filter_ctl[1][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T4
1	1	Covered	T3,T7,T8

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][3].en, aon_filter_ctl[1][3].en})) & 
      2  (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en)) & 
      3  (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T3,T6,T8
1	1	0	Covered	T3,T6,T8
1	1	1	Covered	T3,T6,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T8
0	1	Covered	T3,T6,T8
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn0_match[3] & aon_filter_ctl[0][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T8
1	0	Covered	T1,T2,T4
1	1	Covered	T3,T6,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T8
0	1	Covered	T3,T6,T8
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn1_match[3] & aon_filter_ctl[1][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T8
1	0	Covered	T1,T2,T4
1	1	Covered	T3,T6,T8

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][4].en, aon_filter_ctl[1][4].en})) & 
      2  (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en)) & 
      3  (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T3,T6,T7
1	1	0	Covered	T3,T6,T7
1	1	1	Covered	T3,T6,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T7
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn0_match[4] & aon_filter_ctl[0][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T2,T4
1	1	Covered	T3,T6,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T7
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn1_match[4] & aon_filter_ctl[1][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T2,T4
1	1	Covered	T3,T6,T7

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][5].en, aon_filter_ctl[1][5].en})) & 
      2  (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en)) & 
      3  (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T7,T8,T13
1	1	0	Covered	T7,T8,T13
1	1	1	Covered	T7,T8,T13

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T13
0	1	Covered	T7,T8,T13
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn0_match[5] & aon_filter_ctl[0][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T13
1	0	Covered	T1,T2,T4
1	1	Covered	T7,T8,T13

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T13
0	1	Covered	T7,T8,T13
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn1_match[5] & aon_filter_ctl[1][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T13
1	0	Covered	T1,T2,T4
1	1	Covered	T7,T8,T13

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][6].en, aon_filter_ctl[1][6].en})) & 
      2  (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en)) & 
      3  (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T7,T8,T11
1	1	0	Covered	T7,T8,T11
1	1	1	Covered	T7,T8,T11

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T11
0	1	Covered	T7,T8,T11
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn0_match[6] & aon_filter_ctl[0][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T11
1	0	Covered	T1,T2,T4
1	1	Covered	T7,T8,T11

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T11
0	1	Covered	T7,T8,T11
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn1_match[6] & aon_filter_ctl[1][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T11
1	0	Covered	T1,T2,T4
1	1	Covered	T7,T8,T11

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][7].en, aon_filter_ctl[1][7].en})) & 
      2  (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en)) & 
      3  (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T3,T7,T8
1	1	0	Covered	T3,T8,T10
1	1	1	Covered	T3,T7,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T8
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn0_match[7] & aon_filter_ctl[0][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T4
1	1	Covered	T3,T7,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T8
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn1_match[7] & aon_filter_ctl[1][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T4
1	1	Covered	T3,T7,T8

 LINE       121
 EXPRESSION (adc_ctrl_done && match[0])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T3,T6,T7
1	1	Covered	T3,T7,T8

 LINE       121
 EXPRESSION (adc_ctrl_done && match[1])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T3,T7,T8
1	1	Covered	T3,T6,T7

 LINE       121
 EXPRESSION (adc_ctrl_done && match[2])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T3,T6,T7
1	1	Covered	T3,T7,T8

 LINE       121
 EXPRESSION (adc_ctrl_done && match[3])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T8
1	0	Covered	T3,T6,T7
1	1	Covered	T3,T6,T8

 LINE       121
 EXPRESSION (adc_ctrl_done && match[4])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T3,T6,T7
1	1	Covered	T3,T6,T8

 LINE       121
 EXPRESSION (adc_ctrl_done && match[5])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T13
1	0	Covered	T3,T6,T7
1	1	Covered	T7,T8,T13

 LINE       121
 EXPRESSION (adc_ctrl_done && match[6])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T11
1	0	Covered	T3,T6,T7
1	1	Covered	T7,T8,T11

 LINE       121
 EXPRESSION (adc_ctrl_done && match[7])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T3,T6,T7
1	1	Covered	T3,T7,T8

 LINE       140
 EXPRESSION (aon_fsm_trans | reg2hw_i.filter_status.trans.q)
             ------1------   ---------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T7,T8

 LINE       145
 EXPRESSION (((|(reg2hw_i.filter_status.match.q & reg2hw_i.adc_wakeup_ctl.match_en.q))) || (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q))
             -------------------------------------1------------------------------------    ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T7,T8,T11
1	0	Covered	T3,T6,T7

 LINE       145
 SUB-EXPRESSION (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q)
                 ---------------1--------------   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T6,T7,T8
1	1	Covered	T7,T8,T11

---

Branch Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	83	3	3	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	83	(reg2hw_i.adc_en_ctl.oneshot_mode.q) ? 
-2-:	83	(reg2hw_i.adc_en_ctl.adc_enable.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T6,T10,T11

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T3,T6,T10

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T3,T6,T7

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T3,T6,T10

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T3,T11,T12

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T3,T6,T11

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T3,T7,T10

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T3,T7,T10

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T3,T10,T11

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T3,T10,T11

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T3,T6,T7

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T3,T6,T7

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T3,T6,T7

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T3,T6,T7

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T3,T6,T7

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T3,T6,T7

---

Assert Coverage for Module : adc_ctrl_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	33	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	33	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxFilters_A	34492970	34167409	0	0
gen_filter_match[0].MatchCheck00_A	34492970	10561114	0	0
gen_filter_match[0].MatchCheck01_A	34492970	2661711	0	0
gen_filter_match[0].MatchCheck10_A	34492970	2758158	0	0
gen_filter_match[0].MatchCheck11_A	34492970	18186426	0	0
gen_filter_match[1].MatchCheck00_A	34492970	11535813	0	0
gen_filter_match[1].MatchCheck01_A	34492970	1180784	0	0
gen_filter_match[1].MatchCheck10_A	34492970	1580741	0	0
gen_filter_match[1].MatchCheck11_A	34492970	19870071	0	0
gen_filter_match[2].MatchCheck00_A	34492970	13137229	0	0
gen_filter_match[2].MatchCheck01_A	34492970	633930	0	0
gen_filter_match[2].MatchCheck10_A	34492970	378601	0	0
gen_filter_match[2].MatchCheck11_A	34492970	20017649	0	0
gen_filter_match[3].MatchCheck00_A	34492970	12503329	0	0
gen_filter_match[3].MatchCheck01_A	34492970	533129	0	0
gen_filter_match[3].MatchCheck10_A	34492970	313337	0	0
gen_filter_match[3].MatchCheck11_A	34492970	20817614	0	0
gen_filter_match[4].MatchCheck00_A	34492970	12814440	0	0
gen_filter_match[4].MatchCheck01_A	34492970	77832	0	0
gen_filter_match[4].MatchCheck10_A	34492970	67689	0	0
gen_filter_match[4].MatchCheck11_A	34492970	21207448	0	0
gen_filter_match[5].MatchCheck00_A	34492970	12660991	0	0
gen_filter_match[5].MatchCheck01_A	34492970	38960	0	0
gen_filter_match[5].MatchCheck10_A	34492970	33050	0	0
gen_filter_match[5].MatchCheck11_A	34492970	21434408	0	0
gen_filter_match[6].MatchCheck00_A	34492970	12564875	0	0
gen_filter_match[6].MatchCheck01_A	34492970	131943	0	0
gen_filter_match[6].MatchCheck10_A	34492970	70133	0	0
gen_filter_match[6].MatchCheck11_A	34492970	21400458	0	0
gen_filter_match[7].MatchCheck00_A	34492970	13050261	0	0
gen_filter_match[7].MatchCheck01_A	34492970	241881	0	0
gen_filter_match[7].MatchCheck10_A	34492970	36841	0	0
gen_filter_match[7].MatchCheck11_A	34492970	20838426	0	0

MaxFilters_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34492970	34167409	0	0
T1	20403	17880	0	0
T2	699	607	0	0
T3	74965	74575	0	0
T4	86	6	0	0
T5	7711	7614	0	0
T6	36751	36669	0	0
T7	103885	103797	0	0
T8	126728	126650	0	0
T9	24447	21773	0	0
T10	64732	64640	0	0

gen_filter_match[0].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34492970	10561114	0	0
T1	20403	17669	0	0
T2	699	607	0	0
T3	74965	9513	0	0
T4	86	6	0	0
T5	7711	7614	0	0
T6	36751	36669	0	0
T7	103885	32187	0	0
T8	126728	3	0	0
T9	24447	20677	0	0
T10	64732	32392	0	0

gen_filter_match[0].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34492970	2661711	0	0
T3	74965	32190	0	0
T5	7711	0	0	0
T6	36751	0	0	0
T7	103885	0	0	0
T8	126728	0	0	0
T9	24447	0	0	0
T10	64732	32248	0	0
T11	96308	0	0	0
T12	32258	0	0	0
T13	0	41032	0	0
T15	14841	0	0	0
T17	0	46540	0	0
T26	0	39186	0	0
T41	0	64104	0	0
T44	0	65955	0	0
T136	0	31824	0	0
T137	0	32575	0	0
T138	0	31328	0	0

gen_filter_match[0].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34492970	2758158	0	0
T3	74965	32872	0	0
T5	7711	0	0	0
T6	36751	0	0	0
T7	103885	0	0	0
T8	126728	0	0	0
T9	24447	0	0	0
T10	64732	0	0	0
T11	96308	0	0	0
T12	32258	0	0	0
T15	14841	0	0	0
T51	0	32548	0	0
T52	0	69256	0	0
T81	0	1	0	0
T83	0	36356	0	0
T139	0	31558	0	0
T140	0	32878	0	0
T141	0	43151	0	0
T142	0	32386	0	0
T143	0	35761	0	0

gen_filter_match[0].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34492970	18186426	0	0
T1	20403	211	0	0
T2	699	0	0	0
T3	74965	0	0	0
T4	86	0	0	0
T5	7711	0	0	0
T6	36751	0	0	0
T7	103885	71610	0	0
T8	126728	126647	0	0
T9	24447	1096	0	0
T10	64732	0	0	0
T11	0	73729	0	0
T13	0	32584	0	0
T14	0	33136	0	0
T15	0	758	0	0
T47	0	74351	0	0
T49	0	65654	0	0

gen_filter_match[1].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34492970	11535813	0	0
T1	20403	17880	0	0
T2	699	607	0	0
T3	74965	42385	0	0
T4	86	6	0	0
T5	7711	7614	0	0
T6	36751	4	0	0
T7	103885	37987	0	0
T8	126728	3	0	0
T9	24447	21773	0	0
T10	64732	32392	0	0

gen_filter_match[1].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34492970	1180784	0	0
T7	103885	33626	0	0
T8	126728	0	0	0
T9	24447	0	0	0
T10	64732	0	0	0
T11	96308	0	0	0
T12	32258	0	0	0
T13	107568	33864	0	0
T14	70342	0	0	0
T15	14841	0	0	0
T17	0	31556	0	0
T41	0	32523	0	0
T47	96737	0	0	0
T106	0	35508	0	0
T144	0	32307	0	0
T145	0	32421	0	0
T146	0	31949	0	0
T147	0	33020	0	0
T148	0	33012	0	0

gen_filter_match[1].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34492970	1580741	0	0
T7	103885	32184	0	0
T8	126728	0	0	0
T9	24447	0	0	0
T10	64732	0	0	0
T11	96308	0	0	0
T12	32258	32202	0	0
T13	107568	0	0	0
T14	70342	33136	0	0
T15	14841	0	0	0
T17	0	3	0	0
T32	0	12759	0	0
T37	0	32392	0	0
T47	96737	0	0	0
T81	0	32037	0	0
T137	0	32881	0	0
T139	0	37920	0	0
T149	0	33291	0	0

gen_filter_match[1].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34492970	19870071	0	0
T3	74965	32190	0	0
T5	7711	0	0	0
T6	36751	36665	0	0
T7	103885	0	0	0
T8	126728	126647	0	0
T9	24447	0	0	0
T10	64732	32248	0	0
T11	96308	0	0	0
T12	32258	0	0	0
T13	0	32584	0	0
T14	0	37104	0	0
T15	14841	0	0	0
T47	0	73859	0	0
T49	0	65654	0	0
T51	0	65214	0	0
T53	0	34050	0	0

gen_filter_match[2].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34492970	13137229	0	0
T1	20403	17880	0	0
T2	699	607	0	0
T3	74965	42385	0	0
T4	86	6	0	0
T5	7711	7614	0	0
T6	36751	36669	0	0
T7	103885	70171	0	0
T8	126728	3	0	0
T9	24447	21773	0	0
T10	64732	4	0	0

gen_filter_match[2].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34492970	633930	0	0
T32	0	13252	0	0
T81	0	32813	0	0
T134	1195	0	0	0
T135	1157	0	0	0
T137	98511	1	0	0
T141	79626	0	0	0
T144	97703	0	0	0
T150	40296	40238	0	0
T151	0	32277	0	0
T152	0	59948	0	0
T153	0	33922	0	0
T154	0	2	0	0
T155	0	37341	0	0
T156	0	1	0	0
T157	5193	0	0	0
T158	119809	0	0	0
T159	99384	0	0	0
T160	893	0	0	0

gen_filter_match[2].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34492970	378601	0	0
T13	107568	1	0	0
T14	70342	0	0	0
T17	0	7	0	0
T21	0	3	0	0
T37	0	2	0	0
T47	96737	73859	0	0
T49	65721	0	0	0
T50	104	0	0	0
T51	65318	0	0	0
T52	101803	0	0	0
T53	106293	0	0	0
T54	64437	0	0	0
T55	17325	0	0	0
T85	0	32247	0	0
T149	0	32665	0	0
T154	0	3	0	0
T161	0	1	0	0
T162	0	33693	0	0

gen_filter_match[2].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34492970	20017649	0	0
T3	74965	32190	0	0
T5	7711	0	0	0
T6	36751	0	0	0
T7	103885	33626	0	0
T8	126728	126647	0	0
T9	24447	0	0	0
T10	64732	64636	0	0
T11	96308	73291	0	0
T12	32258	32202	0	0
T13	0	107480	0	0
T15	14841	0	0	0
T47	0	287	0	0
T49	0	65654	0	0
T51	0	32666	0	0

gen_filter_match[3].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34492970	12503329	0	0
T1	20403	17880	0	0
T2	699	607	0	0
T3	74965	9513	0	0
T4	86	6	0	0
T5	7711	7614	0	0
T6	36751	4	0	0
T7	103885	103797	0	0
T8	126728	3	0	0
T9	24447	21773	0	0
T10	64732	32252	0	0

gen_filter_match[3].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34492970	533129	0	0
T13	107568	1	0	0
T14	70342	0	0	0
T40	0	39892	0	0
T47	96737	0	0	0
T49	65721	0	0	0
T50	104	0	0	0
T51	65318	0	0	0
T52	101803	0	0	0
T53	106293	0	0	0
T54	64437	0	0	0
T55	17325	0	0	0
T88	0	12782	0	0
T137	0	1	0	0
T163	0	35861	0	0
T164	0	34319	0	0
T165	0	1	0	0
T166	0	32213	0	0
T167	0	35414	0	0
T168	0	31881	0	0

gen_filter_match[3].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34492970	313337	0	0
T11	96308	38149	0	0
T12	32258	0	0	0
T13	107568	1	0	0
T14	70342	0	0	0
T15	14841	0	0	0
T17	0	8	0	0
T21	0	1	0	0
T36	0	2	0	0
T37	0	3	0	0
T46	0	3	0	0
T47	96737	0	0	0
T49	65721	0	0	0
T50	104	0	0	0
T51	65318	0	0	0
T52	101803	0	0	0
T81	0	1	0	0
T137	0	1	0	0
T161	0	1	0	0

gen_filter_match[3].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34492970	20817614	0	0
T3	74965	65062	0	0
T5	7711	0	0	0
T6	36751	36665	0	0
T7	103885	0	0	0
T8	126728	126647	0	0
T9	24447	0	0	0
T10	64732	32388	0	0
T11	96308	35142	0	0
T12	32258	32202	0	0
T13	0	33864	0	0
T14	0	70240	0	0
T15	14841	0	0	0
T47	0	74146	0	0
T49	0	65654	0	0

gen_filter_match[4].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34492970	12814440	0	0
T1	20403	17880	0	0
T2	699	607	0	0
T3	74965	9513	0	0
T4	86	6	0	0
T5	7711	7614	0	0
T6	36751	4	0	0
T7	103885	65813	0	0
T8	126728	3	0	0
T9	24447	21773	0	0
T10	64732	32252	0	0

gen_filter_match[4].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34492970	77832	0	0
T14	70342	1	0	0
T47	96737	0	0	0
T49	65721	0	0	0
T50	104	0	0	0
T51	65318	0	0	0
T52	101803	0	0	0
T53	106293	0	0	0
T54	64437	0	0	0
T55	17325	0	0	0
T57	86	0	0	0
T156	0	1	0	0
T165	0	2	0	0
T169	0	1	0	0
T170	0	2	0	0
T171	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0
T174	0	2	0	0
T175	0	45139	0	0

gen_filter_match[4].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34492970	67689	0	0
T16	13392	2734	0	0
T17	147462	7	0	0
T26	83359	0	0	0
T27	32637	0	0	0
T28	1144	0	0	0
T29	1140	0	0	0
T30	4352	0	0	0
T31	89	0	0	0
T32	43213	0	0	0
T33	34352	0	0	0
T36	0	9	0	0
T37	0	1	0	0
T46	0	2	0	0
T154	0	1	0	0
T161	0	1	0	0
T165	0	2	0	0
T176	0	1	0	0
T177	0	1	0	0

gen_filter_match[4].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34492970	21207448	0	0
T3	74965	65062	0	0
T5	7711	0	0	0
T6	36751	36665	0	0
T7	103885	37984	0	0
T8	126728	126647	0	0
T9	24447	0	0	0
T10	64732	32388	0	0
T11	96308	35142	0	0
T12	32258	32202	0	0
T14	0	37104	0	0
T15	14841	0	0	0
T49	0	65654	0	0
T51	0	32666	0	0

gen_filter_match[5].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34492970	12660991	0	0
T1	20403	17880	0	0
T2	699	607	0	0
T3	74965	74575	0	0
T4	86	6	0	0
T5	7711	7614	0	0
T6	36751	36669	0	0
T7	103885	37987	0	0
T8	126728	3	0	0
T9	24447	21773	0	0
T10	64732	64640	0	0

gen_filter_match[5].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34492970	38960	0	0
T81	98960	1	0	0
T82	120079	0	0	0
T83	108916	0	0	0
T84	87	0	0	0
T85	98743	0	0	0
T86	96870	0	0	0
T87	32034	0	0	0
T173	0	1	0	0
T174	0	2	0	0
T178	0	2	0	0
T179	0	1	0	0
T180	0	38952	0	0
T181	0	1	0	0
T182	96589	0	0	0
T183	1170	0	0	0
T184	37308	0	0	0

gen_filter_match[5].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34492970	33050	0	0
T13	107568	1	0	0
T14	70342	1	0	0
T17	0	2	0	0
T19	0	1	0	0
T36	0	11	0	0
T46	0	32952	0	0
T47	96737	0	0	0
T49	65721	0	0	0
T50	104	0	0	0
T51	65318	0	0	0
T52	101803	0	0	0
T53	106293	0	0	0
T54	64437	0	0	0
T55	17325	0	0	0
T81	0	1	0	0
T137	0	1	0	0
T161	0	1	0	0
T185	0	1	0	0

gen_filter_match[5].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34492970	21434408	0	0
T7	103885	65810	0	0
T8	126728	126647	0	0
T9	24447	0	0	0
T10	64732	0	0	0
T11	96308	0	0	0
T12	32258	0	0	0
T13	107568	73615	0	0
T14	70342	33135	0	0
T15	14841	0	0	0
T47	96737	73859	0	0
T49	0	65654	0	0
T51	0	32548	0	0
T52	0	33231	0	0
T53	0	32383	0	0
T54	0	64334	0	0

gen_filter_match[6].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34492970	12564875	0	0
T1	20403	17880	0	0
T2	699	607	0	0
T3	74965	74575	0	0
T4	86	6	0	0
T5	7711	7614	0	0
T6	36751	36669	0	0
T7	103885	37987	0	0
T8	126728	3	0	0
T9	24447	21773	0	0
T10	64732	64640	0	0

gen_filter_match[6].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34492970	131943	0	0
T13	107568	1	0	0
T14	70342	0	0	0
T47	96737	0	0	0
T49	65721	0	0	0
T50	104	0	0	0
T51	65318	0	0	0
T52	101803	0	0	0
T53	106293	0	0	0
T54	64437	0	0	0
T55	17325	0	0	0
T81	0	1	0	0
T155	0	32616	0	0
T165	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0
T186	0	31443	0	0
T187	0	31156	0	0
T188	0	1	0	0
T189	0	1	0	0

gen_filter_match[6].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34492970	70133	0	0
T13	107568	1	0	0
T14	70342	0	0	0
T17	0	2	0	0
T36	0	3	0	0
T37	0	1	0	0
T47	96737	0	0	0
T49	65721	0	0	0
T50	104	0	0	0
T51	65318	0	0	0
T52	101803	0	0	0
T53	106293	0	0	0
T54	64437	0	0	0
T55	17325	0	0	0
T81	0	2	0	0
T137	0	1	0	0
T161	0	1	0	0
T184	0	37219	0	0
T185	0	1	0	0
T190	0	1	0	0

gen_filter_match[6].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34492970	21400458	0	0
T7	103885	65810	0	0
T8	126728	126647	0	0
T9	24447	0	0	0
T10	64732	0	0	0
T11	96308	38149	0	0
T12	32258	32202	0	0
T13	107568	33864	0	0
T14	70342	0	0	0
T15	14841	0	0	0
T47	96737	74146	0	0
T49	0	65654	0	0
T51	0	32666	0	0
T52	0	65715	0	0
T53	0	66433	0	0

gen_filter_match[7].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34492970	13050261	0	0
T1	20403	17880	0	0
T2	699	607	0	0
T3	74965	41703	0	0
T4	86	6	0	0
T5	7711	7614	0	0
T6	36751	36669	0	0
T7	103885	65813	0	0
T8	126728	3	0	0
T9	24447	21773	0	0
T10	64732	4	0	0

gen_filter_match[7].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34492970	241881	0	0
T13	107568	1	0	0
T14	70342	0	0	0
T47	96737	0	0	0
T49	65721	0	0	0
T50	104	0	0	0
T51	65318	0	0	0
T52	101803	0	0	0
T53	106293	0	0	0
T54	64437	0	0	0
T55	17325	0	0	0
T81	0	1	0	0
T83	0	1	0	0
T86	0	32683	0	0
T137	0	1	0	0
T156	0	1	0	0
T171	0	1	0	0
T172	0	1	0	0
T191	0	35863	0	0
T192	0	1	0	0

gen_filter_match[7].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34492970	36841	0	0
T13	107568	1	0	0
T14	70342	1	0	0
T17	0	7	0	0
T36	0	12	0	0
T37	0	4	0	0
T47	96737	0	0	0
T49	65721	0	0	0
T50	104	0	0	0
T51	65318	0	0	0
T52	101803	0	0	0
T53	106293	0	0	0
T54	64437	0	0	0
T55	17325	0	0	0
T81	0	1	0	0
T83	0	1	0	0
T137	0	2	0	0
T161	0	1	0	0
T193	0	1	0	0

gen_filter_match[7].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34492970	20838426	0	0
T3	74965	32872	0	0
T5	7711	0	0	0
T6	36751	0	0	0
T7	103885	37984	0	0
T8	126728	126647	0	0
T9	24447	0	0	0
T10	64732	64636	0	0
T11	96308	0	0	0
T12	32258	0	0	0
T13	0	74896	0	0
T14	0	33135	0	0
T15	14841	0	0	0
T47	0	287	0	0
T49	0	65654	0	0
T51	0	65214	0	0
T52	0	69256	0	0