Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2398	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2363	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2434	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2413	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2344	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2426	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2284	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2430	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2275	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2435	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2384	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2373	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2277	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2328	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2281	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2291	0	0
adc_en_ctl_rd_A	2147483647	2096	0	0
adc_fsm_rst_rd_A	2147483647	1892	0	0
adc_intr_ctl_rd_A	2147483647	2462	0	0
adc_lp_sample_ctl_rd_A	2147483647	1894	0	0
adc_pd_ctl_rd_A	2147483647	2340	0	0
adc_sample_ctl_rd_A	2147483647	1826	0	0
adc_wakeup_ctl_rd_A	2147483647	2204	0	0
intr_enable_rd_A	2147483647	2560	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2398	0	0
T14	107379	35	0	0
T15	320641	0	0	0
T16	0	17	0	0
T17	0	15	0	0
T18	0	13	0	0
T19	0	12	0	0
T20	0	23	0	0
T21	0	6	0	0
T22	0	45	0	0
T23	0	17	0	0
T24	0	37	0	0
T25	279174	0	0	0
T26	782251	0	0	0
T27	21152	0	0	0
T28	323736	0	0	0
T29	599617	0	0	0
T30	768923	0	0	0
T31	10607	0	0	0
T32	883299	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2363	0	0
T14	107379	38	0	0
T15	320641	0	0	0
T16	0	24	0	0
T17	0	11	0	0
T18	0	16	0	0
T19	0	19	0	0
T20	0	8	0	0
T21	0	16	0	0
T22	0	45	0	0
T23	0	13	0	0
T24	0	23	0	0
T25	279174	0	0	0
T26	782251	0	0	0
T27	21152	0	0	0
T28	323736	0	0	0
T29	599617	0	0	0
T30	768923	0	0	0
T31	10607	0	0	0
T32	883299	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2434	0	0
T14	107379	33	0	0
T15	320641	0	0	0
T16	0	9	0	0
T17	0	24	0	0
T18	0	23	0	0
T19	0	25	0	0
T20	0	13	0	0
T21	0	22	0	0
T22	0	30	0	0
T23	0	20	0	0
T24	0	20	0	0
T25	279174	0	0	0
T26	782251	0	0	0
T27	21152	0	0	0
T28	323736	0	0	0
T29	599617	0	0	0
T30	768923	0	0	0
T31	10607	0	0	0
T32	883299	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2413	0	0
T14	107379	36	0	0
T15	320641	0	0	0
T16	0	11	0	0
T17	0	20	0	0
T18	0	19	0	0
T19	0	17	0	0
T20	0	20	0	0
T21	0	9	0	0
T22	0	42	0	0
T23	0	22	0	0
T24	0	22	0	0
T25	279174	0	0	0
T26	782251	0	0	0
T27	21152	0	0	0
T28	323736	0	0	0
T29	599617	0	0	0
T30	768923	0	0	0
T31	10607	0	0	0
T32	883299	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2344	0	0
T14	107379	37	0	0
T15	320641	0	0	0
T16	0	42	0	0
T17	0	19	0	0
T18	0	15	0	0
T19	0	6	0	0
T20	0	13	0	0
T21	0	28	0	0
T22	0	33	0	0
T23	0	15	0	0
T24	0	29	0	0
T25	279174	0	0	0
T26	782251	0	0	0
T27	21152	0	0	0
T28	323736	0	0	0
T29	599617	0	0	0
T30	768923	0	0	0
T31	10607	0	0	0
T32	883299	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2426	0	0
T14	107379	28	0	0
T15	320641	0	0	0
T16	0	19	0	0
T17	0	2	0	0
T18	0	20	0	0
T19	0	21	0	0
T20	0	13	0	0
T21	0	15	0	0
T22	0	32	0	0
T23	0	34	0	0
T24	0	18	0	0
T25	279174	0	0	0
T26	782251	0	0	0
T27	21152	0	0	0
T28	323736	0	0	0
T29	599617	0	0	0
T30	768923	0	0	0
T31	10607	0	0	0
T32	883299	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2284	0	0
T14	107379	42	0	0
T15	320641	0	0	0
T16	0	29	0	0
T17	0	27	0	0
T18	0	24	0	0
T19	0	20	0	0
T20	0	20	0	0
T21	0	14	0	0
T22	0	26	0	0
T23	0	30	0	0
T24	0	25	0	0
T25	279174	0	0	0
T26	782251	0	0	0
T27	21152	0	0	0
T28	323736	0	0	0
T29	599617	0	0	0
T30	768923	0	0	0
T31	10607	0	0	0
T32	883299	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2430	0	0
T14	107379	29	0	0
T15	320641	0	0	0
T16	0	20	0	0
T17	0	16	0	0
T18	0	22	0	0
T19	0	23	0	0
T20	0	20	0	0
T21	0	12	0	0
T22	0	35	0	0
T23	0	13	0	0
T24	0	26	0	0
T25	279174	0	0	0
T26	782251	0	0	0
T27	21152	0	0	0
T28	323736	0	0	0
T29	599617	0	0	0
T30	768923	0	0	0
T31	10607	0	0	0
T32	883299	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2275	0	0
T14	107379	30	0	0
T15	320641	0	0	0
T16	0	43	0	0
T17	0	14	0	0
T18	0	12	0	0
T19	0	15	0	0
T20	0	14	0	0
T21	0	6	0	0
T22	0	25	0	0
T23	0	20	0	0
T24	0	21	0	0
T25	279174	0	0	0
T26	782251	0	0	0
T27	21152	0	0	0
T28	323736	0	0	0
T29	599617	0	0	0
T30	768923	0	0	0
T31	10607	0	0	0
T32	883299	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2435	0	0
T14	107379	42	0	0
T15	320641	0	0	0
T16	0	22	0	0
T17	0	14	0	0
T18	0	5	0	0
T19	0	24	0	0
T20	0	17	0	0
T21	0	19	0	0
T22	0	43	0	0
T23	0	32	0	0
T24	0	15	0	0
T25	279174	0	0	0
T26	782251	0	0	0
T27	21152	0	0	0
T28	323736	0	0	0
T29	599617	0	0	0
T30	768923	0	0	0
T31	10607	0	0	0
T32	883299	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2384	0	0
T14	107379	42	0	0
T15	320641	0	0	0
T16	0	14	0	0
T17	0	18	0	0
T18	0	17	0	0
T19	0	33	0	0
T20	0	27	0	0
T21	0	17	0	0
T22	0	31	0	0
T23	0	14	0	0
T24	0	18	0	0
T25	279174	0	0	0
T26	782251	0	0	0
T27	21152	0	0	0
T28	323736	0	0	0
T29	599617	0	0	0
T30	768923	0	0	0
T31	10607	0	0	0
T32	883299	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2373	0	0
T14	107379	31	0	0
T15	320641	0	0	0
T16	0	26	0	0
T17	0	11	0	0
T18	0	8	0	0
T19	0	25	0	0
T20	0	20	0	0
T21	0	22	0	0
T22	0	41	0	0
T23	0	22	0	0
T24	0	30	0	0
T25	279174	0	0	0
T26	782251	0	0	0
T27	21152	0	0	0
T28	323736	0	0	0
T29	599617	0	0	0
T30	768923	0	0	0
T31	10607	0	0	0
T32	883299	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2277	0	0
T14	107379	27	0	0
T15	320641	0	0	0
T16	0	18	0	0
T17	0	16	0	0
T18	0	13	0	0
T19	0	7	0	0
T20	0	21	0	0
T21	0	8	0	0
T22	0	34	0	0
T23	0	36	0	0
T24	0	24	0	0
T25	279174	0	0	0
T26	782251	0	0	0
T27	21152	0	0	0
T28	323736	0	0	0
T29	599617	0	0	0
T30	768923	0	0	0
T31	10607	0	0	0
T32	883299	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2328	0	0
T14	107379	31	0	0
T15	320641	0	0	0
T16	0	20	0	0
T17	0	19	0	0
T18	0	9	0	0
T19	0	12	0	0
T20	0	15	0	0
T21	0	12	0	0
T22	0	46	0	0
T23	0	4	0	0
T24	0	30	0	0
T25	279174	0	0	0
T26	782251	0	0	0
T27	21152	0	0	0
T28	323736	0	0	0
T29	599617	0	0	0
T30	768923	0	0	0
T31	10607	0	0	0
T32	883299	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2281	0	0
T14	107379	32	0	0
T15	320641	0	0	0
T16	0	17	0	0
T17	0	23	0	0
T18	0	9	0	0
T19	0	14	0	0
T20	0	15	0	0
T21	0	12	0	0
T22	0	34	0	0
T23	0	7	0	0
T24	0	37	0	0
T25	279174	0	0	0
T26	782251	0	0	0
T27	21152	0	0	0
T28	323736	0	0	0
T29	599617	0	0	0
T30	768923	0	0	0
T31	10607	0	0	0
T32	883299	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2291	0	0
T14	107379	48	0	0
T15	320641	0	0	0
T16	0	17	0	0
T17	0	15	0	0
T18	0	13	0	0
T19	0	12	0	0
T20	0	20	0	0
T21	0	5	0	0
T22	0	43	0	0
T23	0	26	0	0
T24	0	9	0	0
T25	279174	0	0	0
T26	782251	0	0	0
T27	21152	0	0	0
T28	323736	0	0	0
T29	599617	0	0	0
T30	768923	0	0	0
T31	10607	0	0	0
T32	883299	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2096	0	0
T14	107379	27	0	0
T15	320641	0	0	0
T16	0	22	0	0
T17	0	17	0	0
T18	0	12	0	0
T19	0	21	0	0
T20	0	25	0	0
T21	0	19	0	0
T22	0	61	0	0
T23	0	14	0	0
T24	0	30	0	0
T25	279174	0	0	0
T26	782251	0	0	0
T27	21152	0	0	0
T28	323736	0	0	0
T29	599617	0	0	0
T30	768923	0	0	0
T31	10607	0	0	0
T32	883299	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1892	0	0
T14	107379	44	0	0
T15	320641	0	0	0
T16	0	32	0	0
T17	0	17	0	0
T18	0	17	0	0
T19	0	29	0	0
T20	0	26	0	0
T21	0	21	0	0
T22	0	40	0	0
T23	0	8	0	0
T24	0	17	0	0
T25	279174	0	0	0
T26	782251	0	0	0
T27	21152	0	0	0
T28	323736	0	0	0
T29	599617	0	0	0
T30	768923	0	0	0
T31	10607	0	0	0
T32	883299	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2462	0	0
T14	107379	38	0	0
T15	320641	0	0	0
T16	0	36	0	0
T17	0	6	0	0
T18	0	21	0	0
T19	0	17	0	0
T20	0	37	0	0
T21	0	3	0	0
T22	0	45	0	0
T23	0	31	0	0
T24	0	31	0	0
T25	279174	0	0	0
T26	782251	0	0	0
T27	21152	0	0	0
T28	323736	0	0	0
T29	599617	0	0	0
T30	768923	0	0	0
T31	10607	0	0	0
T32	883299	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1894	0	0
T14	107379	41	0	0
T15	320641	0	0	0
T16	0	10	0	0
T17	0	17	0	0
T18	0	10	0	0
T19	0	24	0	0
T20	0	15	0	0
T21	0	24	0	0
T22	0	32	0	0
T23	0	22	0	0
T24	0	37	0	0
T25	279174	0	0	0
T26	782251	0	0	0
T27	21152	0	0	0
T28	323736	0	0	0
T29	599617	0	0	0
T30	768923	0	0	0
T31	10607	0	0	0
T32	883299	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2340	0	0
T14	107379	31	0	0
T15	320641	0	0	0
T16	0	26	0	0
T17	0	21	0	0
T18	0	16	0	0
T19	0	31	0	0
T20	0	6	0	0
T21	0	19	0	0
T22	0	47	0	0
T23	0	33	0	0
T24	0	17	0	0
T25	279174	0	0	0
T26	782251	0	0	0
T27	21152	0	0	0
T28	323736	0	0	0
T29	599617	0	0	0
T30	768923	0	0	0
T31	10607	0	0	0
T32	883299	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1826	0	0
T14	107379	30	0	0
T15	320641	0	0	0
T16	0	27	0	0
T17	0	22	0	0
T18	0	14	0	0
T19	0	15	0	0
T20	0	23	0	0
T21	0	13	0	0
T22	0	36	0	0
T23	0	13	0	0
T24	0	25	0	0
T25	279174	0	0	0
T26	782251	0	0	0
T27	21152	0	0	0
T28	323736	0	0	0
T29	599617	0	0	0
T30	768923	0	0	0
T31	10607	0	0	0
T32	883299	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2204	0	0
T14	107379	42	0	0
T15	320641	0	0	0
T16	0	19	0	0
T17	0	12	0	0
T18	0	11	0	0
T19	0	13	0	0
T20	0	17	0	0
T21	0	17	0	0
T22	0	36	0	0
T23	0	22	0	0
T24	0	11	0	0
T25	279174	0	0	0
T26	782251	0	0	0
T27	21152	0	0	0
T28	323736	0	0	0
T29	599617	0	0	0
T30	768923	0	0	0
T31	10607	0	0	0
T32	883299	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2560	0	0
T11	233487	13	0	0
T12	319737	0	0	0
T13	100484	0	0	0
T14	107379	49	0	0
T15	320641	0	0	0
T16	0	38	0	0
T17	0	30	0	0
T18	0	36	0	0
T19	0	44	0	0
T20	0	14	0	0
T25	279174	0	0	0
T26	782251	0	0	0
T27	21152	0	0	0
T28	323736	0	0	0
T33	0	12	0	0
T34	0	12	0	0
T35	0	12	0	0
T36	223595	0	0	0