Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1254358	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1230249

1

T1

440

T2

441

T3

1397

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2180534	1			T1	823		T3	2510		T5	1704
values[0x0]	151212	1			T1	48		T2	571		T3	125
values[0x1]	152861	1			T1	56		T2	556		T3	172

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1006009	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1478598

1

T1

548

T2

532

T3

1690

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7617	1			T1	3		T2	5		T7	1
valid_sources[0x01]	18331	1			T1	6		T2	6		T5	4
valid_sources[0x02]	7466	1			T1	4		T2	8		T5	1
valid_sources[0x03]	7548	1			T1	1		T2	6		T5	3
valid_sources[0x04]	10977	1			T1	8		T2	5		T5	3
valid_sources[0x05]	7646	1			T1	1		T2	2		T5	2
valid_sources[0x06]	9418	1			T1	5		T2	4		T5	3
valid_sources[0x07]	8732	1			T1	2		T2	5		T5	1
valid_sources[0x08]	12074	1			T1	6		T2	4		T8	15
valid_sources[0x09]	7933	1			T1	3		T2	4		T5	3
valid_sources[0x0a]	11384	1			T1	4		T2	1		T5	6
valid_sources[0x0b]	10207	1			T1	3		T2	7		T5	3
valid_sources[0x0c]	7235	1			T1	3		T2	1		T5	4
valid_sources[0x0d]	7834	1			T1	7		T2	1		T5	4
valid_sources[0x0e]	11925	1			T1	6		T2	4		T5	4
valid_sources[0x0f]	7021	1			T1	9		T2	4		T5	4
valid_sources[0x10]	7833	1			T1	6		T2	5		T5	2
valid_sources[0x11]	21457	1			T1	6		T2	5		T7	1
valid_sources[0x12]	7839	1			T1	3		T2	5		T5	5
valid_sources[0x13]	9373	1			T1	1		T2	2		T5	4
valid_sources[0x14]	8319	1			T1	2		T2	1		T5	3
valid_sources[0x15]	9428	1			T1	4		T2	3		T5	4
valid_sources[0x16]	7161	1			T1	7		T2	2		T5	4
valid_sources[0x17]	7540	1			T1	6		T2	3		T5	7
valid_sources[0x18]	7266	1			T1	2		T2	7		T5	3
valid_sources[0x19]	7535	1			T1	2		T2	1		T5	3
valid_sources[0x1a]	7373	1			T1	3		T2	4		T5	2
valid_sources[0x1b]	7093	1			T1	8		T2	5		T5	4
valid_sources[0x1c]	11219	1			T1	5		T2	4		T5	2
valid_sources[0x1d]	7369	1			T1	5		T2	4		T5	2
valid_sources[0x1e]	7109	1			T1	2		T2	8		T5	2
valid_sources[0x1f]	7248	1			T1	7		T2	4		T5	4
valid_sources[0x20]	26804	1			T1	5		T2	9		T5	2
valid_sources[0x21]	7820	1			T1	5		T2	8		T5	7
valid_sources[0x22]	7352	1			T1	5		T2	5		T5	4
valid_sources[0x23]	8437	1			T1	3		T2	10		T5	5
valid_sources[0x24]	11950	1			T1	1		T2	10		T5	5
valid_sources[0x25]	7572	1			T1	5		T2	6		T5	7
valid_sources[0x26]	12832	1			T1	3		T2	3		T5	5
valid_sources[0x27]	7479	1			T1	4		T2	5		T5	2
valid_sources[0x28]	10325	1			T1	3		T2	5		T5	5
valid_sources[0x29]	16086	1			T1	4		T2	6		T5	5
valid_sources[0x2a]	8169	1			T1	6		T2	7		T5	2
valid_sources[0x2b]	7977	1			T1	6		T2	4		T5	1
valid_sources[0x2c]	16007	1			T1	2		T2	6		T5	2
valid_sources[0x2d]	12622	1			T1	9		T2	2		T5	2
valid_sources[0x2e]	8486	1			T1	6		T2	6		T5	4
valid_sources[0x2f]	9462	1			T1	3		T2	2		T5	2
valid_sources[0x30]	7076	1			T1	2		T2	4		T5	5
valid_sources[0x31]	11574	1			T1	1		T2	5		T5	1
valid_sources[0x32]	7514	1			T1	6		T2	7		T5	6
valid_sources[0x33]	8128	1			T1	3		T2	5		T5	3
valid_sources[0x34]	11656	1			T1	3		T2	3		T5	7
valid_sources[0x35]	11607	1			T1	4		T2	3		T5	5
valid_sources[0x36]	7511	1			T1	1		T2	4		T5	3
valid_sources[0x37]	12064	1			T1	5		T2	3		T5	9
valid_sources[0x38]	7714	1			T1	2		T2	9		T5	5
valid_sources[0x39]	18596	1			T1	4		T2	3		T5	3
valid_sources[0x3a]	7406	1			T1	2		T2	2		T5	7
valid_sources[0x3b]	9748	1			T1	7		T2	3		T5	7
valid_sources[0x3c]	7419	1			T1	4		T2	4		T5	3
valid_sources[0x3d]	7810	1			T1	4		T2	3		T5	11
valid_sources[0x3e]	7484	1			T1	3		T2	3		T5	6
valid_sources[0x3f]	7079	1			T1	3		T2	5		T5	5
valid_sources[0x40]	10892	1			T1	4		T2	2		T5	3
valid_sources[0x41]	17972	1			T1	3		T2	5		T8	8
valid_sources[0x42]	7575	1			T1	2		T2	6		T5	1
valid_sources[0x43]	10958	1			T1	5		T2	2		T5	11
valid_sources[0x44]	7293	1			T1	6		T2	4		T5	3
valid_sources[0x45]	12058	1			T1	2		T2	3		T5	7
valid_sources[0x46]	7507	1			T1	3		T2	9		T5	1
valid_sources[0x47]	11301	1			T1	6		T2	3		T5	3
valid_sources[0x48]	14176	1			T1	3		T2	6		T4	1219
valid_sources[0x49]	9859	1			T1	5		T2	3		T5	6
valid_sources[0x4a]	7877	1			T1	1		T2	6		T5	6
valid_sources[0x4b]	12491	1			T1	2		T2	6		T5	7
valid_sources[0x4c]	8103	1			T2	1		T5	5		T8	10
valid_sources[0x4d]	12350	1			T1	10		T2	8		T5	2
valid_sources[0x4e]	7935	1			T1	2		T2	3		T5	3
valid_sources[0x4f]	12518	1			T1	1		T2	6		T5	4
valid_sources[0x50]	7573	1			T1	1		T2	4		T5	7
valid_sources[0x51]	7767	1			T2	2		T5	5		T8	4
valid_sources[0x52]	12741	1			T1	2		T2	2		T5	5
valid_sources[0x53]	11898	1			T1	6		T2	3		T5	7
valid_sources[0x54]	12028	1			T1	3		T2	6		T5	5
valid_sources[0x55]	7342	1			T1	3		T2	6		T5	3
valid_sources[0x56]	9072	1			T1	4		T2	4		T5	1
valid_sources[0x57]	8833	1			T1	4		T2	4		T5	3
valid_sources[0x58]	12598	1			T1	4		T2	3		T5	2
valid_sources[0x59]	13901	1			T1	5		T2	3		T5	2
valid_sources[0x5a]	8064	1			T1	1		T2	5		T5	6
valid_sources[0x5b]	9934	1			T1	2		T2	6		T5	4
valid_sources[0x5c]	8621	1			T1	3		T2	8		T5	3
valid_sources[0x5d]	7327	1			T1	2		T2	5		T5	3
valid_sources[0x5e]	11862	1			T2	6		T5	8		T8	5
valid_sources[0x5f]	8178	1			T1	2		T2	6		T5	8
valid_sources[0x60]	7156	1			T1	3		T2	5		T5	4
valid_sources[0x61]	7190	1			T1	8		T2	5		T5	5
valid_sources[0x62]	8538	1			T1	1		T2	3		T5	3
valid_sources[0x63]	11884	1			T1	7		T2	4		T5	9
valid_sources[0x64]	7928	1			T1	5		T2	4		T5	4
valid_sources[0x65]	7458	1			T1	5		T2	2		T5	5
valid_sources[0x66]	11525	1			T1	4		T2	11		T5	4
valid_sources[0x67]	17177	1			T1	6		T2	2		T5	7
valid_sources[0x68]	10952	1			T1	9		T2	4		T5	6
valid_sources[0x69]	7379	1			T1	1		T2	8		T5	3
valid_sources[0x6a]	6693	1			T1	3		T2	3		T5	4
valid_sources[0x6b]	11670	1			T1	3		T2	3		T5	2
valid_sources[0x6c]	9946	1			T1	1		T2	1		T5	5
valid_sources[0x6d]	8098	1			T1	1		T2	2		T5	4
valid_sources[0x6e]	13857	1			T1	6		T2	5		T5	3
valid_sources[0x6f]	7951	1			T1	4		T2	6		T5	2
valid_sources[0x70]	7091	1			T1	1		T2	2		T5	3
valid_sources[0x71]	9941	1			T1	2		T2	9		T5	2
valid_sources[0x72]	7261	1			T1	2		T2	7		T5	7
valid_sources[0x73]	8442	1			T1	3		T2	3		T5	5
valid_sources[0x74]	11748	1			T1	4		T2	8		T5	1
valid_sources[0x75]	17862	1			T1	3		T2	6		T5	1
valid_sources[0x76]	8959	1			T1	3		T5	2		T8	19
valid_sources[0x77]	7592	1			T1	2		T2	5		T5	2
valid_sources[0x78]	7286	1			T1	4		T2	3		T5	4
valid_sources[0x79]	14653	1			T1	2		T2	5		T5	5
valid_sources[0x7a]	7435	1			T1	2		T2	3		T5	4
valid_sources[0x7b]	7711	1			T1	2		T2	2		T5	5
valid_sources[0x7c]	8534	1			T1	4		T2	1		T5	2
valid_sources[0x7d]	13383	1			T1	3		T2	6		T5	3
valid_sources[0x7e]	12441	1			T1	3		T2	1		T5	1
valid_sources[0x7f]	7921	1			T1	1		T2	4		T5	13
valid_sources[0x80]	7772	1			T1	7		T2	5		T5	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1086970

1

T1

388

T3

1261

T5

854

values[0x0]

all_enables

biggest_size

82876

1

T1

26

T2

265

T3

63

values[0x1]

all_enables

biggest_size

60403

1

T1

26

T2

176

T3

73