Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.67	86.67	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	86.67	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.67	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	6	39	86.67

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	5	11	68.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	30361	1			T1	9		T2	220		T3	25
auto[PWRUP]	124	1			T2	1		T4	3		T9	3
auto[ONEST_0]	80	1			T4	1		T11	1		T37	2
auto[ONEST_021]	12	1			T198	1		T199	1		T104	1
auto[ONEST_1]	76	1			T2	2		T4	1		T9	2
auto[ONEST_DONE]	8	1			T9	1		T37	1		T200	1
auto[LP_0]	108	1			T2	3		T4	1		T9	4
auto[LP_021]	30	1			T14	1		T47	1		T48	1
auto[LP_1]	119	1			T2	2		T4	2		T9	4
auto[LP_EVAL]	73	1			T4	3		T9	3		T49	3
auto[LP_SLP]	512	1			T2	7		T4	9		T9	6
auto[LP_PWRUP]	26	1			T2	1		T9	2		T47	2
auto[NP_0]	134	1			T2	3		T4	2		T9	2
auto[NP_021]	34	1			T4	1		T9	1		T13	2
auto[NP_1]	151	1			T2	1		T4	1		T11	1
auto[NP_EVAL]	35	1			T4	1		T11	1		T47	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

5

1

T201

1

T82

1

T202

1

min

29793

1

T1

9

T2

216

T3

25

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29798	1			T1	9		T2	216		T3	25
pow[0x1]	6	1			T48	1		T203	1		T204	1
pow[0x2]	16	1			T9	1		T205	1		T203	1
pow[0x3]	30	1			T2	1		T37	1		T47	2
pow[0x4]	66	1			T4	1		T9	1		T13	1
pow[0x5]	138	1			T2	2		T4	5		T9	3
pow[0x6]	248	1			T2	3		T4	5		T9	3
pow[0x7]	507	1			T2	5		T4	9		T9	13

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

197

1

T2

3

T4

5

T9

5

min

29303

1

T1

9

T2

208

T3

25

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	5	11	68.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29303	1			T1	9		T2	208		T3	25
pow[0x6]	2	1			T206	1		T207	1		-	-
pow[0x7]	1	1			T208	1		-	-		-	-
pow[0x8]	5	1			T47	1		T203	1		T209	1
pow[0x9]	4	1			T210	1		T211	1		T212	1
pow[0xa]	16	1			T11	1		T205	1		T198	1
pow[0xb]	42	1			T4	2		T9	1		T200	1
pow[0xc]	71	1			T4	2		T9	1		T11	1
pow[0xd]	160	1			T2	4		T4	5		T9	3
pow[0xe]	290	1			T2	4		T4	3		T9	6
pow[0xf]	612	1			T2	6		T4	13		T9	6