Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2315	1			T2	23		T4	20		T9	22
auto[PWRUP]	141	1			T2	5		T4	1		T9	2
auto[ONEST_0]	63	1			T9	2		T11	3		T49	1
auto[ONEST_021]	19	1			T2	1		T11	1		T49	1
auto[ONEST_1]	72	1			T2	1		T4	1		T9	2
auto[ONEST_DONE]	5	1			T327	1		T328	1		T204	1
auto[LP_0]	115	1			T4	4		T11	1		T13	4
auto[LP_021]	32	1			T46	1		T329	2		T203	1
auto[LP_1]	141	1			T2	4		T4	5		T9	2
auto[LP_EVAL]	47	1			T2	1		T14	1		T37	2
auto[LP_SLP]	545	1			T2	5		T4	5		T9	11
auto[LP_PWRUP]	30	1			T9	1		T13	1		T200	2
auto[NP_0]	240	1			T2	1		T4	3		T9	2
auto[NP_021]	46	1			T9	2		T13	3		T14	1
auto[NP_1]	217	1			T2	3		T4	2		T9	2
auto[NP_EVAL]	34	1			T2	1		T4	1		T14	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

13

1

T46

1

T198

1

T330

1

min

1985

1

T2

9

T4

10

T9

19

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1993	1			T2	9		T4	10		T9	19
pow[0x1]	8	1			T35	1		T331	1		T332	1
pow[0x2]	23	1			T9	1		T13	1		T14	1
pow[0x3]	22	1			T4	1		T9	1		T11	1
pow[0x4]	67	1			T2	2		T4	1		T9	1
pow[0x5]	117	1			T2	1		T9	2		T11	3
pow[0x6]	238	1			T2	2		T4	5		T9	2
pow[0x7]	542	1			T2	11		T4	11		T9	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

187

1

T2

3

T4

3

T9

1

min

1360

1

T2

2

T4

4

T9

8

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1366	1			T2	2		T4	4		T9	8
pow[0x1]	21	1			T39	1		T42	1		T102	5
pow[0x2]	27	1			T13	1		T38	1		T16	6
pow[0x3]	44	1			T13	1		T14	2		T38	2
pow[0x4]	57	1			T4	1		T13	1		T199	2
pow[0x5]	1	1			T333	1		-	-		-	-
pow[0x6]	2	1			T334	1		T211	1		-	-
pow[0x7]	2	1			T335	1		T336	1		-	-
pow[0x8]	8	1			T198	1		T57	1		T104	1
pow[0x9]	11	1			T200	1		T205	2		T330	1
pow[0xa]	12	1			T2	3		T13	1		T37	1
pow[0xb]	37	1			T11	1		T49	1		T37	1
pow[0xc]	84	1			T4	1		T9	2		T13	1
pow[0xd]	156	1			T2	4		T4	6		T9	4
pow[0xe]	293	1			T2	3		T4	3		T9	7
pow[0xf]	577	1			T2	10		T4	12		T9	12