Unified Coverage Report :: Module :: adc_ctrl_core

Module : adc_ctrl_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_adc_ctrl_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.83	100.00	99.76		100.00	99.37	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_ctrl_fsm	99.75	100.00	100.00		100.00	98.73	100.00
u_adc_ctrl_intr	99.00	100.00	96.00			100.00	100.00
u_oneshot_done_sync	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
TOTAL		63	63	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	73	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	213	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	8	8
63	8	8
72	1	1
73	1	1
74	1	1
75	1	1
83	1	1
86	1	1
87	1	1
88	1	1
89	1	1
104	8	8
107	8	8
117	8	8
121	8	8
137	1	1
138	1	1
140	1	1
141	1	1
145	1	1
213	1	1

---

Cond Coverage for Module : adc_ctrl_core

	Total	Covered	Percent
Conditions	293	293	100.00
Logical	293	293	100.00
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION (reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done : (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0))
             -----------------1----------------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T3,T6

 LINE       83
 SUB-EXPRESSION (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0)
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][0].cond)) ? ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v)) : ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v)))

-1-	Status	Tests
0	Covered	T10,T12,T13
1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T12,T13
0	1	Covered	T10,T12,T13
1	0	Covered	T10,T12,T13

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][1].cond)) ? ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v)) : ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v)))

-1-	Status	Tests
0	Covered	T3,T10,T12
1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T12
0	1	Covered	T3,T10,T12
1	0	Covered	T3,T10,T12

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][2].cond)) ? ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v)) : ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v)))

-1-	Status	Tests
0	Covered	T5,T10,T13
1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T10,T13
0	1	Covered	T5,T10,T13
1	0	Covered	T5,T10,T13

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][3].cond)) ? ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v)) : ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v)))

-1-	Status	Tests
0	Covered	T10,T12,T13
1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T12,T13
0	1	Covered	T10,T12,T13
1	0	Covered	T10,T12,T13

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][4].cond)) ? ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v)) : ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v)))

-1-	Status	Tests
0	Covered	T3,T10,T12
1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T12
0	1	Covered	T3,T10,T12
1	0	Covered	T3,T10,T12

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][5].cond)) ? ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v)) : ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v)))

-1-	Status	Tests
0	Covered	T3,T5,T10
1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T10
0	1	Covered	T3,T5,T10
1	0	Covered	T3,T5,T10

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][6].cond)) ? ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v)) : ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v)))

-1-	Status	Tests
0	Covered	T5,T10,T12
1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T10,T12
0	1	Covered	T5,T10,T12
1	0	Covered	T5,T10,T12

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][7].cond)) ? ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v)) : ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v)))

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T39
1	0	Covered	T2,T3,T6
1	1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T5
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T5

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][0].cond)) ? ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v)) : ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v)))

-1-	Status	Tests
0	Covered	T5,T10,T12
1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T10,T12
0	1	Covered	T5,T10,T12
1	0	Covered	T5,T10,T12

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][1].cond)) ? ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v)) : ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v)))

-1-	Status	Tests
0	Covered	T10,T12,T13
1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T12,T13
0	1	Covered	T10,T12,T13
1	0	Covered	T10,T12,T13

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][2].cond)) ? ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v)) : ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v)))

-1-	Status	Tests
0	Covered	T5,T10,T13
1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T10,T13
0	1	Covered	T5,T10,T13
1	0	Covered	T5,T10,T13

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][3].cond)) ? ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v)) : ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v)))

-1-	Status	Tests
0	Covered	T10,T12,T13
1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T12,T13
0	1	Covered	T10,T12,T13
1	0	Covered	T10,T12,T13

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][4].cond)) ? ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v)) : ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v)))

-1-	Status	Tests
0	Covered	T3,T10,T12
1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T12
0	1	Covered	T3,T10,T12
1	0	Covered	T3,T10,T12

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][5].cond)) ? ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v)) : ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v)))

-1-	Status	Tests
0	Covered	T3,T5,T10
1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T10
0	1	Covered	T3,T5,T10
1	0	Covered	T3,T5,T10

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][6].cond)) ? ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v)) : ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v)))

-1-	Status	Tests
0	Covered	T5,T10,T12
1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T10,T12
0	1	Covered	T5,T10,T12
1	0	Covered	T5,T10,T12

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][7].cond)) ? ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v)) : ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v)))

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T13
1	0	Covered	T2,T3,T6
1	1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T5
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T5

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][0].en, aon_filter_ctl[1][0].en})) & 
      2  (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en)) & 
      3  (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T2
1	0	1	Covered	T1,T5,T8
1	1	0	Covered	T1,T5,T8
1	1	1	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[0] & aon_filter_ctl[0][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T8
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[0] & aon_filter_ctl[1][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T8
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T2,T3

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][1].en, aon_filter_ctl[1][1].en})) & 
      2  (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en)) & 
      3  (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T2
1	0	1	Covered	T1,T3,T8
1	1	0	Covered	T1,T3,T8
1	1	1	Covered	T1,T3,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T1,T3,T8
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[1] & aon_filter_ctl[0][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T3,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T1,T3,T8
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[1] & aon_filter_ctl[1][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T3,T8

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][2].en, aon_filter_ctl[1][2].en})) & 
      2  (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en)) & 
      3  (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T2
1	0	1	Covered	T1,T3,T8
1	1	0	Covered	T1,T3,T8
1	1	1	Covered	T1,T3,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T1,T3,T8
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[2] & aon_filter_ctl[0][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T3,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T1,T3,T8
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[2] & aon_filter_ctl[1][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T3,T8

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][3].en, aon_filter_ctl[1][3].en})) & 
      2  (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en)) & 
      3  (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T2
1	0	1	Covered	T1,T5,T8
1	1	0	Covered	T1,T5,T8
1	1	1	Covered	T1,T5,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T8
0	1	Covered	T1,T5,T8
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[3] & aon_filter_ctl[0][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T8
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T5,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T8
0	1	Covered	T1,T5,T8
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[3] & aon_filter_ctl[1][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T8
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T5,T8

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][4].en, aon_filter_ctl[1][4].en})) & 
      2  (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en)) & 
      3  (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T2
1	0	1	Covered	T1,T5,T8
1	1	0	Covered	T1,T5,T8
1	1	1	Covered	T1,T5,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T8
0	1	Covered	T1,T5,T8
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[4] & aon_filter_ctl[0][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T8
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T5,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T8
0	1	Covered	T1,T5,T8
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[4] & aon_filter_ctl[1][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T8
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T5,T8

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][5].en, aon_filter_ctl[1][5].en})) & 
      2  (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en)) & 
      3  (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T2
1	0	1	Covered	T1,T5,T8
1	1	0	Covered	T1,T5,T8
1	1	1	Covered	T1,T5,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T8
0	1	Covered	T1,T5,T8
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[5] & aon_filter_ctl[0][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T8
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T5,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T8
0	1	Covered	T1,T5,T8
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[5] & aon_filter_ctl[1][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T8
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T5,T8

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][6].en, aon_filter_ctl[1][6].en})) & 
      2  (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en)) & 
      3  (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T2
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T1,T3,T5
1	1	1	Covered	T1,T3,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T5
0	1	Covered	T1,T3,T5
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[6] & aon_filter_ctl[0][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T3,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T5
0	1	Covered	T1,T3,T5
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[6] & aon_filter_ctl[1][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T3,T5

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][7].en, aon_filter_ctl[1][7].en})) & 
      2  (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en)) & 
      3  (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T2
1	0	1	Covered	T1,T3,T8
1	1	0	Covered	T1,T3,T8
1	1	1	Covered	T1,T3,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T1,T3,T8
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[7] & aon_filter_ctl[0][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T3,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T1,T3,T8
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[7] & aon_filter_ctl[1][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T3,T8

 LINE       121
 EXPRESSION (adc_ctrl_done && match[0])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T6

 LINE       121
 EXPRESSION (adc_ctrl_done && match[1])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T8,T9

 LINE       121
 EXPRESSION (adc_ctrl_done && match[2])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T8

 LINE       121
 EXPRESSION (adc_ctrl_done && match[3])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T8
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T5,T8

 LINE       121
 EXPRESSION (adc_ctrl_done && match[4])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T8
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T5,T8

 LINE       121
 EXPRESSION (adc_ctrl_done && match[5])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T8
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T5,T8

 LINE       121
 EXPRESSION (adc_ctrl_done && match[6])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

 LINE       121
 EXPRESSION (adc_ctrl_done && match[7])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T8

 LINE       140
 EXPRESSION (aon_fsm_trans | reg2hw_i.filter_status.trans.q)
             ------1------   ---------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Covered	T8,T39,T40
1	0	Covered	T8,T39,T40

 LINE       145
 EXPRESSION (((|(reg2hw_i.filter_status.match.q & reg2hw_i.adc_wakeup_ctl.match_en.q))) || (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q))
             -------------------------------------1------------------------------------    ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Covered	T8,T39,T40
1	0	Covered	T8,T39,T40

 LINE       145
 SUB-EXPRESSION (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q)
                 ---------------1--------------   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T39,T40
1	0	Covered	T39,T31,T48
1	1	Covered	T8,T39,T40

---

Branch Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	83	3	3	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	83	(reg2hw_i.adc_en_ctl.oneshot_mode.q) ? 
-2-:	83	(reg2hw_i.adc_en_ctl.adc_enable.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T6
0	1	Covered	T1,T2,T3
0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T10,T12,T13

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T5,T10,T12

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T3,T10,T12

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T10,T12,T13

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T5,T10,T13

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T5,T10,T13

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T10,T12,T13

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T10,T12,T13

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T3,T10,T12

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T3,T10,T12

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T3,T5,T10

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T3,T5,T10

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T5,T10,T12

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T5,T10,T12

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T1,T3,T5

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T1,T3,T5

---

Assert Coverage for Module : adc_ctrl_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	33	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	33	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxFilters_A	34329144	33998601	0	0
gen_filter_match[0].MatchCheck00_A	34329144	9932254	0	0
gen_filter_match[0].MatchCheck01_A	34329144	2287876	0	0
gen_filter_match[0].MatchCheck10_A	34329144	2250004	0	0
gen_filter_match[0].MatchCheck11_A	34329144	19528467	0	0
gen_filter_match[1].MatchCheck00_A	34329144	11856077	0	0
gen_filter_match[1].MatchCheck01_A	34329144	1183272	0	0
gen_filter_match[1].MatchCheck10_A	34329144	812745	0	0
gen_filter_match[1].MatchCheck11_A	34329144	20146507	0	0
gen_filter_match[2].MatchCheck00_A	34329144	12310287	0	0
gen_filter_match[2].MatchCheck01_A	34329144	748853	0	0
gen_filter_match[2].MatchCheck10_A	34329144	860683	0	0
gen_filter_match[2].MatchCheck11_A	34329144	20078778	0	0
gen_filter_match[3].MatchCheck00_A	34329144	11988006	0	0
gen_filter_match[3].MatchCheck01_A	34329144	305285	0	0
gen_filter_match[3].MatchCheck10_A	34329144	285461	0	0
gen_filter_match[3].MatchCheck11_A	34329144	21419849	0	0
gen_filter_match[4].MatchCheck00_A	34329144	11677778	0	0
gen_filter_match[4].MatchCheck01_A	34329144	9	0	0
gen_filter_match[4].MatchCheck10_A	34329144	66789	0	0
gen_filter_match[4].MatchCheck11_A	34329144	22254025	0	0
gen_filter_match[5].MatchCheck00_A	34329144	12477644	0	0
gen_filter_match[5].MatchCheck01_A	34329144	48832	0	0
gen_filter_match[5].MatchCheck10_A	34329144	158736	0	0
gen_filter_match[5].MatchCheck11_A	34329144	21313389	0	0
gen_filter_match[6].MatchCheck00_A	34329144	12565844	0	0
gen_filter_match[6].MatchCheck01_A	34329144	162591	0	0
gen_filter_match[6].MatchCheck10_A	34329144	97248	0	0
gen_filter_match[6].MatchCheck11_A	34329144	21172918	0	0
gen_filter_match[7].MatchCheck00_A	34329144	12171772	0	0
gen_filter_match[7].MatchCheck01_A	34329144	203137	0	0
gen_filter_match[7].MatchCheck10_A	34329144	170941	0	0
gen_filter_match[7].MatchCheck11_A	34329144	21452751	0	0

MaxFilters_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34329144	33998601	0	0
T1	97062	97000	0	0
T2	21399	19470	0	0
T3	46241	43805	0	0
T4	85	6	0	0
T5	33582	33528	0	0
T6	24395	21471	0	0
T7	7686	7602	0	0
T8	40976	40883	0	0
T9	65513	65439	0	0
T10	96906	96841	0	0

gen_filter_match[0].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34329144	9932254	0	0
T1	97062	3	0	0
T2	21399	18571	0	0
T3	46241	43052	0	0
T4	85	6	0	0
T5	33582	3	0	0
T6	24395	19192	0	0
T7	7686	7602	0	0
T8	40976	3	0	0
T9	65513	3	0	0
T10	96906	65327	0	0

gen_filter_match[0].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34329144	2287876	0	0
T15	32966	0	0	0
T17	0	17876	0	0
T25	876	0	0	0
T26	98169	0	0	0
T28	0	33318	0	0
T39	102242	34818	0	0
T40	123514	0	0	0
T46	64179	0	0	0
T47	68515	0	0	0
T88	97660	31903	0	0
T111	1154	0	0	0
T134	0	33671	0	0
T135	0	33223	0	0
T136	0	32512	0	0
T137	0	64744	0	0
T138	0	32845	0	0
T139	0	1	0	0
T140	64994	0	0	0

gen_filter_match[0].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34329144	2250004	0	0
T12	98911	32982	0	0
T13	99881	0	0	0
T14	19889	0	0	0
T15	0	11383	0	0
T38	20419	0	0	0
T39	102242	0	0	0
T40	123514	0	0	0
T41	0	12662	0	0
T44	14484	0	0	0
T46	64179	0	0	0
T47	0	34725	0	0
T88	97660	0	0	0
T111	1154	0	0	0
T138	0	31875	0	0
T141	0	32963	0	0
T142	0	35134	0	0
T143	0	32695	0	0
T144	0	32451	0	0
T145	0	1	0	0

gen_filter_match[0].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34329144	19528467	0	0
T1	97062	96997	0	0
T2	21399	899	0	0
T3	46241	753	0	0
T5	33582	33525	0	0
T6	24395	2279	0	0
T7	7686	0	0	0
T8	40976	40880	0	0
T9	65513	65436	0	0
T10	96906	31514	0	0
T11	1113	0	0	0
T12	0	32963	0	0
T38	0	794	0	0

gen_filter_match[1].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34329144	11856077	0	0
T1	97062	3	0	0
T2	21399	19470	0	0
T3	46241	17438	0	0
T4	85	6	0	0
T5	33582	33528	0	0
T6	24395	21471	0	0
T7	7686	7602	0	0
T8	40976	3	0	0
T9	65513	3	0	0
T10	96906	32390	0	0

gen_filter_match[1].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34329144	1183272	0	0
T10	96906	32937	0	0
T11	1113	0	0	0
T12	98911	0	0	0
T13	99881	0	0	0
T14	19889	0	0	0
T37	0	7695	0	0
T38	20419	0	0	0
T39	102242	0	0	0
T40	123514	34561	0	0
T43	1161	0	0	0
T44	14484	0	0	0
T146	0	34688	0	0
T147	0	31985	0	0
T148	0	34696	0	0
T149	0	56035	0	0
T150	0	70402	0	0
T151	0	1	0	0
T152	0	32583	0	0

gen_filter_match[1].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34329144	812745	0	0
T41	0	6330	0	0
T45	0	4	0	0
T56	0	1	0	0
T135	33319	0	0	0
T139	0	1	0	0
T142	70926	0	0	0
T143	98429	0	0	0
T145	0	1	0	0
T153	68948	36231	0	0
T154	32375	32306	0	0
T155	0	32952	0	0
T156	0	33229	0	0
T157	0	35179	0	0
T158	98732	0	0	0
T159	65674	0	0	0
T160	96939	0	0	0
T161	64662	0	0	0
T162	35762	0	0	0

gen_filter_match[1].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34329144	20146507	0	0
T1	97062	96997	0	0
T2	21399	0	0	0
T3	46241	26367	0	0
T5	33582	0	0	0
T6	24395	0	0	0
T7	7686	0	0	0
T8	40976	40880	0	0
T9	65513	65436	0	0
T10	96906	31514	0	0
T11	1113	0	0	0
T12	0	98820	0	0
T13	0	99811	0	0
T40	0	32880	0	0
T46	0	31884	0	0
T88	0	31903	0	0

gen_filter_match[2].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34329144	12310287	0	0
T1	97062	3	0	0
T2	21399	19470	0	0
T3	46241	17438	0	0
T4	85	6	0	0
T5	33582	33528	0	0
T6	24395	21471	0	0
T7	7686	7602	0	0
T8	40976	3	0	0
T9	65513	3	0	0
T10	96906	4	0	0

gen_filter_match[2].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34329144	748853	0	0
T10	96906	32386	0	0
T11	1113	0	0	0
T12	98911	0	0	0
T13	99881	0	0	0
T14	19889	0	0	0
T38	20419	0	0	0
T39	102242	0	0	0
T40	123514	0	0	0
T43	1161	0	0	0
T44	14484	0	0	0
T82	0	68342	0	0
T83	0	33061	0	0
T138	0	32266	0	0
T144	0	1	0	0
T151	0	33319	0	0
T163	0	33024	0	0
T164	0	31852	0	0
T165	0	31886	0	0
T166	0	33964	0	0

gen_filter_match[2].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34329144	860683	0	0
T15	32966	0	0	0
T25	876	0	0	0
T26	98169	0	0	0
T39	102242	33584	0	0
T40	123514	0	0	0
T46	64179	31884	0	0
T47	68515	0	0	0
T49	0	33643	0	0
T88	97660	33537	0	0
T111	1154	0	0	0
T140	64994	31950	0	0
T141	0	32662	0	0
T145	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0

gen_filter_match[2].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34329144	20078778	0	0
T1	97062	96997	0	0
T2	21399	0	0	0
T3	46241	26367	0	0
T5	33582	0	0	0
T6	24395	0	0	0
T7	7686	0	0	0
T8	40976	40880	0	0
T9	65513	65436	0	0
T10	96906	64451	0	0
T11	1113	0	0	0
T12	0	32963	0	0
T13	0	33546	0	0
T39	0	34818	0	0
T46	0	32202	0	0
T88	0	64070	0	0

gen_filter_match[3].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34329144	11988006	0	0
T1	97062	3	0	0
T2	21399	19470	0	0
T3	46241	43805	0	0
T4	85	6	0	0
T5	33582	3	0	0
T6	24395	21471	0	0
T7	7686	7602	0	0
T8	40976	3	0	0
T9	65513	3	0	0
T10	96906	32941	0	0

gen_filter_match[3].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34329144	305285	0	0
T13	99881	33580	0	0
T14	19889	0	0	0
T31	0	34795	0	0
T39	102242	0	0	0
T40	123514	0	0	0
T44	14484	0	0	0
T46	64179	0	0	0
T47	68515	0	0	0
T48	0	37722	0	0
T88	97660	0	0	0
T111	1154	0	0	0
T137	0	1	0	0
T140	64994	0	0	0
T144	0	31977	0	0
T153	0	32617	0	0
T169	0	36116	0	0
T170	0	1	0	0
T171	0	32228	0	0
T172	0	1	0	0

gen_filter_match[3].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34329144	285461	0	0
T9	65513	1	0	0
T10	96906	0	0	0
T11	1113	0	0	0
T12	98911	0	0	0
T13	99881	0	0	0
T14	19889	0	0	0
T15	0	1	0	0
T28	0	1	0	0
T38	20419	0	0	0
T39	102242	0	0	0
T41	0	6119	0	0
T43	1161	0	0	0
T44	14484	0	0	0
T137	0	2	0	0
T145	0	1	0	0
T163	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T173	0	1	0	0

gen_filter_match[3].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34329144	21419849	0	0
T1	97062	96997	0	0
T2	21399	0	0	0
T3	46241	0	0	0
T5	33582	33525	0	0
T6	24395	0	0	0
T7	7686	0	0	0
T8	40976	40880	0	0
T9	65513	65435	0	0
T10	96906	63900	0	0
T11	1113	0	0	0
T12	0	65945	0	0
T39	0	33783	0	0
T40	0	67441	0	0
T88	0	65440	0	0
T140	0	64927	0	0

gen_filter_match[4].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34329144	11677778	0	0
T1	97062	3	0	0
T2	21399	19470	0	0
T3	46241	43805	0	0
T4	85	6	0	0
T5	33582	3	0	0
T6	24395	21471	0	0
T7	7686	7602	0	0
T8	40976	3	0	0
T9	65513	3	0	0
T10	96906	65327	0	0

gen_filter_match[4].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34329144	9	0	0
T63	1572	0	0	0
T79	40603	0	0	0
T104	0	1	0	0
T139	125474	2	0	0
T166	0	1	0	0
T170	0	1	0	0
T172	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	32037	0	0	0
T178	13159	0	0	0
T179	1029	0	0	0
T180	65918	0	0	0
T181	70	0	0	0
T182	65707	0	0	0
T183	117436	0	0	0

gen_filter_match[4].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34329144	66789	0	0
T9	65513	1	0	0
T10	96906	0	0	0
T11	1113	0	0	0
T12	98911	0	0	0
T13	99881	0	0	0
T14	19889	0	0	0
T15	0	2	0	0
T38	20419	0	0	0
T39	102242	0	0	0
T43	1161	0	0	0
T44	14484	0	0	0
T137	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0
T173	0	1	0	0
T184	0	2	0	0

gen_filter_match[4].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34329144	22254025	0	0
T1	97062	96997	0	0
T2	21399	0	0	0
T3	46241	0	0	0
T5	33582	33525	0	0
T6	24395	0	0	0
T7	7686	0	0	0
T8	40976	40880	0	0
T9	65513	65435	0	0
T10	96906	31514	0	0
T11	1113	0	0	0
T12	0	65838	0	0
T13	0	66231	0	0
T39	0	102185	0	0
T40	0	67441	0	0
T88	0	31903	0	0

gen_filter_match[5].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34329144	12477644	0	0
T1	97062	3	0	0
T2	21399	19470	0	0
T3	46241	43805	0	0
T4	85	6	0	0
T5	33582	3	0	0
T6	24395	21471	0	0
T7	7686	7602	0	0
T8	40976	3	0	0
T9	65513	3	0	0
T10	96906	32390	0	0

gen_filter_match[5].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34329144	48832	0	0
T41	84162	0	0	0
T42	13713	0	0	0
T56	0	1	0	0
T95	0	1	0	0
T104	0	1	0	0
T144	96483	1	0	0
T152	0	1	0	0
T166	0	1	0	0
T169	36214	0	0	0
T173	122235	0	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	1	0	0
T188	0	2	0	0
T189	98231	0	0	0
T190	80624	0	0	0
T191	125279	0	0	0
T192	119	0	0	0
T193	14373	0	0	0

gen_filter_match[5].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34329144	158736	0	0
T9	65513	1	0	0
T10	96906	0	0	0
T11	1113	0	0	0
T12	98911	0	0	0
T13	99881	0	0	0
T14	19889	0	0	0
T28	0	1	0	0
T38	20419	0	0	0
T39	102242	0	0	0
T43	1161	0	0	0
T44	14484	0	0	0
T137	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0
T163	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	0	2	0	0
T173	0	1	0	0

gen_filter_match[5].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34329144	21313389	0	0
T1	97062	96997	0	0
T2	21399	0	0	0
T3	46241	0	0	0
T5	33582	33525	0	0
T6	24395	0	0	0
T7	7686	0	0	0
T8	40976	40880	0	0
T9	65513	65435	0	0
T10	96906	64451	0	0
T11	1113	0	0	0
T12	0	65945	0	0
T13	0	32685	0	0
T39	0	68402	0	0
T40	0	34561	0	0
T88	0	65704	0	0

gen_filter_match[6].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34329144	12565844	0	0
T1	97062	3	0	0
T2	21399	19470	0	0
T3	46241	17438	0	0
T4	85	6	0	0
T5	33582	3	0	0
T6	24395	21471	0	0
T7	7686	7602	0	0
T8	40976	3	0	0
T9	65513	3	0	0
T10	96906	32390	0	0

gen_filter_match[6].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34329144	162591	0	0
T95	0	1	0	0
T105	0	32494	0	0
T135	33319	0	0	0
T143	98429	1	0	0
T151	0	2	0	0
T154	32375	0	0	0
T158	98732	0	0	0
T159	65674	0	0	0
T160	96939	0	0	0
T161	64662	0	0	0
T162	35762	0	0	0
T166	0	1	0	0
T172	0	1	0	0
T175	0	1	0	0
T186	0	1	0	0
T194	0	31509	0	0
T195	0	1	0	0
T196	25285	0	0	0
T197	32883	0	0	0

gen_filter_match[6].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34329144	97248	0	0
T9	65513	1	0	0
T10	96906	0	0	0
T11	1113	0	0	0
T12	98911	0	0	0
T13	99881	0	0	0
T14	19889	0	0	0
T15	0	3	0	0
T28	0	2	0	0
T38	20419	0	0	0
T39	102242	0	0	0
T43	1161	0	0	0
T44	14484	0	0	0
T137	0	1	0	0
T145	0	2	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	0	2	0	0
T173	0	1	0	0
T184	0	2	0	0

gen_filter_match[6].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34329144	21172918	0	0
T1	97062	96997	0	0
T2	21399	0	0	0
T3	46241	26367	0	0
T5	33582	33525	0	0
T6	24395	0	0	0
T7	7686	0	0	0
T8	40976	40880	0	0
T9	65513	65435	0	0
T10	96906	64451	0	0
T11	1113	0	0	0
T12	0	65945	0	0
T13	0	32685	0	0
T39	0	102185	0	0
T40	0	55993	0	0

gen_filter_match[7].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34329144	12171772	0	0
T1	97062	3	0	0
T2	21399	19470	0	0
T3	46241	17438	0	0
T4	85	6	0	0
T5	33582	33528	0	0
T6	24395	21471	0	0
T7	7686	7602	0	0
T8	40976	3	0	0
T9	65513	3	0	0
T10	96906	32941	0	0

gen_filter_match[7].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34329144	203137	0	0
T13	99881	32685	0	0
T14	19889	0	0	0
T22	0	33453	0	0
T39	102242	0	0	0
T40	123514	0	0	0
T44	14484	0	0	0
T46	64179	0	0	0
T47	68515	0	0	0
T56	0	1	0	0
T88	97660	0	0	0
T111	1154	0	0	0
T139	0	1	0	0
T140	64994	0	0	0
T143	0	1	0	0
T161	0	31904	0	0
T166	0	1	0	0
T172	0	1	0	0
T175	0	1	0	0
T188	0	3	0	0

gen_filter_match[7].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34329144	170941	0	0
T9	65513	1	0	0
T10	96906	0	0	0
T11	1113	0	0	0
T12	98911	0	0	0
T13	99881	0	0	0
T14	19889	0	0	0
T28	0	1	0	0
T38	20419	0	0	0
T39	102242	0	0	0
T43	1161	0	0	0
T44	14484	0	0	0
T56	0	1	0	0
T144	0	1	0	0
T145	0	2	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0
T173	0	1	0	0
T184	0	1	0	0

gen_filter_match[7].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34329144	21452751	0	0
T1	97062	96997	0	0
T2	21399	0	0	0
T3	46241	26367	0	0
T5	33582	0	0	0
T6	24395	0	0	0
T7	7686	0	0	0
T8	40976	40880	0	0
T9	65513	65435	0	0
T10	96906	63900	0	0
T11	1113	0	0	0
T12	0	32875	0	0
T13	0	67126	0	0
T39	0	68601	0	0
T40	0	67441	0	0
T88	0	64070	0	0