Line Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Module :
prim_pulse_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T4,T1,T2 |
1 | 0 | Covered | T4,T1,T2 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T4,T1,T2 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T1,T2 |
Branch Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Module :
prim_pulse_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
356134 |
0 |
0 |
T1 |
11715753 |
126 |
0 |
0 |
T2 |
5178976 |
1305 |
0 |
0 |
T3 |
15306299 |
1244 |
0 |
0 |
T4 |
38076 |
0 |
0 |
0 |
T5 |
4281936 |
42 |
0 |
0 |
T6 |
3217871 |
1300 |
0 |
0 |
T7 |
8379060 |
70 |
0 |
0 |
T8 |
3339659 |
42 |
0 |
0 |
T9 |
20407679 |
84 |
0 |
0 |
T10 |
13023964 |
126 |
0 |
0 |
T11 |
2948463 |
102 |
0 |
0 |
T12 |
672586 |
108 |
0 |
0 |
T13 |
574339 |
84 |
0 |
0 |
T14 |
994518 |
37 |
0 |
0 |
T15 |
0 |
62 |
0 |
0 |
T37 |
0 |
1 |
0 |
0 |
T38 |
122519 |
457 |
0 |
0 |
T39 |
0 |
84 |
0 |
0 |
T40 |
0 |
84 |
0 |
0 |
T43 |
1117888 |
20 |
0 |
0 |
T44 |
188302 |
34 |
0 |
0 |
T111 |
0 |
20 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
359894 |
0 |
0 |
T1 |
12074900 |
126 |
0 |
0 |
T2 |
5178976 |
1305 |
0 |
0 |
T3 |
15907456 |
1249 |
0 |
0 |
T4 |
38076 |
0 |
0 |
0 |
T5 |
4407879 |
42 |
0 |
0 |
T6 |
3314239 |
1300 |
0 |
0 |
T7 |
8744205 |
70 |
0 |
0 |
T8 |
3401128 |
42 |
0 |
0 |
T9 |
21161095 |
84 |
0 |
0 |
T10 |
13392198 |
126 |
0 |
0 |
T11 |
3086587 |
102 |
0 |
0 |
T12 |
1048439 |
108 |
0 |
0 |
T13 |
574339 |
84 |
0 |
0 |
T14 |
994518 |
37 |
0 |
0 |
T15 |
0 |
66 |
0 |
0 |
T37 |
0 |
9 |
0 |
0 |
T38 |
122519 |
457 |
0 |
0 |
T39 |
0 |
84 |
0 |
0 |
T40 |
0 |
84 |
0 |
0 |
T43 |
1117888 |
20 |
0 |
0 |
T44 |
188302 |
34 |
0 |
0 |
T111 |
0 |
20 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 5 | 2 | 40.00 |
Logical | 5 | 2 | 40.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Unreachable | |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Unreachable | |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 5 | 2 | 40.00 |
Logical | 5 | 2 | 40.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Unreachable | |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Unreachable | |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 6 | 75.00 |
Logical | 8 | 6 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T3,T15,T37 |
1 | 0 | Covered | T3,T15,T37 |
1 | 1 | Not Covered | |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T3,T15,T37 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T3,T15,T37 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
80 |
0 |
0 |
T3 |
46241 |
1 |
0 |
0 |
T5 |
33582 |
0 |
0 |
0 |
T6 |
24395 |
0 |
0 |
0 |
T7 |
7686 |
0 |
0 |
0 |
T8 |
40976 |
0 |
0 |
0 |
T9 |
65513 |
0 |
0 |
0 |
T10 |
96906 |
0 |
0 |
0 |
T11 |
1113 |
0 |
0 |
0 |
T12 |
98911 |
0 |
0 |
0 |
T15 |
0 |
1 |
0 |
0 |
T16 |
0 |
1 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
1 |
0 |
0 |
T19 |
0 |
1 |
0 |
0 |
T37 |
0 |
1 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T42 |
0 |
1 |
0 |
0 |
T43 |
1161 |
0 |
0 |
0 |
T45 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
393 |
0 |
0 |
T3 |
647398 |
5 |
0 |
0 |
T5 |
159525 |
0 |
0 |
0 |
T6 |
120763 |
0 |
0 |
0 |
T7 |
372831 |
0 |
0 |
0 |
T8 |
102445 |
0 |
0 |
0 |
T9 |
818929 |
0 |
0 |
0 |
T10 |
465140 |
0 |
0 |
0 |
T11 |
139237 |
0 |
0 |
0 |
T12 |
474764 |
0 |
0 |
0 |
T15 |
0 |
5 |
0 |
0 |
T16 |
0 |
5 |
0 |
0 |
T17 |
0 |
5 |
0 |
0 |
T18 |
0 |
8 |
0 |
0 |
T19 |
0 |
5 |
0 |
0 |
T37 |
0 |
9 |
0 |
0 |
T41 |
0 |
9 |
0 |
0 |
T42 |
0 |
10 |
0 |
0 |
T43 |
557783 |
0 |
0 |
0 |
T45 |
0 |
5 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
39836 |
0 |
0 |
T1 |
97062 |
9 |
0 |
0 |
T2 |
21399 |
353 |
0 |
0 |
T3 |
46241 |
336 |
0 |
0 |
T5 |
33582 |
3 |
0 |
0 |
T6 |
24395 |
361 |
0 |
0 |
T7 |
7686 |
35 |
0 |
0 |
T8 |
40976 |
3 |
0 |
0 |
T9 |
65513 |
6 |
0 |
0 |
T10 |
96906 |
9 |
0 |
0 |
T11 |
1113 |
41 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
40035 |
0 |
0 |
T1 |
456209 |
9 |
0 |
0 |
T2 |
214009 |
353 |
0 |
0 |
T3 |
647398 |
336 |
0 |
0 |
T5 |
159525 |
3 |
0 |
0 |
T6 |
120763 |
361 |
0 |
0 |
T7 |
372831 |
35 |
0 |
0 |
T8 |
102445 |
3 |
0 |
0 |
T9 |
818929 |
6 |
0 |
0 |
T10 |
465140 |
9 |
0 |
0 |
T11 |
139237 |
41 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
39973 |
0 |
0 |
T1 |
456209 |
9 |
0 |
0 |
T2 |
214009 |
353 |
0 |
0 |
T3 |
647398 |
336 |
0 |
0 |
T5 |
159525 |
3 |
0 |
0 |
T6 |
120763 |
361 |
0 |
0 |
T7 |
372831 |
35 |
0 |
0 |
T8 |
102445 |
3 |
0 |
0 |
T9 |
818929 |
6 |
0 |
0 |
T10 |
465140 |
9 |
0 |
0 |
T11 |
139237 |
41 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
39989 |
0 |
0 |
T1 |
97062 |
9 |
0 |
0 |
T2 |
21399 |
353 |
0 |
0 |
T3 |
46241 |
336 |
0 |
0 |
T5 |
33582 |
3 |
0 |
0 |
T6 |
24395 |
361 |
0 |
0 |
T7 |
7686 |
35 |
0 |
0 |
T8 |
40976 |
3 |
0 |
0 |
T9 |
65513 |
6 |
0 |
0 |
T10 |
96906 |
9 |
0 |
0 |
T11 |
1113 |
41 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
18691 |
0 |
0 |
T1 |
97062 |
6 |
0 |
0 |
T2 |
21399 |
176 |
0 |
0 |
T3 |
46241 |
132 |
0 |
0 |
T5 |
33582 |
2 |
0 |
0 |
T6 |
24395 |
180 |
0 |
0 |
T7 |
7686 |
17 |
0 |
0 |
T8 |
40976 |
2 |
0 |
0 |
T9 |
65513 |
4 |
0 |
0 |
T10 |
96906 |
6 |
0 |
0 |
T11 |
1113 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
18840 |
0 |
0 |
T1 |
456209 |
6 |
0 |
0 |
T2 |
214009 |
176 |
0 |
0 |
T3 |
647398 |
132 |
0 |
0 |
T5 |
159525 |
2 |
0 |
0 |
T6 |
120763 |
180 |
0 |
0 |
T7 |
372831 |
17 |
0 |
0 |
T8 |
102445 |
2 |
0 |
0 |
T9 |
818929 |
4 |
0 |
0 |
T10 |
465140 |
6 |
0 |
0 |
T11 |
139237 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
18823 |
0 |
0 |
T1 |
456209 |
6 |
0 |
0 |
T2 |
214009 |
176 |
0 |
0 |
T3 |
647398 |
132 |
0 |
0 |
T5 |
159525 |
2 |
0 |
0 |
T6 |
120763 |
180 |
0 |
0 |
T7 |
372831 |
17 |
0 |
0 |
T8 |
102445 |
2 |
0 |
0 |
T9 |
818929 |
4 |
0 |
0 |
T10 |
465140 |
6 |
0 |
0 |
T11 |
139237 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
18823 |
0 |
0 |
T1 |
97062 |
6 |
0 |
0 |
T2 |
21399 |
176 |
0 |
0 |
T3 |
46241 |
132 |
0 |
0 |
T5 |
33582 |
2 |
0 |
0 |
T6 |
24395 |
180 |
0 |
0 |
T7 |
7686 |
17 |
0 |
0 |
T8 |
40976 |
2 |
0 |
0 |
T9 |
65513 |
4 |
0 |
0 |
T10 |
96906 |
6 |
0 |
0 |
T11 |
1113 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T4,T1,T2 |
1 | 0 | Covered | T4,T1,T2 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T4,T1,T2 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T1,T2 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
14747 |
0 |
0 |
T1 |
97062 |
3 |
0 |
0 |
T2 |
21399 |
176 |
0 |
0 |
T3 |
46241 |
127 |
0 |
0 |
T4 |
85 |
1 |
0 |
0 |
T5 |
33582 |
1 |
0 |
0 |
T6 |
24395 |
180 |
0 |
0 |
T7 |
7686 |
0 |
0 |
0 |
T8 |
40976 |
1 |
0 |
0 |
T9 |
65513 |
2 |
0 |
0 |
T10 |
96906 |
3 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
14942 |
0 |
0 |
T1 |
456209 |
3 |
0 |
0 |
T2 |
214009 |
176 |
0 |
0 |
T3 |
647398 |
127 |
0 |
0 |
T4 |
18953 |
1 |
0 |
0 |
T5 |
159525 |
1 |
0 |
0 |
T6 |
120763 |
180 |
0 |
0 |
T7 |
372831 |
0 |
0 |
0 |
T8 |
102445 |
1 |
0 |
0 |
T9 |
818929 |
2 |
0 |
0 |
T10 |
465140 |
3 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T4,T1,T2 |
1 | 0 | Covered | T4,T1,T2 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T4,T1,T2 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T1,T2 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
14902 |
0 |
0 |
T1 |
456209 |
3 |
0 |
0 |
T2 |
214009 |
176 |
0 |
0 |
T3 |
647398 |
127 |
0 |
0 |
T4 |
18953 |
1 |
0 |
0 |
T5 |
159525 |
1 |
0 |
0 |
T6 |
120763 |
180 |
0 |
0 |
T7 |
372831 |
0 |
0 |
0 |
T8 |
102445 |
1 |
0 |
0 |
T9 |
818929 |
2 |
0 |
0 |
T10 |
465140 |
3 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
14902 |
0 |
0 |
T1 |
97062 |
3 |
0 |
0 |
T2 |
21399 |
176 |
0 |
0 |
T3 |
46241 |
127 |
0 |
0 |
T4 |
85 |
1 |
0 |
0 |
T5 |
33582 |
1 |
0 |
0 |
T6 |
24395 |
180 |
0 |
0 |
T7 |
7686 |
0 |
0 |
0 |
T8 |
40976 |
1 |
0 |
0 |
T9 |
65513 |
2 |
0 |
0 |
T10 |
96906 |
3 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T4,T1,T2 |
1 | 0 | Covered | T4,T1,T2 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T4,T1,T2 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T1,T2 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
14741 |
0 |
0 |
T1 |
97062 |
3 |
0 |
0 |
T2 |
21399 |
176 |
0 |
0 |
T3 |
46241 |
127 |
0 |
0 |
T4 |
85 |
1 |
0 |
0 |
T5 |
33582 |
1 |
0 |
0 |
T6 |
24395 |
180 |
0 |
0 |
T7 |
7686 |
0 |
0 |
0 |
T8 |
40976 |
1 |
0 |
0 |
T9 |
65513 |
2 |
0 |
0 |
T10 |
96906 |
3 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
14933 |
0 |
0 |
T1 |
456209 |
3 |
0 |
0 |
T2 |
214009 |
176 |
0 |
0 |
T3 |
647398 |
127 |
0 |
0 |
T4 |
18953 |
1 |
0 |
0 |
T5 |
159525 |
1 |
0 |
0 |
T6 |
120763 |
180 |
0 |
0 |
T7 |
372831 |
0 |
0 |
0 |
T8 |
102445 |
1 |
0 |
0 |
T9 |
818929 |
2 |
0 |
0 |
T10 |
465140 |
3 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T4,T1,T2 |
1 | 0 | Covered | T4,T1,T2 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T4,T1,T2 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T1,T2 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
14892 |
0 |
0 |
T1 |
456209 |
3 |
0 |
0 |
T2 |
214009 |
176 |
0 |
0 |
T3 |
647398 |
127 |
0 |
0 |
T4 |
18953 |
1 |
0 |
0 |
T5 |
159525 |
1 |
0 |
0 |
T6 |
120763 |
180 |
0 |
0 |
T7 |
372831 |
0 |
0 |
0 |
T8 |
102445 |
1 |
0 |
0 |
T9 |
818929 |
2 |
0 |
0 |
T10 |
465140 |
3 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
14892 |
0 |
0 |
T1 |
97062 |
3 |
0 |
0 |
T2 |
21399 |
176 |
0 |
0 |
T3 |
46241 |
127 |
0 |
0 |
T4 |
85 |
1 |
0 |
0 |
T5 |
33582 |
1 |
0 |
0 |
T6 |
24395 |
180 |
0 |
0 |
T7 |
7686 |
0 |
0 |
0 |
T8 |
40976 |
1 |
0 |
0 |
T9 |
65513 |
2 |
0 |
0 |
T10 |
96906 |
3 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
20965 |
0 |
0 |
T1 |
97062 |
6 |
0 |
0 |
T2 |
21399 |
270 |
0 |
0 |
T3 |
46241 |
195 |
0 |
0 |
T5 |
33582 |
2 |
0 |
0 |
T6 |
24395 |
265 |
0 |
0 |
T7 |
7686 |
0 |
0 |
0 |
T8 |
40976 |
2 |
0 |
0 |
T9 |
65513 |
4 |
0 |
0 |
T10 |
96906 |
6 |
0 |
0 |
T11 |
1113 |
0 |
0 |
0 |
T12 |
0 |
6 |
0 |
0 |
T38 |
0 |
204 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
21111 |
0 |
0 |
T1 |
456209 |
6 |
0 |
0 |
T2 |
214009 |
270 |
0 |
0 |
T3 |
647398 |
195 |
0 |
0 |
T5 |
159525 |
2 |
0 |
0 |
T6 |
120763 |
265 |
0 |
0 |
T7 |
372831 |
0 |
0 |
0 |
T8 |
102445 |
2 |
0 |
0 |
T9 |
818929 |
4 |
0 |
0 |
T10 |
465140 |
6 |
0 |
0 |
T11 |
139237 |
0 |
0 |
0 |
T12 |
0 |
6 |
0 |
0 |
T38 |
0 |
204 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
21098 |
0 |
0 |
T1 |
456209 |
6 |
0 |
0 |
T2 |
214009 |
270 |
0 |
0 |
T3 |
647398 |
195 |
0 |
0 |
T5 |
159525 |
2 |
0 |
0 |
T6 |
120763 |
265 |
0 |
0 |
T7 |
372831 |
0 |
0 |
0 |
T8 |
102445 |
2 |
0 |
0 |
T9 |
818929 |
4 |
0 |
0 |
T10 |
465140 |
6 |
0 |
0 |
T11 |
139237 |
0 |
0 |
0 |
T12 |
0 |
6 |
0 |
0 |
T38 |
0 |
204 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
21098 |
0 |
0 |
T1 |
97062 |
6 |
0 |
0 |
T2 |
21399 |
270 |
0 |
0 |
T3 |
46241 |
195 |
0 |
0 |
T5 |
33582 |
2 |
0 |
0 |
T6 |
24395 |
265 |
0 |
0 |
T7 |
7686 |
0 |
0 |
0 |
T8 |
40976 |
2 |
0 |
0 |
T9 |
65513 |
4 |
0 |
0 |
T10 |
96906 |
6 |
0 |
0 |
T11 |
1113 |
0 |
0 |
0 |
T12 |
0 |
6 |
0 |
0 |
T38 |
0 |
204 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T9,T10 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T9,T10 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
1907 |
0 |
0 |
T1 |
97062 |
3 |
0 |
0 |
T2 |
21399 |
1 |
0 |
0 |
T3 |
46241 |
4 |
0 |
0 |
T5 |
33582 |
1 |
0 |
0 |
T6 |
24395 |
1 |
0 |
0 |
T7 |
7686 |
0 |
0 |
0 |
T8 |
40976 |
1 |
0 |
0 |
T9 |
65513 |
2 |
0 |
0 |
T10 |
96906 |
3 |
0 |
0 |
T11 |
1113 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2050 |
0 |
0 |
T1 |
456209 |
3 |
0 |
0 |
T2 |
214009 |
1 |
0 |
0 |
T3 |
647398 |
4 |
0 |
0 |
T5 |
159525 |
1 |
0 |
0 |
T6 |
120763 |
1 |
0 |
0 |
T7 |
372831 |
0 |
0 |
0 |
T8 |
102445 |
1 |
0 |
0 |
T9 |
818929 |
2 |
0 |
0 |
T10 |
465140 |
3 |
0 |
0 |
T11 |
139237 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T9,T10 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T9,T10 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2034 |
0 |
0 |
T1 |
456209 |
3 |
0 |
0 |
T2 |
214009 |
1 |
0 |
0 |
T3 |
647398 |
4 |
0 |
0 |
T5 |
159525 |
1 |
0 |
0 |
T6 |
120763 |
1 |
0 |
0 |
T7 |
372831 |
0 |
0 |
0 |
T8 |
102445 |
1 |
0 |
0 |
T9 |
818929 |
2 |
0 |
0 |
T10 |
465140 |
3 |
0 |
0 |
T11 |
139237 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
2034 |
0 |
0 |
T1 |
97062 |
3 |
0 |
0 |
T2 |
21399 |
1 |
0 |
0 |
T3 |
46241 |
4 |
0 |
0 |
T5 |
33582 |
1 |
0 |
0 |
T6 |
24395 |
1 |
0 |
0 |
T7 |
7686 |
0 |
0 |
0 |
T8 |
40976 |
1 |
0 |
0 |
T9 |
65513 |
2 |
0 |
0 |
T10 |
96906 |
3 |
0 |
0 |
T11 |
1113 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T1,T9,T10 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T9,T10 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
1798 |
0 |
0 |
T1 |
97062 |
3 |
0 |
0 |
T2 |
21399 |
0 |
0 |
0 |
T3 |
46241 |
3 |
0 |
0 |
T5 |
33582 |
1 |
0 |
0 |
T6 |
24395 |
0 |
0 |
0 |
T7 |
7686 |
0 |
0 |
0 |
T8 |
40976 |
1 |
0 |
0 |
T9 |
65513 |
2 |
0 |
0 |
T10 |
96906 |
3 |
0 |
0 |
T11 |
1113 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1939 |
0 |
0 |
T1 |
456209 |
3 |
0 |
0 |
T2 |
214009 |
0 |
0 |
0 |
T3 |
647398 |
3 |
0 |
0 |
T5 |
159525 |
1 |
0 |
0 |
T6 |
120763 |
0 |
0 |
0 |
T7 |
372831 |
0 |
0 |
0 |
T8 |
102445 |
1 |
0 |
0 |
T9 |
818929 |
2 |
0 |
0 |
T10 |
465140 |
3 |
0 |
0 |
T11 |
139237 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T1,T9,T10 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T9,T10 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1924 |
0 |
0 |
T1 |
456209 |
3 |
0 |
0 |
T2 |
214009 |
0 |
0 |
0 |
T3 |
647398 |
3 |
0 |
0 |
T5 |
159525 |
1 |
0 |
0 |
T6 |
120763 |
0 |
0 |
0 |
T7 |
372831 |
0 |
0 |
0 |
T8 |
102445 |
1 |
0 |
0 |
T9 |
818929 |
2 |
0 |
0 |
T10 |
465140 |
3 |
0 |
0 |
T11 |
139237 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
1924 |
0 |
0 |
T1 |
97062 |
3 |
0 |
0 |
T2 |
21399 |
0 |
0 |
0 |
T3 |
46241 |
3 |
0 |
0 |
T5 |
33582 |
1 |
0 |
0 |
T6 |
24395 |
0 |
0 |
0 |
T7 |
7686 |
0 |
0 |
0 |
T8 |
40976 |
1 |
0 |
0 |
T9 |
65513 |
2 |
0 |
0 |
T10 |
96906 |
3 |
0 |
0 |
T11 |
1113 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T1,T9,T10 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T9,T10 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
1781 |
0 |
0 |
T1 |
97062 |
3 |
0 |
0 |
T2 |
21399 |
0 |
0 |
0 |
T3 |
46241 |
3 |
0 |
0 |
T5 |
33582 |
1 |
0 |
0 |
T6 |
24395 |
0 |
0 |
0 |
T7 |
7686 |
0 |
0 |
0 |
T8 |
40976 |
1 |
0 |
0 |
T9 |
65513 |
2 |
0 |
0 |
T10 |
96906 |
3 |
0 |
0 |
T11 |
1113 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1915 |
0 |
0 |
T1 |
456209 |
3 |
0 |
0 |
T2 |
214009 |
0 |
0 |
0 |
T3 |
647398 |
3 |
0 |
0 |
T5 |
159525 |
1 |
0 |
0 |
T6 |
120763 |
0 |
0 |
0 |
T7 |
372831 |
0 |
0 |
0 |
T8 |
102445 |
1 |
0 |
0 |
T9 |
818929 |
2 |
0 |
0 |
T10 |
465140 |
3 |
0 |
0 |
T11 |
139237 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T1,T9,T10 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T9,T10 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1902 |
0 |
0 |
T1 |
456209 |
3 |
0 |
0 |
T2 |
214009 |
0 |
0 |
0 |
T3 |
647398 |
3 |
0 |
0 |
T5 |
159525 |
1 |
0 |
0 |
T6 |
120763 |
0 |
0 |
0 |
T7 |
372831 |
0 |
0 |
0 |
T8 |
102445 |
1 |
0 |
0 |
T9 |
818929 |
2 |
0 |
0 |
T10 |
465140 |
3 |
0 |
0 |
T11 |
139237 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
1902 |
0 |
0 |
T1 |
97062 |
3 |
0 |
0 |
T2 |
21399 |
0 |
0 |
0 |
T3 |
46241 |
3 |
0 |
0 |
T5 |
33582 |
1 |
0 |
0 |
T6 |
24395 |
0 |
0 |
0 |
T7 |
7686 |
0 |
0 |
0 |
T8 |
40976 |
1 |
0 |
0 |
T9 |
65513 |
2 |
0 |
0 |
T10 |
96906 |
3 |
0 |
0 |
T11 |
1113 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T1,T9,T10 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T9,T10 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
1807 |
0 |
0 |
T1 |
97062 |
3 |
0 |
0 |
T2 |
21399 |
0 |
0 |
0 |
T3 |
46241 |
3 |
0 |
0 |
T5 |
33582 |
1 |
0 |
0 |
T6 |
24395 |
0 |
0 |
0 |
T7 |
7686 |
0 |
0 |
0 |
T8 |
40976 |
1 |
0 |
0 |
T9 |
65513 |
2 |
0 |
0 |
T10 |
96906 |
3 |
0 |
0 |
T11 |
1113 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1940 |
0 |
0 |
T1 |
456209 |
3 |
0 |
0 |
T2 |
214009 |
0 |
0 |
0 |
T3 |
647398 |
3 |
0 |
0 |
T5 |
159525 |
1 |
0 |
0 |
T6 |
120763 |
0 |
0 |
0 |
T7 |
372831 |
0 |
0 |
0 |
T8 |
102445 |
1 |
0 |
0 |
T9 |
818929 |
2 |
0 |
0 |
T10 |
465140 |
3 |
0 |
0 |
T11 |
139237 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T1,T9,T10 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T9,T10 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1925 |
0 |
0 |
T1 |
456209 |
3 |
0 |
0 |
T2 |
214009 |
0 |
0 |
0 |
T3 |
647398 |
3 |
0 |
0 |
T5 |
159525 |
1 |
0 |
0 |
T6 |
120763 |
0 |
0 |
0 |
T7 |
372831 |
0 |
0 |
0 |
T8 |
102445 |
1 |
0 |
0 |
T9 |
818929 |
2 |
0 |
0 |
T10 |
465140 |
3 |
0 |
0 |
T11 |
139237 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
1925 |
0 |
0 |
T1 |
97062 |
3 |
0 |
0 |
T2 |
21399 |
0 |
0 |
0 |
T3 |
46241 |
3 |
0 |
0 |
T5 |
33582 |
1 |
0 |
0 |
T6 |
24395 |
0 |
0 |
0 |
T7 |
7686 |
0 |
0 |
0 |
T8 |
40976 |
1 |
0 |
0 |
T9 |
65513 |
2 |
0 |
0 |
T10 |
96906 |
3 |
0 |
0 |
T11 |
1113 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T1,T9,T10 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T9,T10 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
1774 |
0 |
0 |
T1 |
97062 |
3 |
0 |
0 |
T2 |
21399 |
0 |
0 |
0 |
T3 |
46241 |
3 |
0 |
0 |
T5 |
33582 |
1 |
0 |
0 |
T6 |
24395 |
0 |
0 |
0 |
T7 |
7686 |
0 |
0 |
0 |
T8 |
40976 |
1 |
0 |
0 |
T9 |
65513 |
2 |
0 |
0 |
T10 |
96906 |
3 |
0 |
0 |
T11 |
1113 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1918 |
0 |
0 |
T1 |
456209 |
3 |
0 |
0 |
T2 |
214009 |
0 |
0 |
0 |
T3 |
647398 |
3 |
0 |
0 |
T5 |
159525 |
1 |
0 |
0 |
T6 |
120763 |
0 |
0 |
0 |
T7 |
372831 |
0 |
0 |
0 |
T8 |
102445 |
1 |
0 |
0 |
T9 |
818929 |
2 |
0 |
0 |
T10 |
465140 |
3 |
0 |
0 |
T11 |
139237 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T1,T9,T10 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T9,T10 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1906 |
0 |
0 |
T1 |
456209 |
3 |
0 |
0 |
T2 |
214009 |
0 |
0 |
0 |
T3 |
647398 |
3 |
0 |
0 |
T5 |
159525 |
1 |
0 |
0 |
T6 |
120763 |
0 |
0 |
0 |
T7 |
372831 |
0 |
0 |
0 |
T8 |
102445 |
1 |
0 |
0 |
T9 |
818929 |
2 |
0 |
0 |
T10 |
465140 |
3 |
0 |
0 |
T11 |
139237 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
1906 |
0 |
0 |
T1 |
97062 |
3 |
0 |
0 |
T2 |
21399 |
0 |
0 |
0 |
T3 |
46241 |
3 |
0 |
0 |
T5 |
33582 |
1 |
0 |
0 |
T6 |
24395 |
0 |
0 |
0 |
T7 |
7686 |
0 |
0 |
0 |
T8 |
40976 |
1 |
0 |
0 |
T9 |
65513 |
2 |
0 |
0 |
T10 |
96906 |
3 |
0 |
0 |
T11 |
1113 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T1,T9,T10 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T9,T10 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
1744 |
0 |
0 |
T1 |
97062 |
3 |
0 |
0 |
T2 |
21399 |
0 |
0 |
0 |
T3 |
46241 |
3 |
0 |
0 |
T5 |
33582 |
1 |
0 |
0 |
T6 |
24395 |
0 |
0 |
0 |
T7 |
7686 |
0 |
0 |
0 |
T8 |
40976 |
1 |
0 |
0 |
T9 |
65513 |
2 |
0 |
0 |
T10 |
96906 |
3 |
0 |
0 |
T11 |
1113 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1886 |
0 |
0 |
T1 |
456209 |
3 |
0 |
0 |
T2 |
214009 |
0 |
0 |
0 |
T3 |
647398 |
3 |
0 |
0 |
T5 |
159525 |
1 |
0 |
0 |
T6 |
120763 |
0 |
0 |
0 |
T7 |
372831 |
0 |
0 |
0 |
T8 |
102445 |
1 |
0 |
0 |
T9 |
818929 |
2 |
0 |
0 |
T10 |
465140 |
3 |
0 |
0 |
T11 |
139237 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T1,T9,T10 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T9,T10 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1875 |
0 |
0 |
T1 |
456209 |
3 |
0 |
0 |
T2 |
214009 |
0 |
0 |
0 |
T3 |
647398 |
3 |
0 |
0 |
T5 |
159525 |
1 |
0 |
0 |
T6 |
120763 |
0 |
0 |
0 |
T7 |
372831 |
0 |
0 |
0 |
T8 |
102445 |
1 |
0 |
0 |
T9 |
818929 |
2 |
0 |
0 |
T10 |
465140 |
3 |
0 |
0 |
T11 |
139237 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
1875 |
0 |
0 |
T1 |
97062 |
3 |
0 |
0 |
T2 |
21399 |
0 |
0 |
0 |
T3 |
46241 |
3 |
0 |
0 |
T5 |
33582 |
1 |
0 |
0 |
T6 |
24395 |
0 |
0 |
0 |
T7 |
7686 |
0 |
0 |
0 |
T8 |
40976 |
1 |
0 |
0 |
T9 |
65513 |
2 |
0 |
0 |
T10 |
96906 |
3 |
0 |
0 |
T11 |
1113 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T1,T9,T10 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T9,T10 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
1766 |
0 |
0 |
T1 |
97062 |
3 |
0 |
0 |
T2 |
21399 |
0 |
0 |
0 |
T3 |
46241 |
3 |
0 |
0 |
T5 |
33582 |
1 |
0 |
0 |
T6 |
24395 |
0 |
0 |
0 |
T7 |
7686 |
0 |
0 |
0 |
T8 |
40976 |
1 |
0 |
0 |
T9 |
65513 |
2 |
0 |
0 |
T10 |
96906 |
3 |
0 |
0 |
T11 |
1113 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1906 |
0 |
0 |
T1 |
456209 |
3 |
0 |
0 |
T2 |
214009 |
0 |
0 |
0 |
T3 |
647398 |
3 |
0 |
0 |
T5 |
159525 |
1 |
0 |
0 |
T6 |
120763 |
0 |
0 |
0 |
T7 |
372831 |
0 |
0 |
0 |
T8 |
102445 |
1 |
0 |
0 |
T9 |
818929 |
2 |
0 |
0 |
T10 |
465140 |
3 |
0 |
0 |
T11 |
139237 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T1,T9,T10 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T9,T10 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1892 |
0 |
0 |
T1 |
456209 |
3 |
0 |
0 |
T2 |
214009 |
0 |
0 |
0 |
T3 |
647398 |
3 |
0 |
0 |
T5 |
159525 |
1 |
0 |
0 |
T6 |
120763 |
0 |
0 |
0 |
T7 |
372831 |
0 |
0 |
0 |
T8 |
102445 |
1 |
0 |
0 |
T9 |
818929 |
2 |
0 |
0 |
T10 |
465140 |
3 |
0 |
0 |
T11 |
139237 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
1892 |
0 |
0 |
T1 |
97062 |
3 |
0 |
0 |
T2 |
21399 |
0 |
0 |
0 |
T3 |
46241 |
3 |
0 |
0 |
T5 |
33582 |
1 |
0 |
0 |
T6 |
24395 |
0 |
0 |
0 |
T7 |
7686 |
0 |
0 |
0 |
T8 |
40976 |
1 |
0 |
0 |
T9 |
65513 |
2 |
0 |
0 |
T10 |
96906 |
3 |
0 |
0 |
T11 |
1113 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T1,T9,T10 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T9,T10 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
1749 |
0 |
0 |
T1 |
97062 |
3 |
0 |
0 |
T2 |
21399 |
0 |
0 |
0 |
T3 |
46241 |
3 |
0 |
0 |
T5 |
33582 |
1 |
0 |
0 |
T6 |
24395 |
0 |
0 |
0 |
T7 |
7686 |
0 |
0 |
0 |
T8 |
40976 |
1 |
0 |
0 |
T9 |
65513 |
2 |
0 |
0 |
T10 |
96906 |
3 |
0 |
0 |
T11 |
1113 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1892 |
0 |
0 |
T1 |
456209 |
3 |
0 |
0 |
T2 |
214009 |
0 |
0 |
0 |
T3 |
647398 |
3 |
0 |
0 |
T5 |
159525 |
1 |
0 |
0 |
T6 |
120763 |
0 |
0 |
0 |
T7 |
372831 |
0 |
0 |
0 |
T8 |
102445 |
1 |
0 |
0 |
T9 |
818929 |
2 |
0 |
0 |
T10 |
465140 |
3 |
0 |
0 |
T11 |
139237 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T1,T9,T10 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T9,T10 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1877 |
0 |
0 |
T1 |
456209 |
3 |
0 |
0 |
T2 |
214009 |
0 |
0 |
0 |
T3 |
647398 |
3 |
0 |
0 |
T5 |
159525 |
1 |
0 |
0 |
T6 |
120763 |
0 |
0 |
0 |
T7 |
372831 |
0 |
0 |
0 |
T8 |
102445 |
1 |
0 |
0 |
T9 |
818929 |
2 |
0 |
0 |
T10 |
465140 |
3 |
0 |
0 |
T11 |
139237 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
1877 |
0 |
0 |
T1 |
97062 |
3 |
0 |
0 |
T2 |
21399 |
0 |
0 |
0 |
T3 |
46241 |
3 |
0 |
0 |
T5 |
33582 |
1 |
0 |
0 |
T6 |
24395 |
0 |
0 |
0 |
T7 |
7686 |
0 |
0 |
0 |
T8 |
40976 |
1 |
0 |
0 |
T9 |
65513 |
2 |
0 |
0 |
T10 |
96906 |
3 |
0 |
0 |
T11 |
1113 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T9,T10 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T9,T10 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
1917 |
0 |
0 |
T1 |
97062 |
3 |
0 |
0 |
T2 |
21399 |
1 |
0 |
0 |
T3 |
46241 |
4 |
0 |
0 |
T5 |
33582 |
1 |
0 |
0 |
T6 |
24395 |
1 |
0 |
0 |
T7 |
7686 |
0 |
0 |
0 |
T8 |
40976 |
1 |
0 |
0 |
T9 |
65513 |
2 |
0 |
0 |
T10 |
96906 |
3 |
0 |
0 |
T11 |
1113 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2063 |
0 |
0 |
T1 |
456209 |
3 |
0 |
0 |
T2 |
214009 |
1 |
0 |
0 |
T3 |
647398 |
4 |
0 |
0 |
T5 |
159525 |
1 |
0 |
0 |
T6 |
120763 |
1 |
0 |
0 |
T7 |
372831 |
0 |
0 |
0 |
T8 |
102445 |
1 |
0 |
0 |
T9 |
818929 |
2 |
0 |
0 |
T10 |
465140 |
3 |
0 |
0 |
T11 |
139237 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T9,T10 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T9,T10 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2048 |
0 |
0 |
T1 |
456209 |
3 |
0 |
0 |
T2 |
214009 |
1 |
0 |
0 |
T3 |
647398 |
4 |
0 |
0 |
T5 |
159525 |
1 |
0 |
0 |
T6 |
120763 |
1 |
0 |
0 |
T7 |
372831 |
0 |
0 |
0 |
T8 |
102445 |
1 |
0 |
0 |
T9 |
818929 |
2 |
0 |
0 |
T10 |
465140 |
3 |
0 |
0 |
T11 |
139237 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
2048 |
0 |
0 |
T1 |
97062 |
3 |
0 |
0 |
T2 |
21399 |
1 |
0 |
0 |
T3 |
46241 |
4 |
0 |
0 |
T5 |
33582 |
1 |
0 |
0 |
T6 |
24395 |
1 |
0 |
0 |
T7 |
7686 |
0 |
0 |
0 |
T8 |
40976 |
1 |
0 |
0 |
T9 |
65513 |
2 |
0 |
0 |
T10 |
96906 |
3 |
0 |
0 |
T11 |
1113 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T1,T9,T10 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T9,T10 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
1783 |
0 |
0 |
T1 |
97062 |
3 |
0 |
0 |
T2 |
21399 |
0 |
0 |
0 |
T3 |
46241 |
3 |
0 |
0 |
T5 |
33582 |
1 |
0 |
0 |
T6 |
24395 |
0 |
0 |
0 |
T7 |
7686 |
0 |
0 |
0 |
T8 |
40976 |
1 |
0 |
0 |
T9 |
65513 |
2 |
0 |
0 |
T10 |
96906 |
3 |
0 |
0 |
T11 |
1113 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1927 |
0 |
0 |
T1 |
456209 |
3 |
0 |
0 |
T2 |
214009 |
0 |
0 |
0 |
T3 |
647398 |
3 |
0 |
0 |
T5 |
159525 |
1 |
0 |
0 |
T6 |
120763 |
0 |
0 |
0 |
T7 |
372831 |
0 |
0 |
0 |
T8 |
102445 |
1 |
0 |
0 |
T9 |
818929 |
2 |
0 |
0 |
T10 |
465140 |
3 |
0 |
0 |
T11 |
139237 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T1,T9,T10 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T9,T10 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1914 |
0 |
0 |
T1 |
456209 |
3 |
0 |
0 |
T2 |
214009 |
0 |
0 |
0 |
T3 |
647398 |
3 |
0 |
0 |
T5 |
159525 |
1 |
0 |
0 |
T6 |
120763 |
0 |
0 |
0 |
T7 |
372831 |
0 |
0 |
0 |
T8 |
102445 |
1 |
0 |
0 |
T9 |
818929 |
2 |
0 |
0 |
T10 |
465140 |
3 |
0 |
0 |
T11 |
139237 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
1914 |
0 |
0 |
T1 |
97062 |
3 |
0 |
0 |
T2 |
21399 |
0 |
0 |
0 |
T3 |
46241 |
3 |
0 |
0 |
T5 |
33582 |
1 |
0 |
0 |
T6 |
24395 |
0 |
0 |
0 |
T7 |
7686 |
0 |
0 |
0 |
T8 |
40976 |
1 |
0 |
0 |
T9 |
65513 |
2 |
0 |
0 |
T10 |
96906 |
3 |
0 |
0 |
T11 |
1113 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T1,T9,T10 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T9,T10 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
1808 |
0 |
0 |
T1 |
97062 |
3 |
0 |
0 |
T2 |
21399 |
0 |
0 |
0 |
T3 |
46241 |
3 |
0 |
0 |
T5 |
33582 |
1 |
0 |
0 |
T6 |
24395 |
0 |
0 |
0 |
T7 |
7686 |
0 |
0 |
0 |
T8 |
40976 |
1 |
0 |
0 |
T9 |
65513 |
2 |
0 |
0 |
T10 |
96906 |
3 |
0 |
0 |
T11 |
1113 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1948 |
0 |
0 |
T1 |
456209 |
3 |
0 |
0 |
T2 |
214009 |
0 |
0 |
0 |
T3 |
647398 |
3 |
0 |
0 |
T5 |
159525 |
1 |
0 |
0 |
T6 |
120763 |
0 |
0 |
0 |
T7 |
372831 |
0 |
0 |
0 |
T8 |
102445 |
1 |
0 |
0 |
T9 |
818929 |
2 |
0 |
0 |
T10 |
465140 |
3 |
0 |
0 |
T11 |
139237 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T1,T9,T10 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T9,T10 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1934 |
0 |
0 |
T1 |
456209 |
3 |
0 |
0 |
T2 |
214009 |
0 |
0 |
0 |
T3 |
647398 |
3 |
0 |
0 |
T5 |
159525 |
1 |
0 |
0 |
T6 |
120763 |
0 |
0 |
0 |
T7 |
372831 |
0 |
0 |
0 |
T8 |
102445 |
1 |
0 |
0 |
T9 |
818929 |
2 |
0 |
0 |
T10 |
465140 |
3 |
0 |
0 |
T11 |
139237 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
1934 |
0 |
0 |
T1 |
97062 |
3 |
0 |
0 |
T2 |
21399 |
0 |
0 |
0 |
T3 |
46241 |
3 |
0 |
0 |
T5 |
33582 |
1 |
0 |
0 |
T6 |
24395 |
0 |
0 |
0 |
T7 |
7686 |
0 |
0 |
0 |
T8 |
40976 |
1 |
0 |
0 |
T9 |
65513 |
2 |
0 |
0 |
T10 |
96906 |
3 |
0 |
0 |
T11 |
1113 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T1,T9,T10 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T9,T10 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
1816 |
0 |
0 |
T1 |
97062 |
3 |
0 |
0 |
T2 |
21399 |
0 |
0 |
0 |
T3 |
46241 |
3 |
0 |
0 |
T5 |
33582 |
1 |
0 |
0 |
T6 |
24395 |
0 |
0 |
0 |
T7 |
7686 |
0 |
0 |
0 |
T8 |
40976 |
1 |
0 |
0 |
T9 |
65513 |
2 |
0 |
0 |
T10 |
96906 |
3 |
0 |
0 |
T11 |
1113 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1960 |
0 |
0 |
T1 |
456209 |
3 |
0 |
0 |
T2 |
214009 |
0 |
0 |
0 |
T3 |
647398 |
3 |
0 |
0 |
T5 |
159525 |
1 |
0 |
0 |
T6 |
120763 |
0 |
0 |
0 |
T7 |
372831 |
0 |
0 |
0 |
T8 |
102445 |
1 |
0 |
0 |
T9 |
818929 |
2 |
0 |
0 |
T10 |
465140 |
3 |
0 |
0 |
T11 |
139237 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T1,T9,T10 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T9,T10 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1946 |
0 |
0 |
T1 |
456209 |
3 |
0 |
0 |
T2 |
214009 |
0 |
0 |
0 |
T3 |
647398 |
3 |
0 |
0 |
T5 |
159525 |
1 |
0 |
0 |
T6 |
120763 |
0 |
0 |
0 |
T7 |
372831 |
0 |
0 |
0 |
T8 |
102445 |
1 |
0 |
0 |
T9 |
818929 |
2 |
0 |
0 |
T10 |
465140 |
3 |
0 |
0 |
T11 |
139237 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
1946 |
0 |
0 |
T1 |
97062 |
3 |
0 |
0 |
T2 |
21399 |
0 |
0 |
0 |
T3 |
46241 |
3 |
0 |
0 |
T5 |
33582 |
1 |
0 |
0 |
T6 |
24395 |
0 |
0 |
0 |
T7 |
7686 |
0 |
0 |
0 |
T8 |
40976 |
1 |
0 |
0 |
T9 |
65513 |
2 |
0 |
0 |
T10 |
96906 |
3 |
0 |
0 |
T11 |
1113 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T1,T9,T10 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T9,T10 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
1776 |
0 |
0 |
T1 |
97062 |
3 |
0 |
0 |
T2 |
21399 |
0 |
0 |
0 |
T3 |
46241 |
3 |
0 |
0 |
T5 |
33582 |
1 |
0 |
0 |
T6 |
24395 |
0 |
0 |
0 |
T7 |
7686 |
0 |
0 |
0 |
T8 |
40976 |
1 |
0 |
0 |
T9 |
65513 |
2 |
0 |
0 |
T10 |
96906 |
3 |
0 |
0 |
T11 |
1113 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1917 |
0 |
0 |
T1 |
456209 |
3 |
0 |
0 |
T2 |
214009 |
0 |
0 |
0 |
T3 |
647398 |
3 |
0 |
0 |
T5 |
159525 |
1 |
0 |
0 |
T6 |
120763 |
0 |
0 |
0 |
T7 |
372831 |
0 |
0 |
0 |
T8 |
102445 |
1 |
0 |
0 |
T9 |
818929 |
2 |
0 |
0 |
T10 |
465140 |
3 |
0 |
0 |
T11 |
139237 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T1,T9,T10 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T9,T10 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1904 |
0 |
0 |
T1 |
456209 |
3 |
0 |
0 |
T2 |
214009 |
0 |
0 |
0 |
T3 |
647398 |
3 |
0 |
0 |
T5 |
159525 |
1 |
0 |
0 |
T6 |
120763 |
0 |
0 |
0 |
T7 |
372831 |
0 |
0 |
0 |
T8 |
102445 |
1 |
0 |
0 |
T9 |
818929 |
2 |
0 |
0 |
T10 |
465140 |
3 |
0 |
0 |
T11 |
139237 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
1904 |
0 |
0 |
T1 |
97062 |
3 |
0 |
0 |
T2 |
21399 |
0 |
0 |
0 |
T3 |
46241 |
3 |
0 |
0 |
T5 |
33582 |
1 |
0 |
0 |
T6 |
24395 |
0 |
0 |
0 |
T7 |
7686 |
0 |
0 |
0 |
T8 |
40976 |
1 |
0 |
0 |
T9 |
65513 |
2 |
0 |
0 |
T10 |
96906 |
3 |
0 |
0 |
T11 |
1113 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T1,T9,T10 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T9,T10 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
1794 |
0 |
0 |
T1 |
97062 |
3 |
0 |
0 |
T2 |
21399 |
0 |
0 |
0 |
T3 |
46241 |
3 |
0 |
0 |
T5 |
33582 |
1 |
0 |
0 |
T6 |
24395 |
0 |
0 |
0 |
T7 |
7686 |
0 |
0 |
0 |
T8 |
40976 |
1 |
0 |
0 |
T9 |
65513 |
2 |
0 |
0 |
T10 |
96906 |
3 |
0 |
0 |
T11 |
1113 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1935 |
0 |
0 |
T1 |
456209 |
3 |
0 |
0 |
T2 |
214009 |
0 |
0 |
0 |
T3 |
647398 |
3 |
0 |
0 |
T5 |
159525 |
1 |
0 |
0 |
T6 |
120763 |
0 |
0 |
0 |
T7 |
372831 |
0 |
0 |
0 |
T8 |
102445 |
1 |
0 |
0 |
T9 |
818929 |
2 |
0 |
0 |
T10 |
465140 |
3 |
0 |
0 |
T11 |
139237 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T1,T9,T10 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T9,T10 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1923 |
0 |
0 |
T1 |
456209 |
3 |
0 |
0 |
T2 |
214009 |
0 |
0 |
0 |
T3 |
647398 |
3 |
0 |
0 |
T5 |
159525 |
1 |
0 |
0 |
T6 |
120763 |
0 |
0 |
0 |
T7 |
372831 |
0 |
0 |
0 |
T8 |
102445 |
1 |
0 |
0 |
T9 |
818929 |
2 |
0 |
0 |
T10 |
465140 |
3 |
0 |
0 |
T11 |
139237 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
1923 |
0 |
0 |
T1 |
97062 |
3 |
0 |
0 |
T2 |
21399 |
0 |
0 |
0 |
T3 |
46241 |
3 |
0 |
0 |
T5 |
33582 |
1 |
0 |
0 |
T6 |
24395 |
0 |
0 |
0 |
T7 |
7686 |
0 |
0 |
0 |
T8 |
40976 |
1 |
0 |
0 |
T9 |
65513 |
2 |
0 |
0 |
T10 |
96906 |
3 |
0 |
0 |
T11 |
1113 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T1,T9,T10 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T9,T10 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
1771 |
0 |
0 |
T1 |
97062 |
3 |
0 |
0 |
T2 |
21399 |
0 |
0 |
0 |
T3 |
46241 |
3 |
0 |
0 |
T5 |
33582 |
1 |
0 |
0 |
T6 |
24395 |
0 |
0 |
0 |
T7 |
7686 |
0 |
0 |
0 |
T8 |
40976 |
1 |
0 |
0 |
T9 |
65513 |
2 |
0 |
0 |
T10 |
96906 |
3 |
0 |
0 |
T11 |
1113 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1907 |
0 |
0 |
T1 |
456209 |
3 |
0 |
0 |
T2 |
214009 |
0 |
0 |
0 |
T3 |
647398 |
3 |
0 |
0 |
T5 |
159525 |
1 |
0 |
0 |
T6 |
120763 |
0 |
0 |
0 |
T7 |
372831 |
0 |
0 |
0 |
T8 |
102445 |
1 |
0 |
0 |
T9 |
818929 |
2 |
0 |
0 |
T10 |
465140 |
3 |
0 |
0 |
T11 |
139237 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T1,T9,T10 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T9,T10 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1893 |
0 |
0 |
T1 |
456209 |
3 |
0 |
0 |
T2 |
214009 |
0 |
0 |
0 |
T3 |
647398 |
3 |
0 |
0 |
T5 |
159525 |
1 |
0 |
0 |
T6 |
120763 |
0 |
0 |
0 |
T7 |
372831 |
0 |
0 |
0 |
T8 |
102445 |
1 |
0 |
0 |
T9 |
818929 |
2 |
0 |
0 |
T10 |
465140 |
3 |
0 |
0 |
T11 |
139237 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
1893 |
0 |
0 |
T1 |
97062 |
3 |
0 |
0 |
T2 |
21399 |
0 |
0 |
0 |
T3 |
46241 |
3 |
0 |
0 |
T5 |
33582 |
1 |
0 |
0 |
T6 |
24395 |
0 |
0 |
0 |
T7 |
7686 |
0 |
0 |
0 |
T8 |
40976 |
1 |
0 |
0 |
T9 |
65513 |
2 |
0 |
0 |
T10 |
96906 |
3 |
0 |
0 |
T11 |
1113 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T1,T9,T10 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T9,T10 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
1774 |
0 |
0 |
T1 |
97062 |
3 |
0 |
0 |
T2 |
21399 |
0 |
0 |
0 |
T3 |
46241 |
3 |
0 |
0 |
T5 |
33582 |
1 |
0 |
0 |
T6 |
24395 |
0 |
0 |
0 |
T7 |
7686 |
0 |
0 |
0 |
T8 |
40976 |
1 |
0 |
0 |
T9 |
65513 |
2 |
0 |
0 |
T10 |
96906 |
3 |
0 |
0 |
T11 |
1113 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1916 |
0 |
0 |
T1 |
456209 |
3 |
0 |
0 |
T2 |
214009 |
0 |
0 |
0 |
T3 |
647398 |
3 |
0 |
0 |
T5 |
159525 |
1 |
0 |
0 |
T6 |
120763 |
0 |
0 |
0 |
T7 |
372831 |
0 |
0 |
0 |
T8 |
102445 |
1 |
0 |
0 |
T9 |
818929 |
2 |
0 |
0 |
T10 |
465140 |
3 |
0 |
0 |
T11 |
139237 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T1,T9,T10 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T9,T10 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1903 |
0 |
0 |
T1 |
456209 |
3 |
0 |
0 |
T2 |
214009 |
0 |
0 |
0 |
T3 |
647398 |
3 |
0 |
0 |
T5 |
159525 |
1 |
0 |
0 |
T6 |
120763 |
0 |
0 |
0 |
T7 |
372831 |
0 |
0 |
0 |
T8 |
102445 |
1 |
0 |
0 |
T9 |
818929 |
2 |
0 |
0 |
T10 |
465140 |
3 |
0 |
0 |
T11 |
139237 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
1903 |
0 |
0 |
T1 |
97062 |
3 |
0 |
0 |
T2 |
21399 |
0 |
0 |
0 |
T3 |
46241 |
3 |
0 |
0 |
T5 |
33582 |
1 |
0 |
0 |
T6 |
24395 |
0 |
0 |
0 |
T7 |
7686 |
0 |
0 |
0 |
T8 |
40976 |
1 |
0 |
0 |
T9 |
65513 |
2 |
0 |
0 |
T10 |
96906 |
3 |
0 |
0 |
T11 |
1113 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T8,T39,T40 |
1 | 0 | Covered | T8,T39,T40 |
1 | 1 | Covered | T39,T40,T46 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T8,T39,T40 |
1 | 0 | Covered | T39,T40,T46 |
1 | 1 | Covered | T8,T39,T40 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
1199 |
0 |
0 |
T8 |
40976 |
1 |
0 |
0 |
T9 |
65513 |
0 |
0 |
0 |
T10 |
96906 |
0 |
0 |
0 |
T11 |
1113 |
0 |
0 |
0 |
T12 |
98911 |
0 |
0 |
0 |
T13 |
99881 |
0 |
0 |
0 |
T14 |
19889 |
0 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
T31 |
0 |
2 |
0 |
0 |
T33 |
0 |
1 |
0 |
0 |
T38 |
20419 |
0 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
T43 |
1161 |
0 |
0 |
0 |
T44 |
14484 |
0 |
0 |
0 |
T46 |
0 |
2 |
0 |
0 |
T47 |
0 |
2 |
0 |
0 |
T48 |
0 |
3 |
0 |
0 |
T49 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1340 |
0 |
0 |
T8 |
102445 |
1 |
0 |
0 |
T9 |
818929 |
0 |
0 |
0 |
T10 |
465140 |
0 |
0 |
0 |
T11 |
139237 |
0 |
0 |
0 |
T12 |
474764 |
0 |
0 |
0 |
T13 |
474458 |
0 |
0 |
0 |
T14 |
974629 |
0 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
T31 |
0 |
2 |
0 |
0 |
T33 |
0 |
1 |
0 |
0 |
T38 |
102100 |
0 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
T43 |
557783 |
0 |
0 |
0 |
T44 |
173818 |
0 |
0 |
0 |
T46 |
0 |
2 |
0 |
0 |
T47 |
0 |
2 |
0 |
0 |
T48 |
0 |
3 |
0 |
0 |
T49 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T8,T39,T40 |
1 | 0 | Covered | T8,T39,T40 |
1 | 1 | Covered | T39,T40,T46 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T8,T39,T40 |
1 | 0 | Covered | T39,T40,T46 |
1 | 1 | Covered | T8,T39,T40 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1326 |
0 |
0 |
T8 |
102445 |
1 |
0 |
0 |
T9 |
818929 |
0 |
0 |
0 |
T10 |
465140 |
0 |
0 |
0 |
T11 |
139237 |
0 |
0 |
0 |
T12 |
474764 |
0 |
0 |
0 |
T13 |
474458 |
0 |
0 |
0 |
T14 |
974629 |
0 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
T31 |
0 |
2 |
0 |
0 |
T33 |
0 |
1 |
0 |
0 |
T38 |
102100 |
0 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
T43 |
557783 |
0 |
0 |
0 |
T44 |
173818 |
0 |
0 |
0 |
T46 |
0 |
2 |
0 |
0 |
T47 |
0 |
2 |
0 |
0 |
T48 |
0 |
3 |
0 |
0 |
T49 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
1326 |
0 |
0 |
T8 |
40976 |
1 |
0 |
0 |
T9 |
65513 |
0 |
0 |
0 |
T10 |
96906 |
0 |
0 |
0 |
T11 |
1113 |
0 |
0 |
0 |
T12 |
98911 |
0 |
0 |
0 |
T13 |
99881 |
0 |
0 |
0 |
T14 |
19889 |
0 |
0 |
0 |
T15 |
0 |
2 |
0 |
0 |
T31 |
0 |
2 |
0 |
0 |
T33 |
0 |
1 |
0 |
0 |
T38 |
20419 |
0 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
T43 |
1161 |
0 |
0 |
0 |
T44 |
14484 |
0 |
0 |
0 |
T46 |
0 |
2 |
0 |
0 |
T47 |
0 |
2 |
0 |
0 |
T48 |
0 |
3 |
0 |
0 |
T49 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T1,T3,T5 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T1,T3,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34407821 |
68385 |
0 |
0 |
T1 |
97062 |
222 |
0 |
0 |
T2 |
21399 |
0 |
0 |
0 |
T3 |
46241 |
45 |
0 |
0 |
T5 |
33582 |
75 |
0 |
0 |
T6 |
24395 |
0 |
0 |
0 |
T7 |
7686 |
0 |
0 |
0 |
T8 |
40976 |
76 |
0 |
0 |
T9 |
65513 |
162 |
0 |
0 |
T10 |
96906 |
206 |
0 |
0 |
T11 |
1113 |
0 |
0 |
0 |
T12 |
0 |
250 |
0 |
0 |
T13 |
0 |
252 |
0 |
0 |
T39 |
0 |
148 |
0 |
0 |
T40 |
0 |
209 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
68538 |
0 |
0 |
T1 |
456209 |
222 |
0 |
0 |
T2 |
214009 |
0 |
0 |
0 |
T3 |
647398 |
45 |
0 |
0 |
T5 |
159525 |
75 |
0 |
0 |
T6 |
120763 |
0 |
0 |
0 |
T7 |
372831 |
0 |
0 |
0 |
T8 |
102445 |
76 |
0 |
0 |
T9 |
818929 |
162 |
0 |
0 |
T10 |
465140 |
206 |
0 |
0 |
T11 |
139237 |
0 |
0 |
0 |
T12 |
0 |
250 |
0 |
0 |
T13 |
0 |
252 |
0 |
0 |
T39 |
0 |
148 |
0 |
0 |
T40 |
0 |
209 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_adc_ctrl_core.u_oneshot_done_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_adc_ctrl_core.u_oneshot_done_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T2,T3,T6 |
1 | 0 | Covered | T2,T3,T6 |
1 | 1 | Covered | T2,T3,T6 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T2 |
0 | 1 | Covered | T2,T3,T6 |
1 | 0 | Covered | T2,T3,T6 |
1 | 1 | Covered | T2,T3,T6 |
Branch Coverage for Instance : tb.dut.u_adc_ctrl_core.u_oneshot_done_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T1,T2 |
0 |
Covered |
T4,T1,T2 |
Assert Coverage for Instance : tb.dut.u_adc_ctrl_core.u_oneshot_done_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
6911 |
0 |
0 |
T2 |
214009 |
55 |
0 |
0 |
T3 |
647398 |
81 |
0 |
0 |
T5 |
159525 |
0 |
0 |
0 |
T6 |
120763 |
44 |
0 |
0 |
T7 |
372831 |
0 |
0 |
0 |
T8 |
102445 |
0 |
0 |
0 |
T9 |
818929 |
0 |
0 |
0 |
T10 |
465140 |
0 |
0 |
0 |
T11 |
139237 |
20 |
0 |
0 |
T14 |
0 |
37 |
0 |
0 |
T15 |
0 |
61 |
0 |
0 |
T38 |
0 |
45 |
0 |
0 |
T43 |
557783 |
20 |
0 |
0 |
T44 |
0 |
34 |
0 |
0 |
T111 |
0 |
20 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34329144 |
6913 |
0 |
0 |
T2 |
21399 |
55 |
0 |
0 |
T3 |
46241 |
82 |
0 |
0 |
T5 |
33582 |
0 |
0 |
0 |
T6 |
24395 |
44 |
0 |
0 |
T7 |
7686 |
0 |
0 |
0 |
T8 |
40976 |
0 |
0 |
0 |
T9 |
65513 |
0 |
0 |
0 |
T10 |
96906 |
0 |
0 |
0 |
T11 |
1113 |
20 |
0 |
0 |
T14 |
0 |
37 |
0 |
0 |
T15 |
0 |
61 |
0 |
0 |
T38 |
0 |
45 |
0 |
0 |
T43 |
1161 |
20 |
0 |
0 |
T44 |
0 |
34 |
0 |
0 |
T111 |
0 |
20 |
0 |
0 |