Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2268	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2473	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2457	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2382	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2389	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2458	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2365	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2355	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2414	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2487	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2283	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2415	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2347	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2366	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2290	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2319	0	0
adc_en_ctl_rd_A	2147483647	1925	0	0
adc_fsm_rst_rd_A	2147483647	1706	0	0
adc_intr_ctl_rd_A	2147483647	2779	0	0
adc_lp_sample_ctl_rd_A	2147483647	1930	0	0
adc_pd_ctl_rd_A	2147483647	2192	0	0
adc_sample_ctl_rd_A	2147483647	1733	0	0
adc_wakeup_ctl_rd_A	2147483647	2060	0	0
intr_enable_rd_A	2147483647	3052	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2268	0	0
T17	464256	6	0	0
T18	493994	46	0	0
T19	0	34	0	0
T20	0	32	0	0
T21	0	30	0	0
T22	0	43	0	0
T23	0	55	0	0
T24	0	21	0	0
T25	0	10	0	0
T26	0	39	0	0
T27	125457	0	0	0
T28	877166	0	0	0
T29	266154	0	0	0
T30	181910	0	0	0
T31	483128	0	0	0
T32	506805	0	0	0
T33	250984	0	0	0
T34	469685	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2473	0	0
T17	464256	24	0	0
T18	493994	30	0	0
T19	0	16	0	0
T20	0	27	0	0
T21	0	25	0	0
T22	0	37	0	0
T23	0	34	0	0
T24	0	19	0	0
T25	0	19	0	0
T26	0	23	0	0
T27	125457	0	0	0
T28	877166	0	0	0
T29	266154	0	0	0
T30	181910	0	0	0
T31	483128	0	0	0
T32	506805	0	0	0
T33	250984	0	0	0
T34	469685	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2457	0	0
T17	464256	17	0	0
T18	493994	31	0	0
T19	0	16	0	0
T20	0	6	0	0
T21	0	38	0	0
T22	0	41	0	0
T23	0	57	0	0
T24	0	31	0	0
T25	0	18	0	0
T26	0	40	0	0
T27	125457	0	0	0
T28	877166	0	0	0
T29	266154	0	0	0
T30	181910	0	0	0
T31	483128	0	0	0
T32	506805	0	0	0
T33	250984	0	0	0
T34	469685	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2382	0	0
T17	464256	22	0	0
T18	493994	31	0	0
T19	0	11	0	0
T20	0	12	0	0
T21	0	28	0	0
T22	0	46	0	0
T23	0	37	0	0
T24	0	14	0	0
T25	0	20	0	0
T26	0	27	0	0
T27	125457	0	0	0
T28	877166	0	0	0
T29	266154	0	0	0
T30	181910	0	0	0
T31	483128	0	0	0
T32	506805	0	0	0
T33	250984	0	0	0
T34	469685	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2389	0	0
T17	464256	29	0	0
T18	493994	20	0	0
T19	0	23	0	0
T20	0	14	0	0
T21	0	48	0	0
T22	0	30	0	0
T23	0	39	0	0
T24	0	14	0	0
T25	0	42	0	0
T26	0	9	0	0
T27	125457	0	0	0
T28	877166	0	0	0
T29	266154	0	0	0
T30	181910	0	0	0
T31	483128	0	0	0
T32	506805	0	0	0
T33	250984	0	0	0
T34	469685	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2458	0	0
T17	464256	28	0	0
T18	493994	30	0	0
T19	0	28	0	0
T20	0	16	0	0
T21	0	49	0	0
T22	0	51	0	0
T23	0	18	0	0
T24	0	14	0	0
T25	0	23	0	0
T26	0	27	0	0
T27	125457	0	0	0
T28	877166	0	0	0
T29	266154	0	0	0
T30	181910	0	0	0
T31	483128	0	0	0
T32	506805	0	0	0
T33	250984	0	0	0
T34	469685	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2365	0	0
T17	464256	22	0	0
T18	493994	40	0	0
T19	0	27	0	0
T20	0	13	0	0
T21	0	36	0	0
T22	0	37	0	0
T23	0	24	0	0
T24	0	6	0	0
T25	0	17	0	0
T26	0	23	0	0
T27	125457	0	0	0
T28	877166	0	0	0
T29	266154	0	0	0
T30	181910	0	0	0
T31	483128	0	0	0
T32	506805	0	0	0
T33	250984	0	0	0
T34	469685	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2355	0	0
T17	464256	17	0	0
T18	493994	48	0	0
T19	0	10	0	0
T20	0	17	0	0
T21	0	28	0	0
T22	0	35	0	0
T23	0	51	0	0
T24	0	15	0	0
T25	0	15	0	0
T26	0	19	0	0
T27	125457	0	0	0
T28	877166	0	0	0
T29	266154	0	0	0
T30	181910	0	0	0
T31	483128	0	0	0
T32	506805	0	0	0
T33	250984	0	0	0
T34	469685	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2414	0	0
T17	464256	25	0	0
T18	493994	28	0	0
T19	0	14	0	0
T20	0	17	0	0
T21	0	42	0	0
T22	0	39	0	0
T23	0	47	0	0
T24	0	21	0	0
T25	0	5	0	0
T26	0	14	0	0
T27	125457	0	0	0
T28	877166	0	0	0
T29	266154	0	0	0
T30	181910	0	0	0
T31	483128	0	0	0
T32	506805	0	0	0
T33	250984	0	0	0
T34	469685	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2487	0	0
T17	464256	22	0	0
T18	493994	16	0	0
T19	0	33	0	0
T20	0	21	0	0
T21	0	44	0	0
T22	0	30	0	0
T23	0	32	0	0
T24	0	8	0	0
T25	0	41	0	0
T26	0	32	0	0
T27	125457	0	0	0
T28	877166	0	0	0
T29	266154	0	0	0
T30	181910	0	0	0
T31	483128	0	0	0
T32	506805	0	0	0
T33	250984	0	0	0
T34	469685	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2283	0	0
T17	464256	23	0	0
T18	493994	30	0	0
T19	0	19	0	0
T20	0	20	0	0
T21	0	29	0	0
T22	0	44	0	0
T23	0	25	0	0
T24	0	5	0	0
T25	0	37	0	0
T26	0	26	0	0
T27	125457	0	0	0
T28	877166	0	0	0
T29	266154	0	0	0
T30	181910	0	0	0
T31	483128	0	0	0
T32	506805	0	0	0
T33	250984	0	0	0
T34	469685	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2415	0	0
T17	464256	22	0	0
T18	493994	29	0	0
T19	0	17	0	0
T20	0	28	0	0
T21	0	40	0	0
T22	0	37	0	0
T23	0	34	0	0
T24	0	14	0	0
T25	0	20	0	0
T26	0	40	0	0
T27	125457	0	0	0
T28	877166	0	0	0
T29	266154	0	0	0
T30	181910	0	0	0
T31	483128	0	0	0
T32	506805	0	0	0
T33	250984	0	0	0
T34	469685	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2347	0	0
T17	464256	19	0	0
T18	493994	39	0	0
T19	0	22	0	0
T20	0	22	0	0
T21	0	26	0	0
T22	0	31	0	0
T23	0	43	0	0
T24	0	15	0	0
T25	0	31	0	0
T26	0	35	0	0
T27	125457	0	0	0
T28	877166	0	0	0
T29	266154	0	0	0
T30	181910	0	0	0
T31	483128	0	0	0
T32	506805	0	0	0
T33	250984	0	0	0
T34	469685	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2366	0	0
T17	464256	31	0	0
T18	493994	29	0	0
T19	0	31	0	0
T20	0	18	0	0
T21	0	23	0	0
T22	0	37	0	0
T23	0	43	0	0
T24	0	26	0	0
T25	0	12	0	0
T26	0	29	0	0
T27	125457	0	0	0
T28	877166	0	0	0
T29	266154	0	0	0
T30	181910	0	0	0
T31	483128	0	0	0
T32	506805	0	0	0
T33	250984	0	0	0
T34	469685	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2290	0	0
T17	464256	13	0	0
T18	493994	30	0	0
T19	0	43	0	0
T20	0	27	0	0
T21	0	42	0	0
T22	0	29	0	0
T23	0	43	0	0
T24	0	17	0	0
T25	0	10	0	0
T26	0	28	0	0
T27	125457	0	0	0
T28	877166	0	0	0
T29	266154	0	0	0
T30	181910	0	0	0
T31	483128	0	0	0
T32	506805	0	0	0
T33	250984	0	0	0
T34	469685	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2319	0	0
T17	464256	31	0	0
T18	493994	40	0	0
T19	0	25	0	0
T20	0	31	0	0
T21	0	41	0	0
T22	0	54	0	0
T23	0	28	0	0
T24	0	14	0	0
T25	0	18	0	0
T26	0	17	0	0
T27	125457	0	0	0
T28	877166	0	0	0
T29	266154	0	0	0
T30	181910	0	0	0
T31	483128	0	0	0
T32	506805	0	0	0
T33	250984	0	0	0
T34	469685	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1925	0	0
T17	464256	5	0	0
T18	493994	41	0	0
T19	0	13	0	0
T20	0	17	0	0
T21	0	44	0	0
T22	0	28	0	0
T23	0	52	0	0
T24	0	13	0	0
T25	0	9	0	0
T26	0	30	0	0
T27	125457	0	0	0
T28	877166	0	0	0
T29	266154	0	0	0
T30	181910	0	0	0
T31	483128	0	0	0
T32	506805	0	0	0
T33	250984	0	0	0
T34	469685	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1706	0	0
T17	464256	35	0	0
T18	493994	44	0	0
T19	0	15	0	0
T20	0	12	0	0
T21	0	26	0	0
T22	0	31	0	0
T23	0	42	0	0
T24	0	24	0	0
T25	0	25	0	0
T26	0	14	0	0
T27	125457	0	0	0
T28	877166	0	0	0
T29	266154	0	0	0
T30	181910	0	0	0
T31	483128	0	0	0
T32	506805	0	0	0
T33	250984	0	0	0
T34	469685	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2779	0	0
T17	464256	8	0	0
T18	493994	47	0	0
T19	0	12	0	0
T20	0	8	0	0
T21	0	27	0	0
T22	0	44	0	0
T23	0	36	0	0
T24	0	24	0	0
T25	0	18	0	0
T26	0	31	0	0
T27	125457	0	0	0
T28	877166	0	0	0
T29	266154	0	0	0
T30	181910	0	0	0
T31	483128	0	0	0
T32	506805	0	0	0
T33	250984	0	0	0
T34	469685	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1930	0	0
T17	464256	15	0	0
T18	493994	38	0	0
T19	0	26	0	0
T20	0	21	0	0
T21	0	23	0	0
T22	0	33	0	0
T23	0	25	0	0
T24	0	25	0	0
T25	0	23	0	0
T26	0	30	0	0
T27	125457	0	0	0
T28	877166	0	0	0
T29	266154	0	0	0
T30	181910	0	0	0
T31	483128	0	0	0
T32	506805	0	0	0
T33	250984	0	0	0
T34	469685	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2192	0	0
T17	464256	35	0	0
T18	493994	24	0	0
T19	0	36	0	0
T20	0	20	0	0
T21	0	50	0	0
T22	0	35	0	0
T23	0	37	0	0
T24	0	26	0	0
T25	0	23	0	0
T26	0	20	0	0
T27	125457	0	0	0
T28	877166	0	0	0
T29	266154	0	0	0
T30	181910	0	0	0
T31	483128	0	0	0
T32	506805	0	0	0
T33	250984	0	0	0
T34	469685	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1733	0	0
T17	464256	16	0	0
T18	493994	39	0	0
T19	0	4	0	0
T20	0	17	0	0
T21	0	43	0	0
T22	0	37	0	0
T23	0	16	0	0
T24	0	21	0	0
T25	0	20	0	0
T26	0	12	0	0
T27	125457	0	0	0
T28	877166	0	0	0
T29	266154	0	0	0
T30	181910	0	0	0
T31	483128	0	0	0
T32	506805	0	0	0
T33	250984	0	0	0
T34	469685	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2060	0	0
T17	464256	26	0	0
T18	493994	29	0	0
T19	0	6	0	0
T20	0	17	0	0
T21	0	28	0	0
T22	0	38	0	0
T23	0	55	0	0
T24	0	27	0	0
T25	0	17	0	0
T26	0	21	0	0
T27	125457	0	0	0
T28	877166	0	0	0
T29	266154	0	0	0
T30	181910	0	0	0
T31	483128	0	0	0
T32	506805	0	0	0
T33	250984	0	0	0
T34	469685	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3052	0	0
T17	464256	21	0	0
T18	493994	85	0	0
T19	0	23	0	0
T20	0	35	0	0
T21	0	55	0	0
T22	0	50	0	0
T23	0	34	0	0
T24	0	15	0	0
T25	0	47	0	0
T27	125457	0	0	0
T28	877166	0	0	0
T29	266154	0	0	0
T30	181910	0	0	0
T31	483128	0	0	0
T32	506805	0	0	0
T33	250984	0	0	0
T34	469685	0	0	0
T35	0	5	0	0