Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1213032	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1184065

1

T1

954

T2

24

T3

1339

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2098950	1			T1	1668		T3	2503		T4	81
values[0x0]	148701	1			T1	111		T2	17		T3	148
values[0x1]	149446	1			T1	96		T2	17		T3	165

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	972524	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1424573

1

T1

1139

T2

29

T3

1608

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14898	1			T1	10		T3	10		T5	47
valid_sources[0x01]	7294	1			T1	9		T3	4		T4	1
valid_sources[0x02]	17055	1			T1	13		T3	9		T4	1
valid_sources[0x03]	13142	1			T1	6		T3	8		T5	46
valid_sources[0x04]	8018	1			T1	1		T3	1		T4	2
valid_sources[0x05]	8355	1			T1	8		T3	5		T5	63
valid_sources[0x06]	6903	1			T1	1		T3	26		T5	25
valid_sources[0x07]	7021	1			T3	17		T5	53		T6	1
valid_sources[0x08]	13223	1			T1	10		T3	4		T5	62
valid_sources[0x09]	13780	1			T1	4		T3	7		T4	1
valid_sources[0x0a]	7056	1			T1	12		T3	55		T5	34
valid_sources[0x0b]	6853	1			T1	1		T3	20		T4	2
valid_sources[0x0c]	6807	1			T1	11		T3	22		T5	48
valid_sources[0x0d]	6812	1			T1	19		T5	43		T7	5
valid_sources[0x0e]	7091	1			T1	11		T3	4		T5	54
valid_sources[0x0f]	20763	1			T1	9		T3	24		T5	49
valid_sources[0x10]	7714	1			T1	5		T3	16		T5	43
valid_sources[0x11]	11224	1			T1	5		T5	27		T7	3
valid_sources[0x12]	7022	1			T1	5		T3	5		T5	32
valid_sources[0x13]	14001	1			T1	12		T3	8		T5	37
valid_sources[0x14]	12417	1			T1	5		T3	2		T4	1
valid_sources[0x15]	6612	1			T1	4		T3	12		T4	2
valid_sources[0x16]	7269	1			T1	17		T3	12		T5	53
valid_sources[0x17]	7157	1			T5	39		T6	1		T10	52
valid_sources[0x18]	7068	1			T1	8		T3	18		T5	32
valid_sources[0x19]	11824	1			T1	1		T3	8		T4	1
valid_sources[0x1a]	6948	1			T1	7		T3	3		T5	38
valid_sources[0x1b]	7403	1			T1	7		T3	4		T5	50
valid_sources[0x1c]	6747	1			T1	15		T3	19		T5	20
valid_sources[0x1d]	9102	1			T1	6		T3	11		T5	52
valid_sources[0x1e]	13875	1			T3	6		T5	60		T7	2
valid_sources[0x1f]	19506	1			T1	7		T3	31		T5	45
valid_sources[0x20]	11461	1			T1	7		T5	83		T7	7
valid_sources[0x21]	12152	1			T1	7		T3	2		T4	3
valid_sources[0x22]	8225	1			T1	4		T3	1		T4	1
valid_sources[0x23]	7998	1			T3	4		T5	77		T7	5
valid_sources[0x24]	11438	1			T1	3		T3	19		T4	1
valid_sources[0x25]	11148	1			T1	5		T3	7		T4	1
valid_sources[0x26]	18341	1			T1	8		T3	6		T4	3
valid_sources[0x27]	6848	1			T1	7		T3	2		T5	82
valid_sources[0x28]	7257	1			T1	12		T3	12		T5	57
valid_sources[0x29]	7433	1			T1	5		T3	8		T4	3
valid_sources[0x2a]	8631	1			T1	13		T3	19		T4	1
valid_sources[0x2b]	7994	1			T1	7		T3	27		T4	2
valid_sources[0x2c]	11870	1			T1	1		T3	10		T5	31
valid_sources[0x2d]	14400	1			T1	2		T3	6		T5	54
valid_sources[0x2e]	11913	1			T1	15		T4	1		T5	77
valid_sources[0x2f]	12271	1			T1	6		T3	5		T5	65
valid_sources[0x30]	9600	1			T1	2		T3	10		T5	46
valid_sources[0x31]	7053	1			T3	3		T5	39		T7	2
valid_sources[0x32]	6658	1			T1	3		T3	14		T5	48
valid_sources[0x33]	6897	1			T1	3		T3	12		T4	1
valid_sources[0x34]	6863	1			T1	1		T3	16		T4	1
valid_sources[0x35]	15411	1			T3	43		T4	1		T5	22
valid_sources[0x36]	6750	1			T1	8		T4	1		T5	30
valid_sources[0x37]	7108	1			T1	7		T3	31		T4	1
valid_sources[0x38]	7226	1			T1	7		T3	20		T5	56
valid_sources[0x39]	6792	1			T1	14		T3	6		T5	74
valid_sources[0x3a]	6991	1			T1	3		T3	7		T4	1
valid_sources[0x3b]	11211	1			T1	10		T3	28		T5	57
valid_sources[0x3c]	6536	1			T1	10		T3	22		T5	62
valid_sources[0x3d]	6928	1			T1	5		T3	18		T5	36
valid_sources[0x3e]	7771	1			T1	7		T4	1		T5	47
valid_sources[0x3f]	11043	1			T1	3		T3	21		T5	41
valid_sources[0x40]	7815	1			T1	1		T3	1		T5	28
valid_sources[0x41]	7053	1			T1	2		T3	9		T4	1
valid_sources[0x42]	7386	1			T1	14		T3	6		T5	33
valid_sources[0x43]	6762	1			T1	1		T3	2		T5	56
valid_sources[0x44]	15703	1			T1	5		T3	3		T4	1
valid_sources[0x45]	7387	1			T1	11		T3	1		T4	2
valid_sources[0x46]	9263	1			T1	4		T3	12		T4	1
valid_sources[0x47]	7346	1			T1	19		T3	9		T5	42
valid_sources[0x48]	9051	1			T1	8		T4	1		T5	55
valid_sources[0x49]	12164	1			T1	12		T3	2		T5	47
valid_sources[0x4a]	6779	1			T1	12		T3	24		T4	1
valid_sources[0x4b]	15765	1			T1	4		T3	18		T5	36
valid_sources[0x4c]	7058	1			T1	3		T3	12		T4	1
valid_sources[0x4d]	8675	1			T3	4		T5	44		T6	1
valid_sources[0x4e]	7148	1			T1	11		T3	9		T4	2
valid_sources[0x4f]	6609	1			T1	6		T3	3		T5	44
valid_sources[0x50]	14844	1			T1	19		T2	34		T3	13
valid_sources[0x51]	12245	1			T1	12		T3	7		T4	1
valid_sources[0x52]	8731	1			T1	1		T3	7		T4	2
valid_sources[0x53]	6784	1			T1	9		T3	50		T5	72
valid_sources[0x54]	8710	1			T1	3		T3	2		T4	1
valid_sources[0x55]	17790	1			T1	27		T4	1		T5	36
valid_sources[0x56]	11231	1			T1	4		T3	6		T4	1
valid_sources[0x57]	8612	1			T1	8		T3	17		T5	45
valid_sources[0x58]	8995	1			T1	6		T3	10		T5	72
valid_sources[0x59]	12528	1			T1	6		T3	21		T4	2
valid_sources[0x5a]	6996	1			T1	17		T4	1		T5	37
valid_sources[0x5b]	8860	1			T1	17		T4	1		T5	51
valid_sources[0x5c]	10796	1			T1	15		T3	16		T5	53
valid_sources[0x5d]	6859	1			T1	22		T3	19		T5	30
valid_sources[0x5e]	7147	1			T1	11		T3	13		T5	39
valid_sources[0x5f]	17061	1			T1	5		T5	70		T6	2
valid_sources[0x60]	15284	1			T1	7		T3	34		T4	1
valid_sources[0x61]	7936	1			T1	3		T3	1		T4	1
valid_sources[0x62]	13006	1			T1	7		T3	12		T5	49
valid_sources[0x63]	11210	1			T1	3		T3	8		T4	1
valid_sources[0x64]	6743	1			T1	4		T3	18		T5	57
valid_sources[0x65]	13361	1			T1	3		T3	10		T4	1
valid_sources[0x66]	6590	1			T1	4		T3	4		T4	2
valid_sources[0x67]	6807	1			T1	3		T3	1		T5	39
valid_sources[0x68]	11445	1			T1	6		T3	4		T4	1
valid_sources[0x69]	7483	1			T1	8		T3	44		T4	1
valid_sources[0x6a]	7692	1			T1	14		T3	4		T5	49
valid_sources[0x6b]	7323	1			T1	3		T3	22		T5	84
valid_sources[0x6c]	7139	1			T1	7		T4	1		T5	66
valid_sources[0x6d]	9714	1			T1	11		T3	4		T5	48
valid_sources[0x6e]	9591	1			T1	4		T5	43		T7	2
valid_sources[0x6f]	6953	1			T1	3		T3	14		T16	17
valid_sources[0x70]	11545	1			T1	12		T3	6		T5	59
valid_sources[0x71]	7419	1			T1	9		T3	5		T5	45
valid_sources[0x72]	7957	1			T1	21		T3	4		T5	63
valid_sources[0x73]	8807	1			T1	8		T3	4		T4	2
valid_sources[0x74]	7410	1			T1	11		T3	7		T4	1
valid_sources[0x75]	9724	1			T3	4		T5	48		T10	41
valid_sources[0x76]	7129	1			T1	4		T3	5		T4	1
valid_sources[0x77]	7022	1			T1	8		T3	30		T4	1
valid_sources[0x78]	6851	1			T1	3		T3	14		T5	38
valid_sources[0x79]	11406	1			T1	4		T3	24		T4	2
valid_sources[0x7a]	7332	1			T1	8		T3	52		T5	54
valid_sources[0x7b]	9835	1			T1	6		T3	1		T5	55
valid_sources[0x7c]	7154	1			T1	3		T3	14		T4	1
valid_sources[0x7d]	7149	1			T1	4		T3	13		T5	65
valid_sources[0x7e]	7240	1			T1	11		T3	11		T5	44
valid_sources[0x7f]	7104	1			T1	9		T3	24		T4	1
valid_sources[0x80]	10588	1			T1	1		T3	12		T5	48

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1045692

1

T1

856

T3

1188

T4

37

values[0x0]

all_enables

biggest_size

80468

1

T1

62

T2

14

T3

87

values[0x1]

all_enables

biggest_size

57905

1

T1

36

T2

10

T3

64