Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	31044	1			T1	14		T3	15		T5	23
auto[PWRUP]	108	1			T7	2		T19	1		T36	1
auto[ONEST_0]	72	1			T7	1		T41	1		T36	1
auto[ONEST_021]	31	1			T7	1		T34	1		T23	1
auto[ONEST_1]	87	1			T18	2		T34	1		T41	2
auto[ONEST_DONE]	8	1			T42	1		T171	1		T192	2
auto[LP_0]	141	1			T7	2		T18	1		T34	1
auto[LP_021]	24	1			T42	2		T171	1		T193	1
auto[LP_1]	142	1			T7	2		T18	1		T34	2
auto[LP_EVAL]	76	1			T18	1		T34	1		T41	1
auto[LP_SLP]	506	1			T7	7		T34	7		T41	4
auto[LP_PWRUP]	26	1			T180	1		T194	1		T42	1
auto[NP_0]	140	1			T7	1		T18	1		T34	1
auto[NP_021]	42	1			T7	1		T20	1		T180	1
auto[NP_1]	164	1			T7	3		T34	1		T41	3
auto[NP_EVAL]	36	1			T41	1		T36	1		T21	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

9

1

T171

1

T195

1

T196

2

min

30464

1

T1

14

T3

15

T5

23

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	30475	1			T1	14		T3	15		T5	23
pow[0x1]	2	1			T36	1		T197	1		-	-
pow[0x2]	19	1			T21	1		T198	1		T199	1
pow[0x3]	29	1			T180	1		T200	1		T39	1
pow[0x4]	62	1			T41	1		T180	2		T200	3
pow[0x5]	137	1			T7	2		T41	2		T36	1
pow[0x6]	270	1			T7	4		T18	2		T34	2
pow[0x7]	537	1			T7	6		T18	3		T34	8

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

190

1

T7

3

T34

1

T41

3

min

29988

1

T1

14

T3

15

T5

23

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29988	1			T1	14		T3	15		T5	23
pow[0x5]	1	1			T201	1		-	-		-	-
pow[0x6]	1	1			T202	1		-	-		-	-
pow[0x7]	2	1			T203	1		T204	1		-	-
pow[0x8]	4	1			T198	1		T24	1		T203	1
pow[0x9]	9	1			T41	1		T193	1		T205	1
pow[0xa]	16	1			T36	1		T198	1		T77	1
pow[0xb]	38	1			T21	1		T180	2		T200	2
pow[0xc]	79	1			T7	3		T41	1		T36	1
pow[0xd]	165	1			T7	6		T34	2		T41	4
pow[0xe]	305	1			T7	2		T18	1		T34	6
pow[0xf]	609	1			T7	3		T18	2		T34	8