Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2331	1			T7	10		T12	5		T17	12
auto[PWRUP]	134	1			T18	1		T34	3		T19	1
auto[ONEST_0]	82	1			T7	1		T34	2		T41	1
auto[ONEST_021]	20	1			T21	1		T194	1		T335	2
auto[ONEST_1]	72	1			T7	1		T34	1		T180	2
auto[ONEST_DONE]	3	1			T143	1		T336	1		T337	1
auto[LP_0]	143	1			T18	2		T34	2		T41	1
auto[LP_021]	31	1			T7	3		T41	1		T21	1
auto[LP_1]	123	1			T7	4		T41	1		T36	4
auto[LP_EVAL]	60	1			T18	1		T34	1		T19	3
auto[LP_SLP]	538	1			T7	1		T17	1		T18	4
auto[LP_PWRUP]	32	1			T7	1		T41	2		T200	1
auto[NP_0]	237	1			T7	2		T17	3		T18	1
auto[NP_021]	52	1			T36	1		T37	1		T194	1
auto[NP_1]	213	1			T7	1		T17	5		T34	2
auto[NP_EVAL]	32	1			T19	1		T41	1		T21	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

11

1

T335

1

T193

1

T198

1

min

1948

1

T7

6

T12

5

T17

21

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1967	1			T7	6		T12	5		T17	21
pow[0x1]	14	1			T36	1		T244	1		T144	1
pow[0x2]	25	1			T41	1		T21	2		T200	1
pow[0x3]	37	1			T7	1		T19	1		T41	1
pow[0x4]	75	1			T18	1		T34	2		T19	1
pow[0x5]	115	1			T41	2		T36	3		T21	1
pow[0x6]	285	1			T7	4		T18	1		T34	3
pow[0x7]	528	1			T7	2		T18	1		T34	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

207

1

T7

1

T41

4

T36

3

min

1355

1

T7

1

T12

5

T17

17

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1360	1			T7	1		T12	5		T17	17
pow[0x1]	9	1			T22	1		T23	1		T77	1
pow[0x2]	28	1			T36	1		T22	1		T196	1
pow[0x3]	25	1			T17	1		T19	2		T36	3
pow[0x4]	67	1			T17	3		T20	1		T37	1
pow[0x5]	1	1			T338	1		-	-		-	-
pow[0x6]	1	1			T339	1		-	-		-	-
pow[0x7]	4	1			T193	1		T24	1		T340	1
pow[0x8]	9	1			T41	1		T194	1		T42	1
pow[0x9]	15	1			T194	1		T171	1		T303	1
pow[0xa]	16	1			T37	1		T200	1		T42	1
pow[0xb]	41	1			T41	1		T200	2		T193	1
pow[0xc]	70	1			T19	1		T41	1		T36	1
pow[0xd]	140	1			T18	1		T41	2		T36	1
pow[0xe]	300	1			T7	3		T18	1		T34	2
pow[0xf]	617	1			T7	5		T18	1		T34	5