Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1972	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1922	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1538	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1894	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2061	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2166	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1996	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1835	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1978	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2008	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1822	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2093	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2057	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1838	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1823	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1978	0	0
adc_en_ctl_rd_A	2147483647	1673	0	0
adc_fsm_rst_rd_A	2147483647	1460	0	0
adc_intr_ctl_rd_A	2147483647	2304	0	0
adc_lp_sample_ctl_rd_A	2147483647	1516	0	0
adc_pd_ctl_rd_A	2147483647	1810	0	0
adc_sample_ctl_rd_A	2147483647	1416	0	0
adc_wakeup_ctl_rd_A	2147483647	1700	0	0
intr_enable_rd_A	2147483647	2438	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1972	0	0
T13	167405	5	0	0
T14	0	15	0	0
T15	0	15	0	0
T16	0	12	0	0
T17	0	42	0	0
T18	0	12	0	0
T19	0	10	0	0
T20	0	15	0	0
T21	0	38	0	0
T22	0	23	0	0
T23	387262	0	0	0
T24	8853	0	0	0
T25	154831	0	0	0
T26	34756	0	0	0
T27	117810	0	0	0
T28	261044	0	0	0
T29	85093	0	0	0
T30	155732	0	0	0
T31	148365	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1922	0	0
T13	167405	9	0	0
T14	0	17	0	0
T15	0	16	0	0
T16	0	11	0	0
T17	0	48	0	0
T18	0	1	0	0
T19	0	9	0	0
T20	0	17	0	0
T21	0	27	0	0
T22	0	8	0	0
T23	387262	0	0	0
T24	8853	0	0	0
T25	154831	0	0	0
T26	34756	0	0	0
T27	117810	0	0	0
T28	261044	0	0	0
T29	85093	0	0	0
T30	155732	0	0	0
T31	148365	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1538	0	0
T14	245562	23	0	0
T15	0	14	0	0
T16	0	22	0	0
T17	0	36	0	0
T18	0	9	0	0
T19	0	14	0	0
T20	0	7	0	0
T21	0	30	0	0
T22	0	21	0	0
T32	0	14	0	0
T33	17571	0	0	0
T34	121334	0	0	0
T35	482802	0	0	0
T36	530407	0	0	0
T37	154164	0	0	0
T38	358207	0	0	0
T39	467544	0	0	0
T40	798026	0	0	0
T41	955270	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1894	0	0
T13	167405	8	0	0
T14	0	20	0	0
T15	0	20	0	0
T16	0	5	0	0
T17	0	40	0	0
T18	0	4	0	0
T19	0	17	0	0
T20	0	12	0	0
T21	0	42	0	0
T22	0	26	0	0
T23	387262	0	0	0
T24	8853	0	0	0
T25	154831	0	0	0
T26	34756	0	0	0
T27	117810	0	0	0
T28	261044	0	0	0
T29	85093	0	0	0
T30	155732	0	0	0
T31	148365	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2061	0	0
T13	167405	12	0	0
T14	0	14	0	0
T15	0	31	0	0
T16	0	11	0	0
T17	0	31	0	0
T18	0	12	0	0
T19	0	9	0	0
T20	0	11	0	0
T21	0	33	0	0
T22	0	7	0	0
T23	387262	0	0	0
T24	8853	0	0	0
T25	154831	0	0	0
T26	34756	0	0	0
T27	117810	0	0	0
T28	261044	0	0	0
T29	85093	0	0	0
T30	155732	0	0	0
T31	148365	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2166	0	0
T13	167405	15	0	0
T14	0	15	0	0
T15	0	18	0	0
T16	0	12	0	0
T17	0	31	0	0
T18	0	10	0	0
T19	0	11	0	0
T20	0	16	0	0
T21	0	45	0	0
T22	0	10	0	0
T23	387262	0	0	0
T24	8853	0	0	0
T25	154831	0	0	0
T26	34756	0	0	0
T27	117810	0	0	0
T28	261044	0	0	0
T29	85093	0	0	0
T30	155732	0	0	0
T31	148365	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1996	0	0
T13	167405	14	0	0
T14	0	25	0	0
T15	0	14	0	0
T16	0	8	0	0
T17	0	27	0	0
T18	0	9	0	0
T19	0	17	0	0
T20	0	13	0	0
T21	0	45	0	0
T22	0	8	0	0
T23	387262	0	0	0
T24	8853	0	0	0
T25	154831	0	0	0
T26	34756	0	0	0
T27	117810	0	0	0
T28	261044	0	0	0
T29	85093	0	0	0
T30	155732	0	0	0
T31	148365	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1835	0	0
T13	167405	9	0	0
T14	0	12	0	0
T15	0	28	0	0
T16	0	14	0	0
T17	0	38	0	0
T18	0	12	0	0
T19	0	17	0	0
T20	0	27	0	0
T21	0	32	0	0
T22	0	19	0	0
T23	387262	0	0	0
T24	8853	0	0	0
T25	154831	0	0	0
T26	34756	0	0	0
T27	117810	0	0	0
T28	261044	0	0	0
T29	85093	0	0	0
T30	155732	0	0	0
T31	148365	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1978	0	0
T13	167405	15	0	0
T14	0	22	0	0
T15	0	14	0	0
T16	0	10	0	0
T17	0	38	0	0
T18	0	9	0	0
T19	0	22	0	0
T20	0	13	0	0
T21	0	30	0	0
T22	0	17	0	0
T23	387262	0	0	0
T24	8853	0	0	0
T25	154831	0	0	0
T26	34756	0	0	0
T27	117810	0	0	0
T28	261044	0	0	0
T29	85093	0	0	0
T30	155732	0	0	0
T31	148365	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2008	0	0
T13	167405	10	0	0
T14	0	29	0	0
T15	0	26	0	0
T16	0	23	0	0
T17	0	39	0	0
T18	0	14	0	0
T19	0	27	0	0
T20	0	11	0	0
T21	0	27	0	0
T22	0	19	0	0
T23	387262	0	0	0
T24	8853	0	0	0
T25	154831	0	0	0
T26	34756	0	0	0
T27	117810	0	0	0
T28	261044	0	0	0
T29	85093	0	0	0
T30	155732	0	0	0
T31	148365	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1822	0	0
T14	245562	17	0	0
T15	0	13	0	0
T16	0	2	0	0
T17	0	31	0	0
T18	0	21	0	0
T19	0	14	0	0
T20	0	13	0	0
T21	0	36	0	0
T22	0	15	0	0
T32	0	16	0	0
T33	17571	0	0	0
T34	121334	0	0	0
T35	482802	0	0	0
T36	530407	0	0	0
T37	154164	0	0	0
T38	358207	0	0	0
T39	467544	0	0	0
T40	798026	0	0	0
T41	955270	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2093	0	0
T13	167405	11	0	0
T14	0	11	0	0
T15	0	15	0	0
T16	0	17	0	0
T17	0	25	0	0
T18	0	14	0	0
T19	0	20	0	0
T20	0	18	0	0
T21	0	28	0	0
T22	0	19	0	0
T23	387262	0	0	0
T24	8853	0	0	0
T25	154831	0	0	0
T26	34756	0	0	0
T27	117810	0	0	0
T28	261044	0	0	0
T29	85093	0	0	0
T30	155732	0	0	0
T31	148365	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2057	0	0
T14	245562	24	0	0
T15	0	32	0	0
T16	0	5	0	0
T17	0	39	0	0
T18	0	15	0	0
T19	0	10	0	0
T20	0	15	0	0
T21	0	51	0	0
T22	0	26	0	0
T32	0	14	0	0
T33	17571	0	0	0
T34	121334	0	0	0
T35	482802	0	0	0
T36	530407	0	0	0
T37	154164	0	0	0
T38	358207	0	0	0
T39	467544	0	0	0
T40	798026	0	0	0
T41	955270	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1838	0	0
T13	167405	2	0	0
T14	0	21	0	0
T15	0	20	0	0
T16	0	14	0	0
T17	0	39	0	0
T18	0	15	0	0
T19	0	11	0	0
T20	0	9	0	0
T21	0	31	0	0
T22	0	19	0	0
T23	387262	0	0	0
T24	8853	0	0	0
T25	154831	0	0	0
T26	34756	0	0	0
T27	117810	0	0	0
T28	261044	0	0	0
T29	85093	0	0	0
T30	155732	0	0	0
T31	148365	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1823	0	0
T13	167405	13	0	0
T14	0	14	0	0
T15	0	18	0	0
T16	0	13	0	0
T17	0	33	0	0
T18	0	19	0	0
T19	0	17	0	0
T20	0	6	0	0
T21	0	39	0	0
T22	0	15	0	0
T23	387262	0	0	0
T24	8853	0	0	0
T25	154831	0	0	0
T26	34756	0	0	0
T27	117810	0	0	0
T28	261044	0	0	0
T29	85093	0	0	0
T30	155732	0	0	0
T31	148365	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1978	0	0
T13	167405	17	0	0
T14	0	10	0	0
T15	0	16	0	0
T16	0	13	0	0
T17	0	35	0	0
T18	0	7	0	0
T19	0	9	0	0
T20	0	17	0	0
T21	0	40	0	0
T22	0	25	0	0
T23	387262	0	0	0
T24	8853	0	0	0
T25	154831	0	0	0
T26	34756	0	0	0
T27	117810	0	0	0
T28	261044	0	0	0
T29	85093	0	0	0
T30	155732	0	0	0
T31	148365	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1673	0	0
T13	167405	11	0	0
T14	0	11	0	0
T15	0	17	0	0
T16	0	8	0	0
T17	0	43	0	0
T18	0	19	0	0
T19	0	9	0	0
T20	0	23	0	0
T21	0	24	0	0
T22	0	13	0	0
T23	387262	0	0	0
T24	8853	0	0	0
T25	154831	0	0	0
T26	34756	0	0	0
T27	117810	0	0	0
T28	261044	0	0	0
T29	85093	0	0	0
T30	155732	0	0	0
T31	148365	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1460	0	0
T13	167405	6	0	0
T14	0	18	0	0
T15	0	16	0	0
T17	0	25	0	0
T18	0	20	0	0
T19	0	22	0	0
T20	0	17	0	0
T21	0	40	0	0
T22	0	5	0	0
T23	387262	0	0	0
T24	8853	0	0	0
T25	154831	0	0	0
T26	34756	0	0	0
T27	117810	0	0	0
T28	261044	0	0	0
T29	85093	0	0	0
T30	155732	0	0	0
T31	148365	0	0	0
T32	0	31	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2304	0	0
T13	167405	13	0	0
T14	0	25	0	0
T15	0	14	0	0
T16	0	1	0	0
T17	0	51	0	0
T18	0	17	0	0
T19	0	17	0	0
T20	0	20	0	0
T21	0	40	0	0
T22	0	18	0	0
T23	387262	0	0	0
T24	8853	0	0	0
T25	154831	0	0	0
T26	34756	0	0	0
T27	117810	0	0	0
T28	261044	0	0	0
T29	85093	0	0	0
T30	155732	0	0	0
T31	148365	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1516	0	0
T13	167405	20	0	0
T14	0	12	0	0
T15	0	20	0	0
T16	0	7	0	0
T17	0	30	0	0
T18	0	9	0	0
T19	0	25	0	0
T20	0	18	0	0
T21	0	39	0	0
T22	0	21	0	0
T23	387262	0	0	0
T24	8853	0	0	0
T25	154831	0	0	0
T26	34756	0	0	0
T27	117810	0	0	0
T28	261044	0	0	0
T29	85093	0	0	0
T30	155732	0	0	0
T31	148365	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1810	0	0
T13	167405	12	0	0
T14	0	19	0	0
T15	0	28	0	0
T16	0	8	0	0
T17	0	34	0	0
T18	0	17	0	0
T19	0	23	0	0
T20	0	15	0	0
T21	0	29	0	0
T22	0	23	0	0
T23	387262	0	0	0
T24	8853	0	0	0
T25	154831	0	0	0
T26	34756	0	0	0
T27	117810	0	0	0
T28	261044	0	0	0
T29	85093	0	0	0
T30	155732	0	0	0
T31	148365	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1416	0	0
T13	167405	18	0	0
T14	0	15	0	0
T15	0	18	0	0
T16	0	5	0	0
T17	0	28	0	0
T18	0	7	0	0
T19	0	8	0	0
T20	0	18	0	0
T21	0	39	0	0
T22	0	16	0	0
T23	387262	0	0	0
T24	8853	0	0	0
T25	154831	0	0	0
T26	34756	0	0	0
T27	117810	0	0	0
T28	261044	0	0	0
T29	85093	0	0	0
T30	155732	0	0	0
T31	148365	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1700	0	0
T13	167405	16	0	0
T14	0	24	0	0
T15	0	29	0	0
T16	0	24	0	0
T17	0	42	0	0
T18	0	6	0	0
T19	0	8	0	0
T20	0	15	0	0
T21	0	31	0	0
T22	0	17	0	0
T23	387262	0	0	0
T24	8853	0	0	0
T25	154831	0	0	0
T26	34756	0	0	0
T27	117810	0	0	0
T28	261044	0	0	0
T29	85093	0	0	0
T30	155732	0	0	0
T31	148365	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2438	0	0
T13	167405	23	0	0
T14	0	10	0	0
T15	0	31	0	0
T16	0	6	0	0
T17	0	38	0	0
T23	387262	0	0	0
T24	8853	0	0	0
T25	154831	0	0	0
T26	34756	0	0	0
T27	117810	0	0	0
T28	261044	0	0	0
T29	85093	0	0	0
T30	155732	0	0	0
T31	148365	0	0	0
T42	0	16	0	0
T43	0	28	0	0
T44	0	13	0	0
T45	0	9	0	0
T46	0	5	0	0