Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1222609	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1199636

1

T1

4264

T2

478

T3

4229

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2124840	1			T1	8161		T2	837		T3	8045
values[0x0]	148392	1			T1	264		T2	56		T3	232
values[0x1]	149013	1			T1	262		T2	55		T3	226

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	980385	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1441860

1

T1

5159

T2

577

T3

5113

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7120	1			T1	39		T2	6		T3	34
valid_sources[0x01]	14788	1			T1	40		T2	4		T3	30
valid_sources[0x02]	17821	1			T1	26		T2	4		T3	28
valid_sources[0x03]	15377	1			T1	33		T2	4		T3	39
valid_sources[0x04]	9846	1			T1	33		T2	3		T3	21
valid_sources[0x05]	7149	1			T1	28		T2	2		T3	49
valid_sources[0x06]	7070	1			T1	47		T2	3		T3	53
valid_sources[0x07]	12760	1			T1	25		T3	54		T5	8
valid_sources[0x08]	7337	1			T1	33		T2	5		T3	27
valid_sources[0x09]	8931	1			T1	37		T2	3		T3	35
valid_sources[0x0a]	6831	1			T1	35		T2	4		T3	32
valid_sources[0x0b]	13314	1			T1	41		T2	11		T3	16
valid_sources[0x0c]	7300	1			T1	34		T2	2		T3	18
valid_sources[0x0d]	7168	1			T1	49		T2	5		T3	39
valid_sources[0x0e]	17751	1			T1	23		T2	2		T3	37
valid_sources[0x0f]	12545	1			T1	45		T2	5		T3	59
valid_sources[0x10]	6914	1			T1	36		T2	3		T3	41
valid_sources[0x11]	7277	1			T1	29		T2	2		T3	62
valid_sources[0x12]	7655	1			T1	45		T3	12		T4	4
valid_sources[0x13]	6964	1			T1	34		T2	2		T3	47
valid_sources[0x14]	10234	1			T1	40		T2	8		T3	25
valid_sources[0x15]	7030	1			T1	36		T2	2		T3	34
valid_sources[0x16]	18363	1			T1	24		T2	3		T3	39
valid_sources[0x17]	7746	1			T1	38		T2	2		T3	22
valid_sources[0x18]	8592	1			T1	29		T2	2		T3	28
valid_sources[0x19]	11518	1			T1	29		T2	2		T3	30
valid_sources[0x1a]	7351	1			T1	46		T2	6		T3	24
valid_sources[0x1b]	8067	1			T1	33		T2	3		T3	54
valid_sources[0x1c]	7314	1			T1	27		T2	3		T3	50
valid_sources[0x1d]	7381	1			T1	36		T2	5		T3	20
valid_sources[0x1e]	6940	1			T1	32		T2	4		T3	37
valid_sources[0x1f]	7312	1			T1	38		T2	4		T3	23
valid_sources[0x20]	7055	1			T1	35		T2	5		T3	21
valid_sources[0x21]	8593	1			T1	30		T2	4		T3	24
valid_sources[0x22]	13976	1			T1	26		T2	6		T3	54
valid_sources[0x23]	7180	1			T1	38		T2	8		T3	65
valid_sources[0x24]	6967	1			T1	32		T2	2		T3	17
valid_sources[0x25]	6817	1			T1	34		T3	41		T4	6
valid_sources[0x26]	11404	1			T1	26		T2	2		T3	33
valid_sources[0x27]	7528	1			T1	45		T2	5		T3	39
valid_sources[0x28]	6984	1			T1	33		T2	5		T3	47
valid_sources[0x29]	8087	1			T1	41		T2	3		T3	51
valid_sources[0x2a]	7149	1			T1	29		T2	4		T3	17
valid_sources[0x2b]	14929	1			T1	38		T2	4		T3	46
valid_sources[0x2c]	9884	1			T1	34		T2	8		T3	20
valid_sources[0x2d]	9886	1			T1	41		T2	2		T3	18
valid_sources[0x2e]	7163	1			T1	28		T2	4		T3	32
valid_sources[0x2f]	7127	1			T1	34		T2	6		T3	40
valid_sources[0x30]	14918	1			T1	38		T3	29		T4	5
valid_sources[0x31]	7614	1			T1	46		T2	6		T3	29
valid_sources[0x32]	11511	1			T1	30		T2	1		T3	21
valid_sources[0x33]	11950	1			T1	34		T2	2		T3	38
valid_sources[0x34]	7994	1			T1	28		T2	3		T3	34
valid_sources[0x35]	11647	1			T1	29		T2	3		T3	18
valid_sources[0x36]	6975	1			T1	28		T2	3		T3	33
valid_sources[0x37]	10752	1			T1	29		T2	6		T3	16
valid_sources[0x38]	7225	1			T1	47		T2	4		T3	12
valid_sources[0x39]	13101	1			T1	36		T2	3		T3	9
valid_sources[0x3a]	8415	1			T1	29		T2	5		T3	36
valid_sources[0x3b]	7179	1			T1	43		T2	3		T3	19
valid_sources[0x3c]	11355	1			T1	41		T2	3		T3	30
valid_sources[0x3d]	6908	1			T1	19		T2	3		T3	20
valid_sources[0x3e]	8425	1			T1	26		T2	5		T3	62
valid_sources[0x3f]	13400	1			T1	25		T2	7		T3	18
valid_sources[0x40]	12046	1			T1	25		T2	5		T3	57
valid_sources[0x41]	7278	1			T1	18		T2	2		T3	52
valid_sources[0x42]	7063	1			T1	42		T2	10		T3	44
valid_sources[0x43]	7352	1			T1	50		T2	9		T3	30
valid_sources[0x44]	7404	1			T1	45		T2	2		T3	46
valid_sources[0x45]	13851	1			T1	22		T2	4		T3	45
valid_sources[0x46]	10917	1			T1	40		T2	4		T3	30
valid_sources[0x47]	11713	1			T1	34		T2	3		T3	60
valid_sources[0x48]	11254	1			T1	31		T2	6		T3	15
valid_sources[0x49]	6917	1			T1	31		T2	3		T3	39
valid_sources[0x4a]	7260	1			T1	39		T2	3		T3	41
valid_sources[0x4b]	7895	1			T1	34		T2	2		T3	19
valid_sources[0x4c]	19831	1			T1	28		T2	4		T3	26
valid_sources[0x4d]	7311	1			T1	37		T2	4		T3	30
valid_sources[0x4e]	12040	1			T1	35		T2	2		T3	25
valid_sources[0x4f]	8303	1			T1	31		T2	3		T3	40
valid_sources[0x50]	11549	1			T1	37		T2	6		T3	17
valid_sources[0x51]	9376	1			T1	48		T2	1		T3	58
valid_sources[0x52]	7073	1			T1	38		T2	2		T3	18
valid_sources[0x53]	10953	1			T1	38		T2	3		T3	19
valid_sources[0x54]	6800	1			T1	26		T2	7		T3	24
valid_sources[0x55]	7099	1			T1	44		T2	1		T3	59
valid_sources[0x56]	8435	1			T1	30		T2	7		T3	17
valid_sources[0x57]	7839	1			T1	40		T2	6		T3	53
valid_sources[0x58]	7461	1			T1	41		T2	3		T3	62
valid_sources[0x59]	7255	1			T1	26		T2	3		T3	31
valid_sources[0x5a]	7984	1			T1	34		T2	4		T3	22
valid_sources[0x5b]	16004	1			T1	29		T2	6		T3	38
valid_sources[0x5c]	16624	1			T1	34		T2	2		T3	23
valid_sources[0x5d]	12755	1			T1	24		T2	2		T3	31
valid_sources[0x5e]	16720	1			T1	27		T2	6		T3	52
valid_sources[0x5f]	7017	1			T1	29		T2	5		T3	38
valid_sources[0x60]	7360	1			T1	35		T2	5		T3	31
valid_sources[0x61]	10816	1			T1	41		T2	4		T3	53
valid_sources[0x62]	7051	1			T1	29		T2	4		T3	16
valid_sources[0x63]	7427	1			T1	41		T2	3		T3	19
valid_sources[0x64]	7343	1			T1	26		T2	3		T3	30
valid_sources[0x65]	7872	1			T1	37		T2	5		T3	24
valid_sources[0x66]	14989	1			T1	30		T3	26		T4	19
valid_sources[0x67]	8331	1			T1	16		T2	6		T3	29
valid_sources[0x68]	6925	1			T1	22		T2	5		T3	40
valid_sources[0x69]	9528	1			T1	40		T2	7		T3	29
valid_sources[0x6a]	7159	1			T1	39		T2	2		T3	44
valid_sources[0x6b]	8056	1			T1	32		T2	5		T3	23
valid_sources[0x6c]	11487	1			T1	37		T3	34		T5	15
valid_sources[0x6d]	6955	1			T1	49		T2	3		T3	19
valid_sources[0x6e]	10562	1			T1	32		T2	4		T3	48
valid_sources[0x6f]	8242	1			T1	35		T2	5		T3	26
valid_sources[0x70]	7089	1			T1	45		T2	4		T3	23
valid_sources[0x71]	7083	1			T1	35		T2	4		T3	57
valid_sources[0x72]	8227	1			T1	26		T2	2		T3	55
valid_sources[0x73]	7847	1			T1	34		T2	3		T3	22
valid_sources[0x74]	15307	1			T1	30		T2	6		T3	33
valid_sources[0x75]	7115	1			T1	38		T2	6		T3	41
valid_sources[0x76]	6980	1			T1	37		T2	3		T3	32
valid_sources[0x77]	16113	1			T1	40		T2	4		T3	18
valid_sources[0x78]	7880	1			T1	26		T2	4		T3	19
valid_sources[0x79]	7144	1			T1	38		T2	3		T3	29
valid_sources[0x7a]	8335	1			T1	31		T2	6		T3	20
valid_sources[0x7b]	6908	1			T1	38		T2	6		T3	20
valid_sources[0x7c]	9244	1			T1	44		T2	3		T3	22
valid_sources[0x7d]	9897	1			T1	37		T3	43		T4	1
valid_sources[0x7e]	7018	1			T1	30		T2	4		T3	25
valid_sources[0x7f]	9191	1			T1	30		T2	2		T3	30
valid_sources[0x80]	9767	1			T1	30		T2	2		T3	53

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1059209

1

T1

4051

T2

425

T3

4050

values[0x0]

all_enables

biggest_size

81304

1

T1

121

T2

32

T3

121

values[0x1]

all_enables

biggest_size

59123

1

T1

92

T2

21

T3

58