Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.11	91.11	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	91.11	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.11	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	4	41	91.11

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	3	13	81.25	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	29737	1			T1	17		T2	5		T3	13
auto[PWRUP]	103	1			T12	3		T68	1		T67	1
auto[ONEST_0]	59	1			T12	1		T68	2		T67	2
auto[ONEST_021]	14	1			T70	1		T72	1		T211	1
auto[ONEST_1]	79	1			T12	1		T68	3		T47	2
auto[ONEST_DONE]	1	1			T212	1		-	-		-	-
auto[LP_0]	103	1			T68	1		T67	1		T49	2
auto[LP_021]	24	1			T50	1		T51	1		T53	1
auto[LP_1]	133	1			T12	2		T68	1		T47	1
auto[LP_EVAL]	69	1			T12	2		T68	1		T47	1
auto[LP_SLP]	482	1			T12	3		T68	4		T47	7
auto[LP_PWRUP]	24	1			T67	1		T70	2		T72	1
auto[NP_0]	155	1			T12	1		T47	2		T48	2
auto[NP_021]	33	1			T68	2		T48	1		T70	2
auto[NP_1]	157	1			T12	3		T68	1		T47	1
auto[NP_EVAL]	31	1			T68	1		T49	2		T213	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

12

1

T27

1

T52

1

T214

1

min

29225

1

T1

17

T2

5

T3

13

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29231	1			T1	17		T2	5		T3	13
pow[0x1]	12	1			T68	1		T67	1		T215	1
pow[0x2]	21	1			T12	1		T68	1		T216	2
pow[0x3]	43	1			T12	1		T67	1		T49	3
pow[0x4]	61	1			T49	1		T50	1		T70	2
pow[0x5]	108	1			T12	2		T48	1		T67	1
pow[0x6]	252	1			T12	7		T68	3		T47	3
pow[0x7]	465	1			T12	3		T68	4		T47	3

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

198

1

T68

5

T47

3

T48

1

min

28797

1

T1

17

T2

5

T3

13

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	3	13	81.25

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x3]	0	1	1
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28797	1			T1	17		T2	5		T3	13
pow[0x2]	1	1			T217	1		-	-		-	-
pow[0x4]	1	1			T218	1		-	-		-	-
pow[0x6]	2	1			T213	1		T219	1		-	-
pow[0x7]	2	1			T70	1		T215	1		-	-
pow[0x8]	4	1			T48	1		T211	1		T220	1
pow[0x9]	5	1			T216	1		T214	1		T221	1
pow[0xa]	18	1			T211	2		T218	1		T222	2
pow[0xb]	36	1			T47	1		T48	1		T49	1
pow[0xc]	80	1			T12	2		T67	4		T49	1
pow[0xd]	159	1			T12	1		T68	2		T67	1
pow[0xe]	252	1			T12	3		T48	1		T67	4
pow[0xf]	563	1			T12	14		T68	6		T47	6