Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2183	1			T12	20		T68	7		T47	25
auto[PWRUP]	144	1			T12	1		T47	2		T48	1
auto[ONEST_0]	85	1			T68	1		T47	2		T48	1
auto[ONEST_021]	19	1			T68	3		T48	1		T49	2
auto[ONEST_1]	86	1			T68	1		T49	1		T27	2
auto[ONEST_DONE]	6	1			T49	1		T64	1		T73	1
auto[LP_0]	130	1			T12	2		T47	3		T48	5
auto[LP_021]	31	1			T47	1		T48	1		T27	1
auto[LP_1]	122	1			T48	1		T67	2		T49	3
auto[LP_EVAL]	61	1			T12	2		T48	1		T67	1
auto[LP_SLP]	511	1			T12	7		T68	3		T47	3
auto[LP_PWRUP]	32	1			T47	2		T217	1		T213	1
auto[NP_0]	219	1			T12	1		T68	2		T47	3
auto[NP_021]	57	1			T12	1		T68	1		T47	2
auto[NP_1]	230	1			T12	3		T47	2		T48	1
auto[NP_EVAL]	26	1			T47	1		T49	2		T50	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

6

1

T216

1

T351

1

T352

1

min

1863

1

T12

11

T68

3

T47

23

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1879	1			T12	11		T68	3		T47	23
pow[0x1]	12	1			T218	1		T353	1		T354	1
pow[0x2]	23	1			T213	1		T216	1		T260	1
pow[0x3]	40	1			T49	1		T50	2		T51	1
pow[0x4]	73	1			T67	2		T49	3		T50	2
pow[0x5]	128	1			T68	1		T47	3		T48	1
pow[0x6]	243	1			T12	2		T68	1		T47	4
pow[0x7]	508	1			T12	14		T68	5		T47	6

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

197

1

T12

2

T68

3

T47

4

min

1282

1

T12

6

T68

1

T47

16

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1285	1			T12	6		T68	1		T47	16
pow[0x1]	22	1			T47	1		T49	2		T51	5
pow[0x2]	31	1			T48	1		T52	4		T53	1
pow[0x3]	51	1			T47	2		T49	2		T50	1
pow[0x4]	37	1			T48	1		T341	1		T355	2
pow[0x5]	3	1			T67	1		T73	1		T270	1
pow[0x7]	1	1			T356	1		-	-		-	-
pow[0x8]	3	1			T12	1		T213	1		T357	1
pow[0x9]	9	1			T53	1		T73	1		T351	1
pow[0xa]	21	1			T12	1		T68	1		T67	1
pow[0xb]	39	1			T47	1		T50	1		T70	1
pow[0xc]	67	1			T49	2		T27	2		T51	1
pow[0xd]	133	1			T12	3		T68	1		T47	1
pow[0xe]	297	1			T12	3		T68	3		T47	5
pow[0xf]	598	1			T12	10		T68	3		T47	4