Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1200322	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1172852

1

T1

428

T2

2064

T3

2215

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2075408	1			T1	387		T2	3946		T3	4143
values[0x0]	148626	1			T1	251		T2	120		T3	132
values[0x1]	149140	1			T1	254		T2	128		T3	142

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	961779	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1411395

1

T1

505

T2

2501

T3

2614

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7143	1			T1	5		T2	20		T3	17
valid_sources[0x01]	6987	1			T1	4		T2	20		T3	6
valid_sources[0x02]	11180	1			T1	3		T2	10		T3	16
valid_sources[0x03]	7896	1			T1	1		T2	23		T3	18
valid_sources[0x04]	7224	1			T1	9		T2	12		T3	20
valid_sources[0x05]	7723	1			T1	3		T2	20		T3	4
valid_sources[0x06]	7045	1			T1	3		T2	11		T3	10
valid_sources[0x07]	8386	1			T2	22		T3	13		T5	10
valid_sources[0x08]	10046	1			T1	5		T2	13		T3	10
valid_sources[0x09]	7906	1			T2	23		T3	18		T4	1
valid_sources[0x0a]	7233	1			T1	2		T2	10		T3	12
valid_sources[0x0b]	7621	1			T1	3		T2	19		T3	20
valid_sources[0x0c]	11210	1			T1	3		T2	18		T3	12
valid_sources[0x0d]	7095	1			T1	2		T2	14		T3	11
valid_sources[0x0e]	8603	1			T1	2		T2	14		T3	13
valid_sources[0x0f]	6864	1			T1	2		T2	8		T3	27
valid_sources[0x10]	11342	1			T1	7		T2	16		T3	15
valid_sources[0x11]	7015	1			T1	1		T2	18		T3	22
valid_sources[0x12]	7137	1			T1	3		T2	10		T3	29
valid_sources[0x13]	11631	1			T1	4		T2	11		T3	44
valid_sources[0x14]	11145	1			T1	5		T2	20		T3	6
valid_sources[0x15]	7270	1			T1	2		T2	18		T3	9
valid_sources[0x16]	6924	1			T1	6		T2	8		T3	17
valid_sources[0x17]	7908	1			T1	4		T2	13		T3	18
valid_sources[0x18]	16379	1			T2	12		T3	32		T4	2
valid_sources[0x19]	9227	1			T1	9		T2	19		T3	14
valid_sources[0x1a]	9743	1			T1	8		T2	13		T3	18
valid_sources[0x1b]	12053	1			T1	9		T2	12		T3	9
valid_sources[0x1c]	7047	1			T1	6		T2	6		T3	16
valid_sources[0x1d]	11203	1			T1	2		T2	21		T3	8
valid_sources[0x1e]	7215	1			T1	2		T2	18		T3	16
valid_sources[0x1f]	7059	1			T1	1		T2	10		T3	6
valid_sources[0x20]	10369	1			T1	5		T2	12		T3	19
valid_sources[0x21]	7362	1			T1	2		T2	6		T3	29
valid_sources[0x22]	7273	1			T1	3		T2	16		T3	29
valid_sources[0x23]	6966	1			T1	5		T2	10		T3	21
valid_sources[0x24]	8372	1			T1	4		T2	20		T3	25
valid_sources[0x25]	7266	1			T1	6		T2	17		T3	8
valid_sources[0x26]	7077	1			T1	2		T2	19		T3	14
valid_sources[0x27]	6911	1			T1	4		T2	13		T3	43
valid_sources[0x28]	8067	1			T1	4		T2	15		T3	35
valid_sources[0x29]	27341	1			T1	4		T2	17		T3	23
valid_sources[0x2a]	7137	1			T1	3		T2	16		T3	8
valid_sources[0x2b]	10133	1			T2	7		T3	11		T5	9
valid_sources[0x2c]	6784	1			T1	3		T2	15		T3	14
valid_sources[0x2d]	12062	1			T1	1		T2	17		T3	13
valid_sources[0x2e]	7156	1			T1	2		T2	18		T3	24
valid_sources[0x2f]	6611	1			T2	14		T3	17		T4	1
valid_sources[0x30]	7321	1			T1	3		T2	20		T3	20
valid_sources[0x31]	11369	1			T1	7		T2	16		T3	15
valid_sources[0x32]	7399	1			T1	1		T2	19		T3	10
valid_sources[0x33]	13090	1			T1	3		T2	17		T3	17
valid_sources[0x34]	7161	1			T1	1		T2	16		T3	25
valid_sources[0x35]	7400	1			T1	4		T2	16		T3	14
valid_sources[0x36]	7071	1			T1	8		T2	15		T3	14
valid_sources[0x37]	12591	1			T1	3		T2	18		T3	25
valid_sources[0x38]	6991	1			T1	3		T2	20		T3	15
valid_sources[0x39]	6921	1			T2	12		T3	22		T6	13
valid_sources[0x3a]	6933	1			T1	3		T2	16		T3	13
valid_sources[0x3b]	11556	1			T1	5		T2	16		T3	20
valid_sources[0x3c]	7378	1			T1	5		T2	14		T3	28
valid_sources[0x3d]	7248	1			T1	9		T2	18		T3	25
valid_sources[0x3e]	10118	1			T1	1		T2	19		T3	19
valid_sources[0x3f]	7050	1			T1	3		T2	18		T3	28
valid_sources[0x40]	11069	1			T1	6		T2	21		T3	21
valid_sources[0x41]	15872	1			T1	5		T2	11		T3	21
valid_sources[0x42]	7803	1			T1	1		T2	19		T3	15
valid_sources[0x43]	11092	1			T1	6		T2	14		T3	20
valid_sources[0x44]	6911	1			T1	4		T2	19		T3	10
valid_sources[0x45]	21412	1			T1	4		T2	15		T3	12
valid_sources[0x46]	11390	1			T1	1		T2	16		T3	13
valid_sources[0x47]	11318	1			T1	5		T2	12		T3	7
valid_sources[0x48]	9692	1			T1	3		T2	14		T3	15
valid_sources[0x49]	11122	1			T2	23		T3	30		T5	2
valid_sources[0x4a]	11132	1			T1	3		T2	20		T3	20
valid_sources[0x4b]	6849	1			T1	1		T2	25		T3	20
valid_sources[0x4c]	12684	1			T2	11		T3	13		T4	2
valid_sources[0x4d]	6938	1			T1	9		T2	7		T3	25
valid_sources[0x4e]	7431	1			T1	4		T2	17		T3	11
valid_sources[0x4f]	7139	1			T1	3		T2	20		T3	24
valid_sources[0x50]	10851	1			T1	4		T2	18		T3	11
valid_sources[0x51]	7794	1			T1	1		T2	12		T3	27
valid_sources[0x52]	7109	1			T2	15		T3	21		T4	1
valid_sources[0x53]	7384	1			T1	1		T2	12		T3	3
valid_sources[0x54]	7164	1			T1	4		T2	11		T3	32
valid_sources[0x55]	8126	1			T2	18		T3	20		T6	8
valid_sources[0x56]	8193	1			T1	5		T2	20		T3	30
valid_sources[0x57]	6551	1			T2	18		T3	7		T6	18
valid_sources[0x58]	8091	1			T1	2		T2	15		T3	16
valid_sources[0x59]	7595	1			T1	5		T2	24		T3	6
valid_sources[0x5a]	14184	1			T1	2		T2	12		T3	21
valid_sources[0x5b]	15683	1			T1	5		T2	21		T3	22
valid_sources[0x5c]	19647	1			T1	5		T2	15		T3	8
valid_sources[0x5d]	6856	1			T1	5		T2	21		T3	29
valid_sources[0x5e]	8315	1			T1	3		T2	10		T3	17
valid_sources[0x5f]	6869	1			T1	4		T2	25		T3	9
valid_sources[0x60]	12272	1			T1	1		T2	17		T3	16
valid_sources[0x61]	13217	1			T1	6		T2	16		T3	17
valid_sources[0x62]	7905	1			T1	1		T2	14		T3	10
valid_sources[0x63]	7419	1			T1	7		T2	14		T3	17
valid_sources[0x64]	7965	1			T1	7		T2	25		T3	7
valid_sources[0x65]	7393	1			T1	2		T2	14		T3	16
valid_sources[0x66]	7277	1			T1	9		T2	16		T3	22
valid_sources[0x67]	10258	1			T1	2		T2	17		T3	12
valid_sources[0x68]	6924	1			T1	4		T2	10		T3	19
valid_sources[0x69]	6668	1			T1	4		T2	19		T3	22
valid_sources[0x6a]	7055	1			T1	1		T2	14		T3	13
valid_sources[0x6b]	6741	1			T2	25		T3	17		T5	3
valid_sources[0x6c]	7222	1			T1	5		T2	15		T3	18
valid_sources[0x6d]	12340	1			T1	6		T2	16		T3	14
valid_sources[0x6e]	10496	1			T1	2		T2	20		T3	18
valid_sources[0x6f]	7854	1			T1	2		T2	20		T3	19
valid_sources[0x70]	7334	1			T1	1		T2	15		T3	15
valid_sources[0x71]	9878	1			T1	2		T2	14		T3	10
valid_sources[0x72]	8230	1			T1	1		T2	15		T3	4
valid_sources[0x73]	8869	1			T1	7		T2	15		T3	11
valid_sources[0x74]	7926	1			T1	2		T2	26		T3	16
valid_sources[0x75]	6935	1			T1	7		T2	13		T3	21
valid_sources[0x76]	7858	1			T1	8		T2	16		T3	12
valid_sources[0x77]	6888	1			T1	1		T2	15		T3	20
valid_sources[0x78]	7301	1			T1	1		T2	19		T3	17
valid_sources[0x79]	7426	1			T1	8		T2	11		T3	17
valid_sources[0x7a]	8326	1			T1	4		T2	23		T3	14
valid_sources[0x7b]	12554	1			T1	1		T2	15		T3	23
valid_sources[0x7c]	7220	1			T1	3		T2	16		T3	11
valid_sources[0x7d]	21887	1			T1	1		T2	11		T3	20
valid_sources[0x7e]	7259	1			T1	4		T2	20		T3	24
valid_sources[0x7f]	13381	1			T1	2		T2	20		T3	9
valid_sources[0x80]	7931	1			T1	3		T2	10		T3	23

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1033569

1

T1

190

T2

1976

T3

2097

values[0x0]

all_enables

biggest_size

80778

1

T1

128

T2

57

T3

65

values[0x1]

all_enables

biggest_size

58505

1

T1

110

T2

31

T3

53