Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	30649	1			T1	51		T2	5		T3	11
auto[PWRUP]	112	1			T7	3		T44	1		T35	1
auto[ONEST_0]	81	1			T7	2		T43	1		T35	1
auto[ONEST_021]	17	1			T29	1		T87	1		T38	1
auto[ONEST_1]	82	1			T7	1		T43	1		T44	1
auto[ONEST_DONE]	8	1			T87	1		T188	1		T189	1
auto[LP_0]	113	1			T7	1		T44	1		T29	5
auto[LP_021]	34	1			T1	1		T29	2		T86	1
auto[LP_1]	132	1			T7	1		T43	1		T44	1
auto[LP_EVAL]	79	1			T1	1		T43	2		T29	2
auto[LP_SLP]	501	1			T7	7		T43	6		T44	6
auto[LP_PWRUP]	38	1			T7	1		T29	1		T190	1
auto[NP_0]	149	1			T7	2		T43	1		T44	2
auto[NP_021]	40	1			T44	1		T26	1		T29	1
auto[NP_1]	189	1			T1	3		T43	2		T44	5
auto[NP_EVAL]	44	1			T7	1		T29	2		T30	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

18

1

T7

1

T29

1

T46

1

min

30023

1

T1

50

T2

5

T3

11

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	30026	1			T1	50		T2	5		T3	11
pow[0x1]	2	1			T41	1		T191	1		-	-
pow[0x2]	20	1			T7	1		T30	1		T87	1
pow[0x3]	36	1			T43	1		T29	1		T30	1
pow[0x4]	69	1			T43	1		T44	1		T29	3
pow[0x5]	135	1			T1	1		T44	4		T26	2
pow[0x6]	278	1			T7	2		T43	3		T44	1
pow[0x7]	558	1			T1	3		T7	7		T43	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

194

1

T7

1

T43

3

T44

4

min

29571

1

T1

50

T2

5

T3

11

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29571	1			T1	50		T2	5		T3	11
pow[0x4]	2	1			T192	1		T21	1		-	-
pow[0x6]	1	1			T193	1		-	-		-	-
pow[0x7]	2	1			T194	1		T195	1		-	-
pow[0x8]	7	1			T44	1		T196	1		T197	1
pow[0x9]	11	1			T44	1		T29	1		T86	1
pow[0xa]	18	1			T35	1		T29	1		T86	1
pow[0xb]	43	1			T43	1		T26	1		T198	1
pow[0xc]	82	1			T44	1		T29	3		T87	3
pow[0xd]	135	1			T7	2		T44	2		T29	3
pow[0xe]	320	1			T1	1		T7	5		T43	7
pow[0xf]	634	1			T1	3		T7	5		T43	10