Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2338	1			T1	10		T7	22		T43	10
auto[PWRUP]	133	1			T7	3		T43	2		T44	1
auto[ONEST_0]	74	1			T1	1		T43	3		T44	2
auto[ONEST_021]	24	1			T44	1		T35	1		T86	1
auto[ONEST_1]	83	1			T1	1		T7	1		T35	1
auto[ONEST_DONE]	2	1			T194	1		T345	1		-	-
auto[LP_0]	123	1			T7	3		T43	2		T44	1
auto[LP_021]	29	1			T44	1		T35	1		T86	1
auto[LP_1]	141	1			T43	2		T44	3		T13	2
auto[LP_EVAL]	54	1			T1	1		T7	1		T44	1
auto[LP_SLP]	509	1			T1	2		T7	5		T43	8
auto[LP_PWRUP]	28	1			T7	1		T44	1		T26	1
auto[NP_0]	196	1			T7	4		T43	2		T44	3
auto[NP_021]	43	1			T44	1		T29	2		T86	1
auto[NP_1]	239	1			T1	4		T7	2		T43	3
auto[NP_EVAL]	36	1			T1	1		T35	1		T13	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T44

1

T139

1

T232

1

min

1875

1

T1

10

T7

8

T43

10

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1886	1			T1	10		T7	8		T43	10
pow[0x1]	13	1			T13	1		T29	1		T87	1
pow[0x2]	26	1			T7	1		T44	2		T13	1
pow[0x3]	37	1			T1	2		T7	1		T44	1
pow[0x4]	75	1			T43	2		T35	1		T29	1
pow[0x5]	132	1			T1	1		T7	3		T43	2
pow[0x6]	253	1			T7	6		T43	1		T44	6
pow[0x7]	545	1			T1	3		T7	8		T43	6

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

218

1

T7

3

T43

2

T44

4

min

1323

1

T1

10

T7

2

T43

3

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1324	1			T1	10		T7	2		T43	3
pow[0x1]	5	1			T1	1		T14	1		T41	1
pow[0x2]	23	1			T14	1		T39	1		T41	1
pow[0x3]	36	1			T13	2		T23	4		T26	1
pow[0x4]	62	1			T1	1		T35	1		T13	1
pow[0x5]	1	1			T346	1		-	-		-	-
pow[0x6]	1	1			T347	1		-	-		-	-
pow[0x7]	3	1			T88	1		T348	1		T346	1
pow[0x8]	3	1			T349	1		T192	1		T350	1
pow[0x9]	7	1			T7	1		T44	1		T172	1
pow[0xa]	22	1			T29	1		T86	1		T87	1
pow[0xb]	42	1			T44	1		T29	1		T87	2
pow[0xc]	77	1			T7	1		T44	3		T35	1
pow[0xd]	143	1			T7	4		T44	1		T29	1
pow[0xe]	288	1			T7	2		T43	7		T44	3
pow[0xf]	633	1			T1	5		T7	7		T43	6