Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1859	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1841	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1841	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1741	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2042	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1904	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1790	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1780	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1793	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1911	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1843	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1736	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1848	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1780	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1940	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1620	0	0
adc_en_ctl_rd_A	2147483647	1576	0	0
adc_fsm_rst_rd_A	2147483647	1430	0	0
adc_intr_ctl_rd_A	2147483647	1701	0	0
adc_lp_sample_ctl_rd_A	2147483647	1348	0	0
adc_pd_ctl_rd_A	2147483647	1581	0	0
adc_sample_ctl_rd_A	2147483647	1426	0	0
adc_wakeup_ctl_rd_A	2147483647	1617	0	0
intr_enable_rd_A	2147483647	1982	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1859	0	0
T13	344272	20	0	0
T14	0	23	0	0
T15	0	30	0	0
T16	0	19	0	0
T17	0	34	0	0
T18	0	16	0	0
T19	0	26	0	0
T20	0	50	0	0
T21	0	33	0	0
T22	0	42	0	0
T23	242726	0	0	0
T24	309405	0	0	0
T25	836331	0	0	0
T26	466387	0	0	0
T27	533021	0	0	0
T28	124327	0	0	0
T29	172463	0	0	0
T30	297240	0	0	0
T31	718410	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1841	0	0
T13	344272	15	0	0
T14	0	27	0	0
T15	0	42	0	0
T16	0	13	0	0
T17	0	27	0	0
T18	0	13	0	0
T19	0	26	0	0
T20	0	36	0	0
T21	0	32	0	0
T22	0	40	0	0
T23	242726	0	0	0
T24	309405	0	0	0
T25	836331	0	0	0
T26	466387	0	0	0
T27	533021	0	0	0
T28	124327	0	0	0
T29	172463	0	0	0
T30	297240	0	0	0
T31	718410	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1841	0	0
T13	344272	10	0	0
T14	0	37	0	0
T15	0	16	0	0
T16	0	7	0	0
T17	0	36	0	0
T18	0	11	0	0
T19	0	29	0	0
T20	0	58	0	0
T21	0	42	0	0
T22	0	40	0	0
T23	242726	0	0	0
T24	309405	0	0	0
T25	836331	0	0	0
T26	466387	0	0	0
T27	533021	0	0	0
T28	124327	0	0	0
T29	172463	0	0	0
T30	297240	0	0	0
T31	718410	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1741	0	0
T13	344272	24	0	0
T14	0	19	0	0
T15	0	22	0	0
T16	0	24	0	0
T17	0	51	0	0
T18	0	10	0	0
T19	0	9	0	0
T20	0	33	0	0
T21	0	41	0	0
T22	0	51	0	0
T23	242726	0	0	0
T24	309405	0	0	0
T25	836331	0	0	0
T26	466387	0	0	0
T27	533021	0	0	0
T28	124327	0	0	0
T29	172463	0	0	0
T30	297240	0	0	0
T31	718410	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2042	0	0
T13	344272	33	0	0
T14	0	28	0	0
T15	0	25	0	0
T16	0	22	0	0
T17	0	32	0	0
T18	0	7	0	0
T19	0	26	0	0
T20	0	68	0	0
T21	0	21	0	0
T22	0	30	0	0
T23	242726	0	0	0
T24	309405	0	0	0
T25	836331	0	0	0
T26	466387	0	0	0
T27	533021	0	0	0
T28	124327	0	0	0
T29	172463	0	0	0
T30	297240	0	0	0
T31	718410	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1904	0	0
T13	344272	30	0	0
T14	0	39	0	0
T15	0	32	0	0
T16	0	7	0	0
T17	0	25	0	0
T18	0	11	0	0
T19	0	23	0	0
T20	0	39	0	0
T21	0	29	0	0
T22	0	35	0	0
T23	242726	0	0	0
T24	309405	0	0	0
T25	836331	0	0	0
T26	466387	0	0	0
T27	533021	0	0	0
T28	124327	0	0	0
T29	172463	0	0	0
T30	297240	0	0	0
T31	718410	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1790	0	0
T13	344272	21	0	0
T14	0	23	0	0
T15	0	10	0	0
T16	0	14	0	0
T17	0	43	0	0
T18	0	22	0	0
T19	0	22	0	0
T20	0	37	0	0
T21	0	44	0	0
T22	0	35	0	0
T23	242726	0	0	0
T24	309405	0	0	0
T25	836331	0	0	0
T26	466387	0	0	0
T27	533021	0	0	0
T28	124327	0	0	0
T29	172463	0	0	0
T30	297240	0	0	0
T31	718410	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1780	0	0
T13	344272	19	0	0
T14	0	25	0	0
T15	0	26	0	0
T16	0	6	0	0
T17	0	36	0	0
T18	0	13	0	0
T19	0	16	0	0
T20	0	59	0	0
T21	0	28	0	0
T22	0	49	0	0
T23	242726	0	0	0
T24	309405	0	0	0
T25	836331	0	0	0
T26	466387	0	0	0
T27	533021	0	0	0
T28	124327	0	0	0
T29	172463	0	0	0
T30	297240	0	0	0
T31	718410	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1793	0	0
T13	344272	31	0	0
T14	0	47	0	0
T15	0	30	0	0
T16	0	13	0	0
T17	0	33	0	0
T18	0	21	0	0
T19	0	18	0	0
T20	0	46	0	0
T21	0	40	0	0
T22	0	24	0	0
T23	242726	0	0	0
T24	309405	0	0	0
T25	836331	0	0	0
T26	466387	0	0	0
T27	533021	0	0	0
T28	124327	0	0	0
T29	172463	0	0	0
T30	297240	0	0	0
T31	718410	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1911	0	0
T13	344272	21	0	0
T14	0	28	0	0
T15	0	19	0	0
T16	0	7	0	0
T17	0	31	0	0
T18	0	18	0	0
T19	0	35	0	0
T20	0	48	0	0
T21	0	30	0	0
T22	0	33	0	0
T23	242726	0	0	0
T24	309405	0	0	0
T25	836331	0	0	0
T26	466387	0	0	0
T27	533021	0	0	0
T28	124327	0	0	0
T29	172463	0	0	0
T30	297240	0	0	0
T31	718410	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1843	0	0
T13	344272	23	0	0
T14	0	16	0	0
T15	0	21	0	0
T16	0	20	0	0
T17	0	40	0	0
T18	0	16	0	0
T19	0	17	0	0
T20	0	52	0	0
T21	0	30	0	0
T22	0	37	0	0
T23	242726	0	0	0
T24	309405	0	0	0
T25	836331	0	0	0
T26	466387	0	0	0
T27	533021	0	0	0
T28	124327	0	0	0
T29	172463	0	0	0
T30	297240	0	0	0
T31	718410	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1736	0	0
T13	344272	22	0	0
T14	0	40	0	0
T15	0	14	0	0
T16	0	15	0	0
T17	0	36	0	0
T18	0	13	0	0
T19	0	16	0	0
T20	0	23	0	0
T21	0	39	0	0
T22	0	33	0	0
T23	242726	0	0	0
T24	309405	0	0	0
T25	836331	0	0	0
T26	466387	0	0	0
T27	533021	0	0	0
T28	124327	0	0	0
T29	172463	0	0	0
T30	297240	0	0	0
T31	718410	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1848	0	0
T13	344272	25	0	0
T14	0	30	0	0
T15	0	26	0	0
T16	0	15	0	0
T17	0	48	0	0
T18	0	10	0	0
T19	0	15	0	0
T20	0	34	0	0
T21	0	31	0	0
T22	0	42	0	0
T23	242726	0	0	0
T24	309405	0	0	0
T25	836331	0	0	0
T26	466387	0	0	0
T27	533021	0	0	0
T28	124327	0	0	0
T29	172463	0	0	0
T30	297240	0	0	0
T31	718410	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1780	0	0
T13	344272	20	0	0
T14	0	28	0	0
T15	0	34	0	0
T16	0	11	0	0
T17	0	47	0	0
T18	0	10	0	0
T19	0	17	0	0
T20	0	39	0	0
T21	0	37	0	0
T22	0	38	0	0
T23	242726	0	0	0
T24	309405	0	0	0
T25	836331	0	0	0
T26	466387	0	0	0
T27	533021	0	0	0
T28	124327	0	0	0
T29	172463	0	0	0
T30	297240	0	0	0
T31	718410	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1940	0	0
T13	344272	28	0	0
T14	0	23	0	0
T15	0	27	0	0
T16	0	6	0	0
T17	0	44	0	0
T19	0	23	0	0
T20	0	43	0	0
T21	0	28	0	0
T22	0	39	0	0
T23	242726	0	0	0
T24	309405	0	0	0
T25	836331	0	0	0
T26	466387	0	0	0
T27	533021	0	0	0
T28	124327	0	0	0
T29	172463	0	0	0
T30	297240	0	0	0
T31	718410	0	0	0
T32	0	7	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1620	0	0
T13	344272	11	0	0
T14	0	30	0	0
T15	0	22	0	0
T16	0	6	0	0
T17	0	44	0	0
T18	0	6	0	0
T19	0	19	0	0
T20	0	33	0	0
T21	0	30	0	0
T22	0	38	0	0
T23	242726	0	0	0
T24	309405	0	0	0
T25	836331	0	0	0
T26	466387	0	0	0
T27	533021	0	0	0
T28	124327	0	0	0
T29	172463	0	0	0
T30	297240	0	0	0
T31	718410	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1576	0	0
T13	344272	28	0	0
T14	0	33	0	0
T15	0	42	0	0
T16	0	23	0	0
T17	0	38	0	0
T18	0	10	0	0
T19	0	7	0	0
T20	0	31	0	0
T21	0	45	0	0
T22	0	47	0	0
T23	242726	0	0	0
T24	309405	0	0	0
T25	836331	0	0	0
T26	466387	0	0	0
T27	533021	0	0	0
T28	124327	0	0	0
T29	172463	0	0	0
T30	297240	0	0	0
T31	718410	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1430	0	0
T13	344272	32	0	0
T14	0	51	0	0
T15	0	25	0	0
T16	0	4	0	0
T17	0	25	0	0
T18	0	18	0	0
T19	0	30	0	0
T20	0	37	0	0
T21	0	31	0	0
T22	0	36	0	0
T23	242726	0	0	0
T24	309405	0	0	0
T25	836331	0	0	0
T26	466387	0	0	0
T27	533021	0	0	0
T28	124327	0	0	0
T29	172463	0	0	0
T30	297240	0	0	0
T31	718410	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1701	0	0
T13	344272	19	0	0
T14	0	35	0	0
T15	0	30	0	0
T16	0	8	0	0
T17	0	37	0	0
T18	0	10	0	0
T19	0	32	0	0
T20	0	45	0	0
T21	0	38	0	0
T22	0	41	0	0
T23	242726	0	0	0
T24	309405	0	0	0
T25	836331	0	0	0
T26	466387	0	0	0
T27	533021	0	0	0
T28	124327	0	0	0
T29	172463	0	0	0
T30	297240	0	0	0
T31	718410	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1348	0	0
T13	344272	30	0	0
T14	0	20	0	0
T15	0	21	0	0
T16	0	15	0	0
T17	0	39	0	0
T18	0	10	0	0
T19	0	10	0	0
T20	0	36	0	0
T21	0	52	0	0
T22	0	25	0	0
T23	242726	0	0	0
T24	309405	0	0	0
T25	836331	0	0	0
T26	466387	0	0	0
T27	533021	0	0	0
T28	124327	0	0	0
T29	172463	0	0	0
T30	297240	0	0	0
T31	718410	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1581	0	0
T13	344272	18	0	0
T14	0	34	0	0
T15	0	21	0	0
T16	0	7	0	0
T17	0	39	0	0
T18	0	2	0	0
T19	0	24	0	0
T20	0	30	0	0
T21	0	36	0	0
T22	0	42	0	0
T23	242726	0	0	0
T24	309405	0	0	0
T25	836331	0	0	0
T26	466387	0	0	0
T27	533021	0	0	0
T28	124327	0	0	0
T29	172463	0	0	0
T30	297240	0	0	0
T31	718410	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1426	0	0
T13	344272	18	0	0
T14	0	22	0	0
T15	0	28	0	0
T16	0	11	0	0
T17	0	42	0	0
T18	0	6	0	0
T19	0	25	0	0
T20	0	49	0	0
T21	0	33	0	0
T22	0	26	0	0
T23	242726	0	0	0
T24	309405	0	0	0
T25	836331	0	0	0
T26	466387	0	0	0
T27	533021	0	0	0
T28	124327	0	0	0
T29	172463	0	0	0
T30	297240	0	0	0
T31	718410	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1617	0	0
T13	344272	28	0	0
T14	0	28	0	0
T15	0	11	0	0
T16	0	6	0	0
T17	0	46	0	0
T18	0	14	0	0
T19	0	18	0	0
T20	0	62	0	0
T21	0	30	0	0
T22	0	31	0	0
T23	242726	0	0	0
T24	309405	0	0	0
T25	836331	0	0	0
T26	466387	0	0	0
T27	533021	0	0	0
T28	124327	0	0	0
T29	172463	0	0	0
T30	297240	0	0	0
T31	718410	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1982	0	0
T13	344272	89	0	0
T14	0	39	0	0
T15	0	46	0	0
T16	0	16	0	0
T17	0	58	0	0
T18	0	23	0	0
T19	0	17	0	0
T20	0	53	0	0
T23	242726	0	0	0
T24	309405	0	0	0
T25	836331	0	0	0
T26	466387	0	0	0
T27	533021	0	0	0
T28	124327	0	0	0
T29	172463	0	0	0
T30	297240	0	0	0
T31	718410	0	0	0
T33	0	25	0	0
T34	0	10	0	0