Module Definition
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Module : prim_subreg_ext
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_intr_test 100.00 100.00
tb.dut.u_reg.u_alert_test 100.00 100.00
tb.dut.u_reg.u_adc_fsm_state 100.00 100.00



Module Instance : tb.dut.u_reg.u_intr_test

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.92 100.00 99.70 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_alert_test

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.92 100.00 99.70 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_adc_fsm_state

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.92 100.00 99.70 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_subreg_ext
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
29 1 1
30 1 1

Line Coverage for Instance : tb.dut.u_reg.u_intr_test
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 unreachable
27 unreachable
28 1 1
29 1 1
30 unreachable

Line Coverage for Instance : tb.dut.u_reg.u_alert_test
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 unreachable
27 unreachable
28 1 1
29 1 1
30 unreachable

Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2800
CONT_ASSIGN2900
CONT_ASSIGN3011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 unreachable
29 unreachable
30 1 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%