Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_reg_cdc_arb
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.04 100.00 96.51 95.65 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb 77.58 95.65 78.95 85.71 50.00
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb 83.73 90.00 66.67 78.26 100.00
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb 83.73 90.00 66.67 78.26 100.00
tb.dut.u_reg.u_filter_status_cdc.u_arb 97.72 100.00 95.24 95.65 100.00
tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb 100.00 100.00 100.00
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb 100.00 100.00 100.00

Line Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=2,ResetVal=0,DstWrReq=0 + DataWidth=32,ResetVal,DstWrReq=0 + DataWidth=8,ResetVal=4,DstWrReq=0 + DataWidth=16,ResetVal=155,DstWrReq=0 + DataWidth=1,ResetVal=0,DstWrReq=0 + DataWidth=9,ResetVal=0,DstWrReq=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb

Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN28311100.00
CONT_ASSIGN28411100.00
CONT_ASSIGN29900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 1 1
283 1 1
284 1 1
299 unreachable

Line Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=28,ResetVal=0,DstWrReq=1 + DataWidth=9,ResetVal=0,DstWrReq=1 + DataWidth=5,ResetVal=0,DstWrReq=1 )
Line Coverage for Module self-instances :
SCORELINE
83.73 90.00
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb

SCORELINE
83.73 90.00
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb

SCORELINE
97.72 100.00
tb.dut.u_reg.u_filter_status_cdc.u_arb

SCORELINE
77.58 95.65
tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb

Line No.TotalCoveredPercent
TOTAL5050100.00
CONT_ASSIGN10011100.00
ALWAYS11133100.00
ALWAYS12166100.00
CONT_ASSIGN13511100.00
ALWAYS13966100.00
ALWAYS1551010100.00
CONT_ASSIGN18311100.00
ALWAYS1871919100.00
CONT_ASSIGN22811100.00
CONT_ASSIGN24311100.00
CONT_ASSIGN24411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 1 1
111 1 1
112 1 1
114 1 1
121 1 1
122 1 1
123 1 1
128 1 1
129 1 1
132 1 1
MISSING_ELSE
135 1 1
139 1 1
140 1 1
141 1 1
142 1 1
143 1 1
144 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
158 1 1
159 1 1
160 1 1
161 1 1
162 1 1
163 1 1
164 1 1
MISSING_ELSE
183 1 1
187 1 1
188 1 1
192 1 1
193 1 1
195 1 1
197 1 1
199 1 1
200 1 1
202 1 1
203 1 1
204 1 1
205 1 1
206 1 1
207 1 1
210 1 1
211 1 1
MISSING_ELSE
216 1 1
217 1 1
218 1 1
MISSING_ELSE
228 1 1
243 1 1
244 1 1

Cond Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=2,ResetVal=0,DstWrReq=0 + DataWidth=32,ResetVal,DstWrReq=0 + DataWidth=8,ResetVal=4,DstWrReq=0 + DataWidth=16,ResetVal=155,DstWrReq=0 + DataWidth=1,ResetVal=0,DstWrReq=0 + DataWidth=9,ResetVal=0,DstWrReq=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb

TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable 

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3
Cond Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=28,ResetVal=0,DstWrReq=1 + DataWidth=9,ResetVal=0,DstWrReq=1 + DataWidth=5,ResetVal=0,DstWrReq=1 )
Cond Coverage for Module self-instances :
SCORECOND
83.73 66.67
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb

SCORECOND
83.73 66.67
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb

SCORECOND
97.72 95.24
tb.dut.u_reg.u_filter_status_cdc.u_arb

SCORECOND
77.58 78.95
tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb

TotalCoveredPercent
Conditions434093.02
Logical434093.02
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       123
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT49,T50,T51
11CoveredT49,T52,T50 

 LINE       129
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110CoveredT1,T2,T3
111CoveredT49,T52,T50 

 LINE       135
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT49,T52,T50 

 LINE       157
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       159
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT49,T50,T51
11CoveredT1,T2,T3 

 LINE       161
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       183
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------
-1--2-StatusTests
01CoveredT49,T52,T50
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       207
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       228
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT1,T2,T3
010CoveredT1,T2,T3
100CoveredT1,T2,T3 

 LINE       243
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       243
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3
Branch Coverage for Module : prim_reg_cdc_arb
Line No.TotalCoveredPercent
Branches 23 22 95.65
IF 111 2 2 100.00
IF 121 4 4 100.00
IF 139 4 4 100.00
IF 155 6 6 100.00
CASE 197 7 6 85.71

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	111	if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	121	if ((!rst_dst_ni))
-2-:	123	if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d))
-3-:	129	if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T49,T52,T50
0 0 1 Covered T49,T52,T50
0 0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	139	if ((!rst_dst_ni))
-2-:	141	if (gen_wr_req.dst_lat_d)
-3-:	143	if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	155	if ((!rst_dst_ni))
-2-:	157	if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack))
-3-:	159	if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d))
-4-:	161	if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d))
-5-:	163	if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T1,T2,T3
0 0 1 - - Covered T1,T2,T3
0 0 0 1 - Covered T1,T2,T3
0 0 0 0 1 Covered T1,T2,T3
0 0 0 0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	197	case (gen_wr_req.state_q)
-2-:	200	if (gen_wr_req.dst_req)
-3-:	204	if (dst_update)
-4-:	207	if ((dst_qs_o != dst_qs_i))
-5-:	217	if (gen_wr_req.dst_update_ack)

Branches:
-1--2--3--4--5-StatusTests
StIdle 1 - - - Covered T1,T2,T3
StIdle 0 1 - - Covered T1,T2,T3
StIdle 0 0 1 - Covered T1,T2,T3
StIdle 0 0 0 - Covered T1,T2,T3
StWait - - - 1 Covered T1,T2,T3
StWait - - - 0 Covered T1,T2,T3
default - - - - Not Covered

Assert Coverage for Module : prim_reg_cdc_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_wr_req.DstUpdateReqCheck_A 141541480 1289602 0 3668
gen_wr_req.HwIdSelCheck_A 141541480 4547773 0 0


gen_wr_req.DstUpdateReqCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 141541480 1289602 0 3668
T1 42747 321 0 3
T2 100797 1408 0 3
T3 101211 1402 0 3
T4 3555 60 0 3
T5 237978 2853 0 3
T6 331038 4268 0 3
T7 63111 410 0 3
T8 358305 4186 0 3
T9 387429 4180 0 3
T10 102015 1432 0 3
T11 0 43 0 0
T12 0 36 0 0

gen_wr_req.HwIdSelCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 141541480 4547773 0 0
T1 56996 1094 0 0
T2 134396 4847 0 0
T3 134948 4860 0 0
T4 4740 180 0 0
T5 317304 11095 0 0
T6 441384 15258 0 0
T7 84148 1516 0 0
T8 477740 15909 0 0
T9 516572 16706 0 0
T10 136020 4891 0 0
T11 0 43 0 0
T12 0 36 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%