Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.37	100.00	89.49			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_adc_chn_val_0_cdc	78.29	94.12	85.71			83.33	50.00
tb.dut.u_reg.u_adc_chn_val_1_cdc	78.29	94.12	85.71			83.33	50.00
tb.dut.u_reg.u_filter_status_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_adc_fsm_state_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_adc_en_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_pd_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_sample_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_wakeup_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_fsm_rst_cdc	98.08	100.00	92.31			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.29	94.12	85.71			83.33	50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.01	95.31	67.24			89.47	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.67	94.90	67.39			88.37	100.00
u_src_to_dst_req	60.00	100.00	40.00			100.00	0.00

---

Module Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.29	94.12	85.71			83.33	50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.01	95.31	67.24			89.47	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.67	94.90	67.39			88.37	100.00
u_src_to_dst_req	60.00	100.00	40.00			100.00	0.00

---

Module Instance : tb.dut.u_reg.u_filter_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.74	100.00	92.65			98.31	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.79	100.00	93.48			97.67	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_fsm_state_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.72	98.44	79.69			94.74	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	86.03	97.87	78.57			92.68	75.00
u_src_to_dst_req	93.75	100.00	75.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_en_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=2,ResetVal=0,BitMask=3,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal,BitMask,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal=4,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=16,ResetVal=155,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=28,ResetVal=0,BitMask=268374015,DstWrReq=1,TxnWidth=3 + DataWidth=9,ResetVal=0,BitMask=511,DstWrReq=0,TxnWidth=3 + DataWidth=9,ResetVal=0,BitMask=511,DstWrReq=1,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_en_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_pd_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_lp_sample_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_sample_ctl_cdc

SCORE	COND
78.29	85.71

tb.dut.u_reg.u_adc_chn_val_0_cdc

SCORE	COND
78.29	85.71

tb.dut.u_reg.u_adc_chn_val_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_wakeup_ctl_cdc

SCORE	COND
96.43	85.71

tb.dut.u_reg.u_filter_status_cdc

SCORE	COND
96.43	85.71

tb.dut.u_reg.u_adc_fsm_state_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Covered	T16,T17,T44
1	0	Covered	T4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
98.08	92.31

tb.dut.u_reg.u_adc_fsm_rst_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T5,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T1,T5,T6
1	-	Covered	T1,T5,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	179237947	0	0
DstReqKnown_A	894087324	885367522	0	0
SrcAckBusyChk_A	2147483647	200677	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	179237947	0	0
T1	5751604	54410	0	0
T2	2387711	18590	0	0
T3	5510494	46009	0	0
T4	195501	0	0	0
T5	2881141	16904	0	0
T6	2800847	25739	0	0
T7	6157159	300641	0	0
T8	17823938	16987	0	0
T9	3458646	26112	0	0
T10	3204445	559843	0	0
T11	7490808	64023	0	0
T12	0	52180	0	0
T13	0	93975	0	0
T14	0	14142	0	0
T15	0	34015	0	0
T16	686094	1878	0	0
T17	0	2746	0	0
T18	0	2082	0	0
T19	0	838	0	0
T20	0	565	0	0
T26	124121	0	0	0
T27	575220	0	0	0
T28	475786	0	0	0
T29	474317	0	0	0
T30	224887	0	0	0
T31	396351	0	0	0
T32	388726	0	0	0
T33	901302	0	0	0
T34	896295	0	0	0
T44	0	1629	0	0
T45	0	776	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	894087324	885367522	0	0
T1	1734538	1733030	0	0
T2	241982	239772	0	0
T3	157066	154492	0	0
T4	42302	624	0	0
T5	1126424	1115972	0	0
T6	3066128	3064282	0	0
T7	343850	291070	0	0
T8	2032524	2030808	0	0
T9	3053440	3051360	0	0
T10	1568970	1508442	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	200677	0	0
T1	5751604	42	0	0
T2	2387711	41	0	0
T3	5510494	27	0	0
T4	195501	0	0	0
T5	2881141	140	0	0
T6	2800847	63	0	0
T7	6157159	353	0	0
T8	17823938	42	0	0
T9	3458646	63	0	0
T10	3204445	565	0	0
T11	7490808	39	0	0
T12	0	36	0	0
T13	0	54	0	0
T14	0	54	0	0
T15	0	42	0	0
T16	686094	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	0	4	0	0
T26	124121	0	0	0
T27	575220	0	0	0
T28	475786	0	0	0
T29	474317	0	0	0
T30	224887	0	0	0
T31	396351	0	0	0
T32	388726	0	0	0
T33	901302	0	0	0
T34	896295	0	0	0
T44	0	1	0	0
T46	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	7870616	7870590	0	0
T2	3267394	3267264	0	0
T3	7540676	7540442	0	0
T4	5083026	5044546	0	0
T5	3942614	3941652	0	0
T6	3832738	3832712	0	0
T7	8425586	8420126	0	0
T8	24390652	24390444	0	0
T9	4732884	4732858	0	0
T10	4385030	4384406	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		17	16	94.12
CONT_ASSIGN	65	0	0
ALWAYS	71	5	4	80.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	7	7	100.00
CONT_ASSIGN	150	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65		unreachable
71	1	1
72	1	1
73	1	1
74		unreachable
75	1	1
76	0	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123		unreachable
124		unreachable
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150		unreachable
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc

	Total	Covered	Percent
Conditions	7	6	85.71
Logical	7	6	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Unreachable

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T4,T1,T2
1	0	Excluded		VC_COV_UNR
1	1	Excluded		VC_COV_UNR

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Covered	T4,T1,T2
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Not Covered
1	0	Excluded		VC_COV_UNR
1	1	Excluded		VC_COV_UNR

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T4,T1,T2
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc

	Line No.	Total	Covered	Percent
Branches		6	5	83.33
IF	71	3	2	66.67
IF	115	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Unreachable
0	0	1	Not Covered
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Unreachable
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	2	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	2	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	0	0	0
DstReqKnown_A	34387974	34052597	0	0
SrcAckBusyChk_A	2147483647	0	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34387974	34052597	0	0
T1	66713	66655	0	0
T2	9307	9222	0	0
T3	6041	5942	0	0
T4	1627	24	0	0
T5	43324	42922	0	0
T6	117928	117857	0	0
T7	13225	11195	0	0
T8	78174	78108	0	0
T9	117440	117360	0	0
T10	60345	58017	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	302716	302715	0	0
T2	125669	125664	0	0
T3	290026	290017	0	0
T4	195501	194021	0	0
T5	151639	151602	0	0
T6	147413	147412	0	0
T7	324061	323851	0	0
T8	938102	938094	0	0
T9	182034	182033	0	0
T10	168655	168631	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		17	16	94.12
CONT_ASSIGN	65	0	0
ALWAYS	71	5	4	80.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	7	7	100.00
CONT_ASSIGN	150	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65		unreachable
71	1	1
72	1	1
73	1	1
74		unreachable
75	1	1
76	0	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123		unreachable
124		unreachable
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150		unreachable
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc

	Total	Covered	Percent
Conditions	7	6	85.71
Logical	7	6	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Unreachable

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T4,T1,T2
1	0	Excluded		VC_COV_UNR
1	1	Excluded		VC_COV_UNR

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Covered	T4,T1,T2
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Not Covered
1	0	Excluded		VC_COV_UNR
1	1	Excluded		VC_COV_UNR

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T4,T1,T2
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc

	Line No.	Total	Covered	Percent
Branches		6	5	83.33
IF	71	3	2	66.67
IF	115	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Unreachable
0	0	1	Not Covered
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Unreachable
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	2	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	2	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	0	0	0
DstReqKnown_A	34387974	34052597	0	0
SrcAckBusyChk_A	2147483647	0	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34387974	34052597	0	0
T1	66713	66655	0	0
T2	9307	9222	0	0
T3	6041	5942	0	0
T4	1627	24	0	0
T5	43324	42922	0	0
T6	117928	117857	0	0
T7	13225	11195	0	0
T8	78174	78108	0	0
T9	117440	117360	0	0
T10	60345	58017	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	302716	302715	0	0
T2	125669	125664	0	0
T3	290026	290017	0	0
T4	195501	194021	0	0
T5	151639	151602	0	0
T6	147413	147412	0	0
T7	324061	323851	0	0
T8	938102	938094	0	0
T9	182034	182033	0	0
T10	168655	168631	0	0

Line Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T5,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Not Covered
1	1	Covered	T1,T5,T6

---

Branch Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	62361345	0	0
DstReqKnown_A	34387974	34052597	0	0
SrcAckBusyChk_A	2147483647	68762	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	62361345	0	0
T1	302716	258802	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T5	151639	9383	0	0
T6	147413	90219	0	0
T7	324061	0	0	0
T8	938102	59434	0	0
T9	182034	118273	0	0
T10	168655	68609	0	0
T11	416156	0	0	0
T12	0	213472	0	0
T13	0	408129	0	0
T14	0	62604	0	0
T15	0	204575	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34387974	34052597	0	0
T1	66713	66655	0	0
T2	9307	9222	0	0
T3	6041	5942	0	0
T4	1627	24	0	0
T5	43324	42922	0	0
T6	117928	117857	0	0
T7	13225	11195	0	0
T8	78174	78108	0	0
T9	117440	117360	0	0
T10	60345	58017	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	68762	0	0
T1	302716	167	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T5	151639	83	0	0
T6	147413	232	0	0
T7	324061	0	0	0
T8	938102	142	0	0
T9	182034	224	0	0
T10	168655	74	0	0
T11	416156	0	0	0
T12	0	145	0	0
T13	0	234	0	0
T14	0	231	0	0
T15	0	246	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	302716	302715	0	0
T2	125669	125664	0	0
T3	290026	290017	0	0
T4	195501	194021	0	0
T5	151639	151602	0	0
T6	147413	147412	0	0
T7	324061	323851	0	0
T8	938102	938094	0	0
T9	182034	182033	0	0
T10	168655	168631	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc

	Line No.	Total	Covered	Percent
TOTAL		21	21	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150		unreachable
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Covered	T16,T17,T44
1	0	Unreachable

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T16,T17,T44
1	1	Covered	T16,T17,T44

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T17,T44

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T16,T17,T44
1	1	Covered	T16,T17,T44

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T16,T17,T44
0	0	1	Covered	T16,T17,T44
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T16,T17,T44
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	88573	0	0
DstReqKnown_A	34387974	34052597	0	0
SrcAckBusyChk_A	2147483647	87	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	88573	0	0
T16	686094	1878	0	0
T17	0	2746	0	0
T18	0	2082	0	0
T19	0	838	0	0
T20	0	565	0	0
T26	124121	0	0	0
T27	575220	0	0	0
T28	475786	0	0	0
T29	474317	0	0	0
T30	224887	0	0	0
T31	396351	0	0	0
T32	388726	0	0	0
T33	901302	0	0	0
T34	896295	0	0	0
T44	0	1629	0	0
T45	0	776	0	0
T46	0	1741	0	0
T47	0	2132	0	0
T48	0	2206	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34387974	34052597	0	0
T1	66713	66655	0	0
T2	9307	9222	0	0
T3	6041	5942	0	0
T4	1627	24	0	0
T5	43324	42922	0	0
T6	117928	117857	0	0
T7	13225	11195	0	0
T8	78174	78108	0	0
T9	117440	117360	0	0
T10	60345	58017	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	87	0	0
T16	686094	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	0	4	0	0
T26	124121	0	0	0
T27	575220	0	0	0
T28	475786	0	0	0
T29	474317	0	0	0
T30	224887	0	0	0
T31	396351	0	0	0
T32	388726	0	0	0
T33	901302	0	0	0
T34	896295	0	0	0
T44	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	302716	302715	0	0
T2	125669	125664	0	0
T3	290026	290017	0	0
T4	195501	194021	0	0
T5	151639	151602	0	0
T6	147413	147412	0	0
T7	324061	323851	0	0
T8	938102	938094	0	0
T9	182034	182033	0	0
T10	168655	168631	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	33673292	0	0
DstReqKnown_A	34387974	34052597	0	0
SrcAckBusyChk_A	2147483647	37096	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	33673292	0	0
T1	302716	6891	0	0
T2	125669	18590	0	0
T3	290026	46009	0	0
T5	151639	14638	0	0
T6	147413	3925	0	0
T7	324061	176264	0	0
T8	938102	2514	0	0
T9	182034	4427	0	0
T10	168655	337695	0	0
T11	416156	64023	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34387974	34052597	0	0
T1	66713	66655	0	0
T2	9307	9222	0	0
T3	6041	5942	0	0
T4	1627	24	0	0
T5	43324	42922	0	0
T6	117928	117857	0	0
T7	13225	11195	0	0
T8	78174	78108	0	0
T9	117440	117360	0	0
T10	60345	58017	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	37096	0	0
T1	302716	6	0	0
T2	125669	41	0	0
T3	290026	27	0	0
T5	151639	122	0	0
T6	147413	9	0	0
T7	324061	206	0	0
T8	938102	6	0	0
T9	182034	9	0	0
T10	168655	340	0	0
T11	416156	39	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	302716	302715	0	0
T2	125669	125664	0	0
T3	290026	290017	0	0
T4	195501	194021	0	0
T5	151639	151602	0	0
T6	147413	147412	0	0
T7	324061	323851	0	0
T8	938102	938094	0	0
T9	182034	182033	0	0
T10	168655	168631	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	15316123	0	0
DstReqKnown_A	34387974	34052597	0	0
SrcAckBusyChk_A	2147483647	17305	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15316123	0	0
T1	302716	2813	0	0
T2	125669	8633	0	0
T3	290026	22851	0	0
T5	151639	4868	0	0
T6	147413	2482	0	0
T7	324061	83428	0	0
T8	938102	1480	0	0
T9	182034	2634	0	0
T10	168655	161731	0	0
T11	416156	30618	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34387974	34052597	0	0
T1	66713	66655	0	0
T2	9307	9222	0	0
T3	6041	5942	0	0
T4	1627	24	0	0
T5	43324	42922	0	0
T6	117928	117857	0	0
T7	13225	11195	0	0
T8	78174	78108	0	0
T9	117440	117360	0	0
T10	60345	58017	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	17305	0	0
T1	302716	4	0	0
T2	125669	20	0	0
T3	290026	13	0	0
T5	151639	41	0	0
T6	147413	6	0	0
T7	324061	103	0	0
T8	938102	4	0	0
T9	182034	6	0	0
T10	168655	169	0	0
T11	416156	19	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	302716	302715	0	0
T2	125669	125664	0	0
T3	290026	290017	0	0
T4	195501	194021	0	0
T5	151639	151602	0	0
T6	147413	147412	0	0
T7	324061	323851	0	0
T8	938102	938094	0	0
T9	182034	182033	0	0
T10	168655	168631	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T4,T1,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	11661814	0	0
DstReqKnown_A	34387974	34052597	0	0
SrcAckBusyChk_A	2147483647	13313	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	11661814	0	0
T1	302716	2349	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T4	195501	352	0	0
T5	151639	240	0	0
T6	147413	1140	0	0
T7	324061	84536	0	0
T8	938102	769	0	0
T9	182034	958	0	0
T10	168655	135041	0	0
T12	0	2834	0	0
T13	0	4919	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34387974	34052597	0	0
T1	66713	66655	0	0
T2	9307	9222	0	0
T3	6041	5942	0	0
T4	1627	24	0	0
T5	43324	42922	0	0
T6	117928	117857	0	0
T7	13225	11195	0	0
T8	78174	78108	0	0
T9	117440	117360	0	0
T10	60345	58017	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13313	0	0
T1	302716	2	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T4	195501	1	0	0
T5	151639	2	0	0
T6	147413	3	0	0
T7	324061	103	0	0
T8	938102	2	0	0
T9	182034	3	0	0
T10	168655	140	0	0
T12	0	2	0	0
T13	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	302716	302715	0	0
T2	125669	125664	0	0
T3	290026	290017	0	0
T4	195501	194021	0	0
T5	151639	151602	0	0
T6	147413	147412	0	0
T7	324061	323851	0	0
T8	938102	938094	0	0
T9	182034	182033	0	0
T10	168655	168631	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T4,T1,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	11764913	0	0
DstReqKnown_A	34387974	34052597	0	0
SrcAckBusyChk_A	2147483647	13357	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	11764913	0	0
T1	302716	2370	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T4	195501	356	0	0
T5	151639	244	0	0
T6	147413	1158	0	0
T7	324061	85633	0	0
T8	938102	773	0	0
T9	182034	978	0	0
T10	168655	136418	0	0
T12	0	2838	0	0
T13	0	4949	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34387974	34052597	0	0
T1	66713	66655	0	0
T2	9307	9222	0	0
T3	6041	5942	0	0
T4	1627	24	0	0
T5	43324	42922	0	0
T6	117928	117857	0	0
T7	13225	11195	0	0
T8	78174	78108	0	0
T9	117440	117360	0	0
T10	60345	58017	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13357	0	0
T1	302716	2	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T4	195501	1	0	0
T5	151639	2	0	0
T6	147413	3	0	0
T7	324061	103	0	0
T8	938102	2	0	0
T9	182034	3	0	0
T10	168655	140	0	0
T12	0	2	0	0
T13	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	302716	302715	0	0
T2	125669	125664	0	0
T3	290026	290017	0	0
T4	195501	194021	0	0
T5	151639	151602	0	0
T6	147413	147412	0	0
T7	324061	323851	0	0
T8	938102	938094	0	0
T9	182034	182033	0	0
T10	168655	168631	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T5,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1770870	0	0
DstReqKnown_A	34387974	34052597	0	0
SrcAckBusyChk_A	2147483647	2019	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1770870	0	0
T1	302716	2723	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T5	151639	139	0	0
T6	147413	1314	0	0
T7	324061	719	0	0
T8	938102	837	0	0
T9	182034	1342	0	0
T10	168655	1961	0	0
T11	416156	0	0	0
T12	0	2902	0	0
T13	0	5451	0	0
T14	0	855	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34387974	34052597	0	0
T1	66713	66655	0	0
T2	9307	9222	0	0
T3	6041	5942	0	0
T4	1627	24	0	0
T5	43324	42922	0	0
T6	117928	117857	0	0
T7	13225	11195	0	0
T8	78174	78108	0	0
T9	117440	117360	0	0
T10	60345	58017	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2019	0	0
T1	302716	2	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T5	151639	1	0	0
T6	147413	3	0	0
T7	324061	1	0	0
T8	938102	2	0	0
T9	182034	3	0	0
T10	168655	2	0	0
T11	416156	0	0	0
T12	0	2	0	0
T13	0	3	0	0
T14	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	302716	302715	0	0
T2	125669	125664	0	0
T3	290026	290017	0	0
T4	195501	194021	0	0
T5	151639	151602	0	0
T6	147413	147412	0	0
T7	324061	323851	0	0
T8	938102	938094	0	0
T9	182034	182033	0	0
T10	168655	168631	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T5,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1615119	0	0
DstReqKnown_A	34387974	34052597	0	0
SrcAckBusyChk_A	2147483647	1872	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1615119	0	0
T1	302716	2711	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T5	151639	137	0	0
T6	147413	1279	0	0
T7	324061	0	0	0
T8	938102	833	0	0
T9	182034	1318	0	0
T10	168655	828	0	0
T11	416156	0	0	0
T12	0	2898	0	0
T13	0	5424	0	0
T14	0	830	0	0
T15	0	2583	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34387974	34052597	0	0
T1	66713	66655	0	0
T2	9307	9222	0	0
T3	6041	5942	0	0
T4	1627	24	0	0
T5	43324	42922	0	0
T6	117928	117857	0	0
T7	13225	11195	0	0
T8	78174	78108	0	0
T9	117440	117360	0	0
T10	60345	58017	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1872	0	0
T1	302716	2	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T5	151639	1	0	0
T6	147413	3	0	0
T7	324061	0	0	0
T8	938102	2	0	0
T9	182034	3	0	0
T10	168655	1	0	0
T11	416156	0	0	0
T12	0	2	0	0
T13	0	3	0	0
T14	0	3	0	0
T15	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	302716	302715	0	0
T2	125669	125664	0	0
T3	290026	290017	0	0
T4	195501	194021	0	0
T5	151639	151602	0	0
T6	147413	147412	0	0
T7	324061	323851	0	0
T8	938102	938094	0	0
T9	182034	182033	0	0
T10	168655	168631	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T5,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1682560	0	0
DstReqKnown_A	34387974	34052597	0	0
SrcAckBusyChk_A	2147483647	1910	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1682560	0	0
T1	302716	2696	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T5	151639	135	0	0
T6	147413	1245	0	0
T7	324061	0	0	0
T8	938102	829	0	0
T9	182034	1295	0	0
T10	168655	821	0	0
T11	416156	0	0	0
T12	0	2894	0	0
T13	0	5386	0	0
T14	0	819	0	0
T15	0	2553	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34387974	34052597	0	0
T1	66713	66655	0	0
T2	9307	9222	0	0
T3	6041	5942	0	0
T4	1627	24	0	0
T5	43324	42922	0	0
T6	117928	117857	0	0
T7	13225	11195	0	0
T8	78174	78108	0	0
T9	117440	117360	0	0
T10	60345	58017	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1910	0	0
T1	302716	2	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T5	151639	1	0	0
T6	147413	3	0	0
T7	324061	0	0	0
T8	938102	2	0	0
T9	182034	3	0	0
T10	168655	1	0	0
T11	416156	0	0	0
T12	0	2	0	0
T13	0	3	0	0
T14	0	3	0	0
T15	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	302716	302715	0	0
T2	125669	125664	0	0
T3	290026	290017	0	0
T4	195501	194021	0	0
T5	151639	151602	0	0
T6	147413	147412	0	0
T7	324061	323851	0	0
T8	938102	938094	0	0
T9	182034	182033	0	0
T10	168655	168631	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T5,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1643407	0	0
DstReqKnown_A	34387974	34052597	0	0
SrcAckBusyChk_A	2147483647	1901	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1643407	0	0
T1	302716	2678	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T5	151639	133	0	0
T6	147413	1211	0	0
T7	324061	0	0	0
T8	938102	825	0	0
T9	182034	1274	0	0
T10	168655	808	0	0
T11	416156	0	0	0
T12	0	2890	0	0
T13	0	5358	0	0
T14	0	791	0	0
T15	0	2538	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34387974	34052597	0	0
T1	66713	66655	0	0
T2	9307	9222	0	0
T3	6041	5942	0	0
T4	1627	24	0	0
T5	43324	42922	0	0
T6	117928	117857	0	0
T7	13225	11195	0	0
T8	78174	78108	0	0
T9	117440	117360	0	0
T10	60345	58017	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1901	0	0
T1	302716	2	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T5	151639	1	0	0
T6	147413	3	0	0
T7	324061	0	0	0
T8	938102	2	0	0
T9	182034	3	0	0
T10	168655	1	0	0
T11	416156	0	0	0
T12	0	2	0	0
T13	0	3	0	0
T14	0	3	0	0
T15	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	302716	302715	0	0
T2	125669	125664	0	0
T3	290026	290017	0	0
T4	195501	194021	0	0
T5	151639	151602	0	0
T6	147413	147412	0	0
T7	324061	323851	0	0
T8	938102	938094	0	0
T9	182034	182033	0	0
T10	168655	168631	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T5,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1606648	0	0
DstReqKnown_A	34387974	34052597	0	0
SrcAckBusyChk_A	2147483647	1885	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1606648	0	0
T1	302716	2651	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T5	151639	131	0	0
T6	147413	1172	0	0
T7	324061	0	0	0
T8	938102	821	0	0
T9	182034	1254	0	0
T10	168655	798	0	0
T11	416156	0	0	0
T12	0	2886	0	0
T13	0	5334	0	0
T14	0	768	0	0
T15	0	2510	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34387974	34052597	0	0
T1	66713	66655	0	0
T2	9307	9222	0	0
T3	6041	5942	0	0
T4	1627	24	0	0
T5	43324	42922	0	0
T6	117928	117857	0	0
T7	13225	11195	0	0
T8	78174	78108	0	0
T9	117440	117360	0	0
T10	60345	58017	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1885	0	0
T1	302716	2	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T5	151639	1	0	0
T6	147413	3	0	0
T7	324061	0	0	0
T8	938102	2	0	0
T9	182034	3	0	0
T10	168655	1	0	0
T11	416156	0	0	0
T12	0	2	0	0
T13	0	3	0	0
T14	0	3	0	0
T15	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	302716	302715	0	0
T2	125669	125664	0	0
T3	290026	290017	0	0
T4	195501	194021	0	0
T5	151639	151602	0	0
T6	147413	147412	0	0
T7	324061	323851	0	0
T8	938102	938094	0	0
T9	182034	182033	0	0
T10	168655	168631	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T5,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1657726	0	0
DstReqKnown_A	34387974	34052597	0	0
SrcAckBusyChk_A	2147483647	1918	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1657726	0	0
T1	302716	2635	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T5	151639	129	0	0
T6	147413	1145	0	0
T7	324061	0	0	0
T8	938102	817	0	0
T9	182034	1232	0	0
T10	168655	784	0	0
T11	416156	0	0	0
T12	0	2882	0	0
T13	0	5296	0	0
T14	0	738	0	0
T15	0	2488	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34387974	34052597	0	0
T1	66713	66655	0	0
T2	9307	9222	0	0
T3	6041	5942	0	0
T4	1627	24	0	0
T5	43324	42922	0	0
T6	117928	117857	0	0
T7	13225	11195	0	0
T8	78174	78108	0	0
T9	117440	117360	0	0
T10	60345	58017	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1918	0	0
T1	302716	2	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T5	151639	1	0	0
T6	147413	3	0	0
T7	324061	0	0	0
T8	938102	2	0	0
T9	182034	3	0	0
T10	168655	1	0	0
T11	416156	0	0	0
T12	0	2	0	0
T13	0	3	0	0
T14	0	3	0	0
T15	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	302716	302715	0	0
T2	125669	125664	0	0
T3	290026	290017	0	0
T4	195501	194021	0	0
T5	151639	151602	0	0
T6	147413	147412	0	0
T7	324061	323851	0	0
T8	938102	938094	0	0
T9	182034	182033	0	0
T10	168655	168631	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T5,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1650066	0	0
DstReqKnown_A	34387974	34052597	0	0
SrcAckBusyChk_A	2147483647	1901	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1650066	0	0
T1	302716	2615	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T5	151639	127	0	0
T6	147413	1102	0	0
T7	324061	0	0	0
T8	938102	813	0	0
T9	182034	1215	0	0
T10	168655	778	0	0
T11	416156	0	0	0
T12	0	2878	0	0
T13	0	5254	0	0
T14	0	713	0	0
T15	0	2472	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34387974	34052597	0	0
T1	66713	66655	0	0
T2	9307	9222	0	0
T3	6041	5942	0	0
T4	1627	24	0	0
T5	43324	42922	0	0
T6	117928	117857	0	0
T7	13225	11195	0	0
T8	78174	78108	0	0
T9	117440	117360	0	0
T10	60345	58017	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1901	0	0
T1	302716	2	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T5	151639	1	0	0
T6	147413	3	0	0
T7	324061	0	0	0
T8	938102	2	0	0
T9	182034	3	0	0
T10	168655	1	0	0
T11	416156	0	0	0
T12	0	2	0	0
T13	0	3	0	0
T14	0	3	0	0
T15	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	302716	302715	0	0
T2	125669	125664	0	0
T3	290026	290017	0	0
T4	195501	194021	0	0
T5	151639	151602	0	0
T6	147413	147412	0	0
T7	324061	323851	0	0
T8	938102	938094	0	0
T9	182034	182033	0	0
T10	168655	168631	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T5,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1652690	0	0
DstReqKnown_A	34387974	34052597	0	0
SrcAckBusyChk_A	2147483647	1911	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1652690	0	0
T1	302716	2585	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T5	151639	125	0	0
T6	147413	1073	0	0
T7	324061	0	0	0
T8	938102	809	0	0
T9	182034	1196	0	0
T10	168655	768	0	0
T11	416156	0	0	0
T12	0	2874	0	0
T13	0	5231	0	0
T14	0	685	0	0
T15	0	2456	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34387974	34052597	0	0
T1	66713	66655	0	0
T2	9307	9222	0	0
T3	6041	5942	0	0
T4	1627	24	0	0
T5	43324	42922	0	0
T6	117928	117857	0	0
T7	13225	11195	0	0
T8	78174	78108	0	0
T9	117440	117360	0	0
T10	60345	58017	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1911	0	0
T1	302716	2	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T5	151639	1	0	0
T6	147413	3	0	0
T7	324061	0	0	0
T8	938102	2	0	0
T9	182034	3	0	0
T10	168655	1	0	0
T11	416156	0	0	0
T12	0	2	0	0
T13	0	3	0	0
T14	0	3	0	0
T15	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	302716	302715	0	0
T2	125669	125664	0	0
T3	290026	290017	0	0
T4	195501	194021	0	0
T5	151639	151602	0	0
T6	147413	147412	0	0
T7	324061	323851	0	0
T8	938102	938094	0	0
T9	182034	182033	0	0
T10	168655	168631	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T5,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1732397	0	0
DstReqKnown_A	34387974	34052597	0	0
SrcAckBusyChk_A	2147483647	2022	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1732397	0	0
T1	302716	2558	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T5	151639	123	0	0
T6	147413	1174	0	0
T7	324061	704	0	0
T8	938102	805	0	0
T9	182034	1176	0	0
T10	168655	1867	0	0
T11	416156	0	0	0
T12	0	2870	0	0
T13	0	5193	0	0
T14	0	663	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34387974	34052597	0	0
T1	66713	66655	0	0
T2	9307	9222	0	0
T3	6041	5942	0	0
T4	1627	24	0	0
T5	43324	42922	0	0
T6	117928	117857	0	0
T7	13225	11195	0	0
T8	78174	78108	0	0
T9	117440	117360	0	0
T10	60345	58017	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2022	0	0
T1	302716	2	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T5	151639	1	0	0
T6	147413	3	0	0
T7	324061	1	0	0
T8	938102	2	0	0
T9	182034	3	0	0
T10	168655	2	0	0
T11	416156	0	0	0
T12	0	2	0	0
T13	0	3	0	0
T14	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	302716	302715	0	0
T2	125669	125664	0	0
T3	290026	290017	0	0
T4	195501	194021	0	0
T5	151639	151602	0	0
T6	147413	147412	0	0
T7	324061	323851	0	0
T8	938102	938094	0	0
T9	182034	182033	0	0
T10	168655	168631	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T5,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1612202	0	0
DstReqKnown_A	34387974	34052597	0	0
SrcAckBusyChk_A	2147483647	1893	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1612202	0	0
T1	302716	2536	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T5	151639	121	0	0
T6	147413	1144	0	0
T7	324061	0	0	0
T8	938102	801	0	0
T9	182034	1147	0	0
T10	168655	739	0	0
T11	416156	0	0	0
T12	0	2866	0	0
T13	0	5169	0	0
T14	0	807	0	0
T15	0	2412	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34387974	34052597	0	0
T1	66713	66655	0	0
T2	9307	9222	0	0
T3	6041	5942	0	0
T4	1627	24	0	0
T5	43324	42922	0	0
T6	117928	117857	0	0
T7	13225	11195	0	0
T8	78174	78108	0	0
T9	117440	117360	0	0
T10	60345	58017	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1893	0	0
T1	302716	2	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T5	151639	1	0	0
T6	147413	3	0	0
T7	324061	0	0	0
T8	938102	2	0	0
T9	182034	3	0	0
T10	168655	1	0	0
T11	416156	0	0	0
T12	0	2	0	0
T13	0	3	0	0
T14	0	3	0	0
T15	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	302716	302715	0	0
T2	125669	125664	0	0
T3	290026	290017	0	0
T4	195501	194021	0	0
T5	151639	151602	0	0
T6	147413	147412	0	0
T7	324061	323851	0	0
T8	938102	938094	0	0
T9	182034	182033	0	0
T10	168655	168631	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T5,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1567056	0	0
DstReqKnown_A	34387974	34052597	0	0
SrcAckBusyChk_A	2147483647	1875	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1567056	0	0
T1	302716	2514	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T5	151639	119	0	0
T6	147413	1120	0	0
T7	324061	0	0	0
T8	938102	797	0	0
T9	182034	1112	0	0
T10	168655	724	0	0
T11	416156	0	0	0
T12	0	2862	0	0
T13	0	5138	0	0
T14	0	786	0	0
T15	0	2385	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34387974	34052597	0	0
T1	66713	66655	0	0
T2	9307	9222	0	0
T3	6041	5942	0	0
T4	1627	24	0	0
T5	43324	42922	0	0
T6	117928	117857	0	0
T7	13225	11195	0	0
T8	78174	78108	0	0
T9	117440	117360	0	0
T10	60345	58017	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1875	0	0
T1	302716	2	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T5	151639	1	0	0
T6	147413	3	0	0
T7	324061	0	0	0
T8	938102	2	0	0
T9	182034	3	0	0
T10	168655	1	0	0
T11	416156	0	0	0
T12	0	2	0	0
T13	0	3	0	0
T14	0	3	0	0
T15	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	302716	302715	0	0
T2	125669	125664	0	0
T3	290026	290017	0	0
T4	195501	194021	0	0
T5	151639	151602	0	0
T6	147413	147412	0	0
T7	324061	323851	0	0
T8	938102	938094	0	0
T9	182034	182033	0	0
T10	168655	168631	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T5,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1650186	0	0
DstReqKnown_A	34387974	34052597	0	0
SrcAckBusyChk_A	2147483647	1919	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1650186	0	0
T1	302716	2490	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T5	151639	117	0	0
T6	147413	1215	0	0
T7	324061	0	0	0
T8	938102	793	0	0
T9	182034	1084	0	0
T10	168655	716	0	0
T11	416156	0	0	0
T12	0	2858	0	0
T13	0	5121	0	0
T14	0	851	0	0
T15	0	2362	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34387974	34052597	0	0
T1	66713	66655	0	0
T2	9307	9222	0	0
T3	6041	5942	0	0
T4	1627	24	0	0
T5	43324	42922	0	0
T6	117928	117857	0	0
T7	13225	11195	0	0
T8	78174	78108	0	0
T9	117440	117360	0	0
T10	60345	58017	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1919	0	0
T1	302716	2	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T5	151639	1	0	0
T6	147413	3	0	0
T7	324061	0	0	0
T8	938102	2	0	0
T9	182034	3	0	0
T10	168655	1	0	0
T11	416156	0	0	0
T12	0	2	0	0
T13	0	3	0	0
T14	0	3	0	0
T15	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	302716	302715	0	0
T2	125669	125664	0	0
T3	290026	290017	0	0
T4	195501	194021	0	0
T5	151639	151602	0	0
T6	147413	147412	0	0
T7	324061	323851	0	0
T8	938102	938094	0	0
T9	182034	182033	0	0
T10	168655	168631	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T5,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1584771	0	0
DstReqKnown_A	34387974	34052597	0	0
SrcAckBusyChk_A	2147483647	1881	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1584771	0	0
T1	302716	2457	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T5	151639	115	0	0
T6	147413	1305	0	0
T7	324061	0	0	0
T8	938102	789	0	0
T9	182034	1069	0	0
T10	168655	706	0	0
T11	416156	0	0	0
T12	0	2854	0	0
T13	0	5092	0	0
T14	0	827	0	0
T15	0	2341	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34387974	34052597	0	0
T1	66713	66655	0	0
T2	9307	9222	0	0
T3	6041	5942	0	0
T4	1627	24	0	0
T5	43324	42922	0	0
T6	117928	117857	0	0
T7	13225	11195	0	0
T8	78174	78108	0	0
T9	117440	117360	0	0
T10	60345	58017	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1881	0	0
T1	302716	2	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T5	151639	1	0	0
T6	147413	3	0	0
T7	324061	0	0	0
T8	938102	2	0	0
T9	182034	3	0	0
T10	168655	1	0	0
T11	416156	0	0	0
T12	0	2	0	0
T13	0	3	0	0
T14	0	3	0	0
T15	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	302716	302715	0	0
T2	125669	125664	0	0
T3	290026	290017	0	0
T4	195501	194021	0	0
T5	151639	151602	0	0
T6	147413	147412	0	0
T7	324061	323851	0	0
T8	938102	938094	0	0
T9	182034	182033	0	0
T10	168655	168631	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T5,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1676044	0	0
DstReqKnown_A	34387974	34052597	0	0
SrcAckBusyChk_A	2147483647	1951	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1676044	0	0
T1	302716	2441	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T5	151639	113	0	0
T6	147413	1275	0	0
T7	324061	0	0	0
T8	938102	785	0	0
T9	182034	1041	0	0
T10	168655	702	0	0
T11	416156	0	0	0
T12	0	2850	0	0
T13	0	5057	0	0
T14	0	799	0	0
T15	0	2321	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34387974	34052597	0	0
T1	66713	66655	0	0
T2	9307	9222	0	0
T3	6041	5942	0	0
T4	1627	24	0	0
T5	43324	42922	0	0
T6	117928	117857	0	0
T7	13225	11195	0	0
T8	78174	78108	0	0
T9	117440	117360	0	0
T10	60345	58017	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1951	0	0
T1	302716	2	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T5	151639	1	0	0
T6	147413	3	0	0
T7	324061	0	0	0
T8	938102	2	0	0
T9	182034	3	0	0
T10	168655	1	0	0
T11	416156	0	0	0
T12	0	2	0	0
T13	0	3	0	0
T14	0	3	0	0
T15	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	302716	302715	0	0
T2	125669	125664	0	0
T3	290026	290017	0	0
T4	195501	194021	0	0
T5	151639	151602	0	0
T6	147413	147412	0	0
T7	324061	323851	0	0
T8	938102	938094	0	0
T9	182034	182033	0	0
T10	168655	168631	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T5,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1597121	0	0
DstReqKnown_A	34387974	34052597	0	0
SrcAckBusyChk_A	2147483647	1910	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1597121	0	0
T1	302716	2420	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T5	151639	111	0	0
T6	147413	1246	0	0
T7	324061	0	0	0
T8	938102	781	0	0
T9	182034	1020	0	0
T10	168655	689	0	0
T11	416156	0	0	0
T12	0	2846	0	0
T13	0	5010	0	0
T14	0	786	0	0
T15	0	2307	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34387974	34052597	0	0
T1	66713	66655	0	0
T2	9307	9222	0	0
T3	6041	5942	0	0
T4	1627	24	0	0
T5	43324	42922	0	0
T6	117928	117857	0	0
T7	13225	11195	0	0
T8	78174	78108	0	0
T9	117440	117360	0	0
T10	60345	58017	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1910	0	0
T1	302716	2	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T5	151639	1	0	0
T6	147413	3	0	0
T7	324061	0	0	0
T8	938102	2	0	0
T9	182034	3	0	0
T10	168655	1	0	0
T11	416156	0	0	0
T12	0	2	0	0
T13	0	3	0	0
T14	0	3	0	0
T15	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	302716	302715	0	0
T2	125669	125664	0	0
T3	290026	290017	0	0
T4	195501	194021	0	0
T5	151639	151602	0	0
T6	147413	147412	0	0
T7	324061	323851	0	0
T8	938102	938094	0	0
T9	182034	182033	0	0
T10	168655	168631	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T5,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1636145	0	0
DstReqKnown_A	34387974	34052597	0	0
SrcAckBusyChk_A	2147483647	1921	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1636145	0	0
T1	302716	2392	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T5	151639	109	0	0
T6	147413	1206	0	0
T7	324061	0	0	0
T8	938102	777	0	0
T9	182034	998	0	0
T10	168655	684	0	0
T11	416156	0	0	0
T12	0	2842	0	0
T13	0	4975	0	0
T14	0	768	0	0
T15	0	2287	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34387974	34052597	0	0
T1	66713	66655	0	0
T2	9307	9222	0	0
T3	6041	5942	0	0
T4	1627	24	0	0
T5	43324	42922	0	0
T6	117928	117857	0	0
T7	13225	11195	0	0
T8	78174	78108	0	0
T9	117440	117360	0	0
T10	60345	58017	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1921	0	0
T1	302716	2	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T5	151639	1	0	0
T6	147413	3	0	0
T7	324061	0	0	0
T8	938102	2	0	0
T9	182034	3	0	0
T10	168655	1	0	0
T11	416156	0	0	0
T12	0	2	0	0
T13	0	3	0	0
T14	0	3	0	0
T15	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	302716	302715	0	0
T2	125669	125664	0	0
T3	290026	290017	0	0
T4	195501	194021	0	0
T5	151639	151602	0	0
T6	147413	147412	0	0
T7	324061	323851	0	0
T8	938102	938094	0	0
T9	182034	182033	0	0
T10	168655	168631	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T5,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1138379	0	0
DstReqKnown_A	34387974	34052597	0	0
SrcAckBusyChk_A	2147483647	1371	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1138379	0	0
T1	302716	2307	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T5	151639	136	0	0
T6	147413	1191	0	0
T7	324061	0	0	0
T8	938102	761	0	0
T9	182034	1375	0	0
T10	168655	647	0	0
T11	416156	0	0	0
T12	0	2826	0	0
T13	0	4848	0	0
T14	0	771	0	0
T50	0	95	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34387974	34052597	0	0
T1	66713	66655	0	0
T2	9307	9222	0	0
T3	6041	5942	0	0
T4	1627	24	0	0
T5	43324	42922	0	0
T6	117928	117857	0	0
T7	13225	11195	0	0
T8	78174	78108	0	0
T9	117440	117360	0	0
T10	60345	58017	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1371	0	0
T1	302716	2	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T5	151639	1	0	0
T6	147413	3	0	0
T7	324061	0	0	0
T8	938102	2	0	0
T9	182034	3	0	0
T10	168655	1	0	0
T11	416156	0	0	0
T12	0	2	0	0
T13	0	3	0	0
T14	0	3	0	0
T50	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	302716	302715	0	0
T2	125669	125664	0	0
T3	290026	290017	0	0
T4	195501	194021	0	0
T5	151639	151602	0	0
T6	147413	147412	0	0
T7	324061	323851	0	0
T8	938102	938094	0	0
T9	182034	182033	0	0
T10	168655	168631	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T5,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T1,T5,T6
1	-	Covered	T1,T5,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Unreachable
1	0	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	16898500	0	0
DstReqKnown_A	34387974	34052597	0	0
SrcAckBusyChk_A	2147483647	18697	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16898500	0	0
T1	302716	6417	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T5	151639	282	0	0
T6	147413	2588	0	0
T7	324061	122954	0	0
T8	938102	1561	0	0
T9	182034	2912	0	0
T10	168655	207775	0	0
T11	416156	0	0	0
T12	0	6228	0	0
T13	0	10486	0	0
T14	0	1656	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34387974	34052597	0	0
T1	66713	66655	0	0
T2	9307	9222	0	0
T3	6041	5942	0	0
T4	1627	24	0	0
T5	43324	42922	0	0
T6	117928	117857	0	0
T7	13225	11195	0	0
T8	78174	78108	0	0
T9	117440	117360	0	0
T10	60345	58017	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	18697	0	0
T1	302716	4	0	0
T2	125669	0	0	0
T3	290026	0	0	0
T5	151639	2	0	0
T6	147413	6	0	0
T7	324061	145	0	0
T8	938102	4	0	0
T9	182034	6	0	0
T10	168655	207	0	0
T11	416156	0	0	0
T12	0	4	0	0
T13	0	6	0	0
T14	0	6	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	302716	302715	0	0
T2	125669	125664	0	0
T3	290026	290017	0	0
T4	195501	194021	0	0
T5	151639	151602	0	0
T6	147413	147412	0	0
T7	324061	323851	0	0
T8	938102	938094	0	0
T9	182034	182033	0	0
T10	168655	168631	0	0