Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_adc_chn1_filter_ctl_7_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.73	90.00	66.67			78.26	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.67	94.90	67.39			88.37	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.29	94.12	85.71			83.33	50.00	u_adc_chn_val_0_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_wr_req.u_dst_update_sync	93.75	100.00	75.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.73	90.00	66.67			78.26	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.67	94.90	67.39			88.37	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.29	94.12	85.71			83.33	50.00	u_adc_chn_val_1_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_wr_req.u_dst_update_sync	93.75	100.00	75.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_adc_wakeup_ctl_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_filter_status_cdc.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.72	100.00	95.24			95.65	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.79	100.00	93.48			97.67	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.43	100.00	85.71			100.00	100.00	u_filter_status_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_wr_req.u_dst_update_sync	93.75	100.00	75.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.58	95.65	78.95			85.71	50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.03	97.87	78.57			92.68	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.43	100.00	85.71			100.00	100.00	u_adc_fsm_state_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_wr_req.u_dst_update_sync	93.75	100.00	75.00			100.00	100.00

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	299	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
283	1	1
284	1	1
299		unreachable

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb

	Line No.	Total	Covered	Percent
TOTAL		50	45	90.00
CONT_ASSIGN	100	1	1	100.00
ALWAYS	111	3	3	100.00
ALWAYS	121	6	4	66.67
CONT_ASSIGN	135	1	1	100.00
ALWAYS	139	6	6	100.00
ALWAYS	155	10	9	90.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	187	19	17	89.47
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	244	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
111	1	1
112	1	1
114	1	1
121	1	1
122	1	1
123	1	1
128	0	1
129	1	1
132	0	1
			MISSING_ELSE
135	1	1
139	1	1
140	1	1
141	1	1
142	1	1
143	1	1
144	1	1
			MISSING_ELSE
155	1	1
156	1	1
157	1	1
158	1	1
159	1	1
160	0	1
161	1	1
162	1	1
163	1	1
164	1	1
			MISSING_ELSE
183	1	1
187	1	1
188	1	1
192	1	1
193	1	1
195	1	1
197	1	1
199	1	1
200	1	1
202	0	1
203	0	1
204	1	1
205	1	1
206	1	1
207	1	1
210	1	1
211	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
			MISSING_ELSE
228	1	1
243	1	1
244	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb

	Total	Covered	Percent
Conditions	42	28	66.67
Logical	42	28	66.67
Non-Logical	0	0
Event	0	0

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T50
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T2,T3

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T2,T3

 LINE       123
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       129
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       135
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Not Covered
1	0	Not Covered

 LINE       157
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       159
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       161
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T2,T3

 LINE       183
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T2
1	1	Not Covered

 LINE       207
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T10,T50

 LINE       228
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T1,T2
0	0	1	Covered	T1,T10,T50
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       243
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       243
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb

	Line No.	Total	Covered	Percent
Branches		23	18	78.26
IF	111	2	2	100.00
IF	121	4	2	50.00
IF	139	4	4	100.00
IF	155	6	5	83.33
CASE	197	7	5	71.43

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	121	if ((!rst_dst_ni))
-2-:	123	if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d))
-3-:	129	if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	139	if ((!rst_dst_ni))
-2-:	141	if (gen_wr_req.dst_lat_d)
-3-:	143	if (gen_wr_req.dst_lat_q)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T10,T50
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	155	if ((!rst_dst_ni))
-2-:	157	if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack))
-3-:	159	if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d))
-4-:	161	if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d))
-5-:	163	if (gen_wr_req.dst_lat_q)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T4,T1,T2
0	1	-	-	-	Covered	T1,T2,T3
0	0	1	-	-	Not Covered
0	0	0	1	-	Covered	T1,T2,T3
0	0	0	0	1	Covered	T1,T10,T50
0	0	0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	197	case (gen_wr_req.state_q)
-2-:	200	if (gen_wr_req.dst_req)
-3-:	204	if (dst_update)
-4-:	207	if ((dst_qs_o != dst_qs_i))
-5-:	217	if (gen_wr_req.dst_update_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StIdle	1	-	-	-	Not Covered
StIdle	0	1	-	-	Covered	T1,T2,T3
StIdle	0	0	1	-	Covered	T1,T10,T50
StIdle	0	0	0	-	Covered	T4,T1,T2
StWait	-	-	-	1	Covered	T1,T2,T3
StWait	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	Not Covered

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wr_req.DstUpdateReqCheck_A	34387974	654401	0	919
gen_wr_req.HwIdSelCheck_A	34387974	654559	0	0

gen_wr_req.DstUpdateReqCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34387974	654401	0	919
T1	66713	1394	0	1
T2	9307	60	0	1
T3	6041	39	0	1
T5	43324	831	0	1
T6	117928	2108	0	1
T7	13225	170	0	1
T8	78174	1383	0	1
T9	117440	2093	0	1
T10	60345	967	0	1
T11	8760	57	0	1

gen_wr_req.HwIdSelCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34387974	654559	0	0
T1	66713	1396	0	0
T2	9307	60	0	0
T3	6041	39	0	0
T5	43324	831	0	0
T6	117928	2108	0	0
T7	13225	170	0	0
T8	78174	1383	0	0
T9	117440	2093	0	0
T10	60345	968	0	0
T11	8760	57	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb

	Line No.	Total	Covered	Percent
TOTAL		50	45	90.00
CONT_ASSIGN	100	1	1	100.00
ALWAYS	111	3	3	100.00
ALWAYS	121	6	4	66.67
CONT_ASSIGN	135	1	1	100.00
ALWAYS	139	6	6	100.00
ALWAYS	155	10	9	90.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	187	19	17	89.47
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	244	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
111	1	1
112	1	1
114	1	1
121	1	1
122	1	1
123	1	1
128	0	1
129	1	1
132	0	1
			MISSING_ELSE
135	1	1
139	1	1
140	1	1
141	1	1
142	1	1
143	1	1
144	1	1
			MISSING_ELSE
155	1	1
156	1	1
157	1	1
158	1	1
159	1	1
160	0	1
161	1	1
162	1	1
163	1	1
164	1	1
			MISSING_ELSE
183	1	1
187	1	1
188	1	1
192	1	1
193	1	1
195	1	1
197	1	1
199	1	1
200	1	1
202	0	1
203	0	1
204	1	1
205	1	1
206	1	1
207	1	1
210	1	1
211	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
			MISSING_ELSE
228	1	1
243	1	1
244	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb

	Total	Covered	Percent
Conditions	42	28	66.67
Logical	42	28	66.67
Non-Logical	0	0
Event	0	0

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T2,T3

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T2,T3

 LINE       123
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       129
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       135
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Not Covered
1	0	Not Covered

 LINE       157
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       159
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       161
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T2,T3

 LINE       183
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T2
1	1	Not Covered

 LINE       207
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T5,T6

 LINE       228
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T1,T2
0	0	1	Covered	T1,T5,T6
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       243
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       243
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb

	Line No.	Total	Covered	Percent
Branches		23	18	78.26
IF	111	2	2	100.00
IF	121	4	2	50.00
IF	139	4	4	100.00
IF	155	6	5	83.33
CASE	197	7	5	71.43

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	121	if ((!rst_dst_ni))
-2-:	123	if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d))
-3-:	129	if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	139	if ((!rst_dst_ni))
-2-:	141	if (gen_wr_req.dst_lat_d)
-3-:	143	if (gen_wr_req.dst_lat_q)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T5,T6
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	155	if ((!rst_dst_ni))
-2-:	157	if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack))
-3-:	159	if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d))
-4-:	161	if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d))
-5-:	163	if (gen_wr_req.dst_lat_q)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T4,T1,T2
0	1	-	-	-	Covered	T1,T2,T3
0	0	1	-	-	Not Covered
0	0	0	1	-	Covered	T1,T2,T3
0	0	0	0	1	Covered	T1,T5,T6
0	0	0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	197	case (gen_wr_req.state_q)
-2-:	200	if (gen_wr_req.dst_req)
-3-:	204	if (dst_update)
-4-:	207	if ((dst_qs_o != dst_qs_i))
-5-:	217	if (gen_wr_req.dst_update_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StIdle	1	-	-	-	Not Covered
StIdle	0	1	-	-	Covered	T1,T2,T3
StIdle	0	0	1	-	Covered	T1,T5,T6
StIdle	0	0	0	-	Covered	T4,T1,T2
StWait	-	-	-	1	Covered	T1,T2,T3
StWait	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	Not Covered

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wr_req.DstUpdateReqCheck_A	34387974	639731	0	919
gen_wr_req.HwIdSelCheck_A	34387974	647686	0	0

gen_wr_req.DstUpdateReqCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34387974	639731	0	919
T1	66713	1384	0	1
T2	9307	60	0	1
T3	6041	39	0	1
T5	43324	789	0	1
T6	117928	2032	0	1
T7	13225	127	0	1
T8	78174	1377	0	1
T9	117440	2059	0	1
T10	60345	922	0	1
T11	8760	57	0	1

gen_wr_req.HwIdSelCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34387974	647686	0	0
T1	66713	1401	0	0
T2	9307	60	0	0
T3	6041	39	0	0
T5	43324	798	0	0
T6	117928	2059	0	0
T7	13225	127	0	0
T8	78174	1392	0	0
T9	117440	2086	0	0
T10	60345	927	0	0
T11	8760	57	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	100	0	0
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	299	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100		unreachable
283	1	1
284	1	1
299		unreachable

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T5,T6

Line Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_arb

	Line No.	Total	Covered	Percent
TOTAL		50	50	100.00
CONT_ASSIGN	100	1	1	100.00
ALWAYS	111	3	3	100.00
ALWAYS	121	6	6	100.00
CONT_ASSIGN	135	1	1	100.00
ALWAYS	139	6	6	100.00
ALWAYS	155	10	10	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	187	19	19	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	244	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
111	1	1
112	1	1
114	1	1
121	1	1
122	1	1
123	1	1
128	1	1
129	1	1
132	1	1
			MISSING_ELSE
135	1	1
139	1	1
140	1	1
141	1	1
142	1	1
143	1	1
144	1	1
			MISSING_ELSE
155	1	1
156	1	1
157	1	1
158	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
			MISSING_ELSE
183	1	1
187	1	1
188	1	1
192	1	1
193	1	1
195	1	1
197	1	1
199	1	1
200	1	1
202	1	1
203	1	1
204	1	1
205	1	1
206	1	1
207	1	1
210	1	1
211	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
			MISSING_ELSE
228	1	1
243	1	1
244	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_arb

	Total	Covered	Percent
Conditions	42	40	95.24
Logical	42	40	95.24
Non-Logical	0	0
Event	0	0

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T36
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T5,T6

 LINE       123
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T57,T58,T59
1	1	Covered	T60,T57,T58

 LINE       129
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T6
1	0	1	Not Covered
1	1	0	Covered	T1,T5,T6
1	1	1	Covered	T60,T57,T58

 LINE       135
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Covered	T1,T5,T6
1	0	Covered	T60,T57,T58

 LINE       157
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       159
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T57,T58,T59
1	1	Covered	T1,T5,T6

 LINE       161
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T5,T6

 LINE       183
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T60,T57,T58
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T5,T6

 LINE       207
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T10,T36

 LINE       228
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T1,T2
0	0	1	Covered	T1,T10,T36
0	1	0	Covered	T1,T5,T6
1	0	0	Covered	T1,T5,T6

 LINE       243
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       243
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T5,T6

---

Branch Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_arb

	Line No.	Total	Covered	Percent
Branches		23	22	95.65
IF	111	2	2	100.00
IF	121	4	4	100.00
IF	139	4	4	100.00
IF	155	6	6	100.00
CASE	197	7	6	85.71

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	121	if ((!rst_dst_ni))
-2-:	123	if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d))
-3-:	129	if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T60,T57,T58
0	0	1	Covered	T60,T57,T58
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	139	if ((!rst_dst_ni))
-2-:	141	if (gen_wr_req.dst_lat_d)
-3-:	143	if (gen_wr_req.dst_lat_q)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T1,T5,T6
0	0	1	Covered	T1,T10,T36
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	155	if ((!rst_dst_ni))
-2-:	157	if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack))
-3-:	159	if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d))
-4-:	161	if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d))
-5-:	163	if (gen_wr_req.dst_lat_q)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T4,T1,T2
0	1	-	-	-	Covered	T1,T5,T6
0	0	1	-	-	Covered	T1,T5,T6
0	0	0	1	-	Covered	T1,T5,T6
0	0	0	0	1	Covered	T1,T10,T36
0	0	0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	197	case (gen_wr_req.state_q)
-2-:	200	if (gen_wr_req.dst_req)
-3-:	204	if (dst_update)
-4-:	207	if ((dst_qs_o != dst_qs_i))
-5-:	217	if (gen_wr_req.dst_update_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StIdle	1	-	-	-	Covered	T1,T5,T6
StIdle	0	1	-	-	Covered	T1,T5,T6
StIdle	0	0	1	-	Covered	T1,T10,T36
StIdle	0	0	0	-	Covered	T4,T1,T2
StWait	-	-	-	1	Covered	T1,T5,T6
StWait	-	-	-	0	Covered	T1,T5,T6
default	-	-	-	-	Not Covered

---

Assert Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wr_req.DstUpdateReqCheck_A	34387974	15880	0	919
gen_wr_req.HwIdSelCheck_A	34387974	15949	0	0

gen_wr_req.DstUpdateReqCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34387974	15880	0	919
T1	66713	35	0	1
T2	9307	0	0	1
T3	6041	0	0	1
T5	43324	12	0	1
T6	117928	71	0	1
T7	13225	0	0	1
T8	78174	56	0	1
T9	117440	86	0	1
T10	60345	14	0	1
T11	8760	0	0	1
T12	0	42	0	0
T13	0	79	0	0
T14	0	72	0	0
T15	0	39	0	0

gen_wr_req.HwIdSelCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34387974	15949	0	0
T1	66713	36	0	0
T2	9307	0	0	0
T3	6041	0	0	0
T5	43324	12	0	0
T6	117928	71	0	0
T7	13225	0	0	0
T8	78174	56	0	0
T9	117440	86	0	0
T10	60345	15	0	0
T11	8760	0	0	0
T12	0	42	0	0
T13	0	79	0	0
T14	0	72	0	0
T15	0	39	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	100	0	0
ALWAYS	111	3	3	100.00
ALWAYS	121	6	4	66.67
CONT_ASSIGN	135	1	1	100.00
ALWAYS	139	6	6	100.00
ALWAYS	155	9	9	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	187	17	17	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	244	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100		unreachable
111	1	1
112	1	1
114	1	1
121	1	1
122	1	1
123	1	1
128	0	1
129	1	1
132	0	1
			MISSING_ELSE
135	1	1
139	1	1
140	1	1
141	1	1
142	1	1
143	1	1
144	1	1
			MISSING_ELSE
155	1	1
156	1	1
157	1	1
158	1	1
159	1	1
160	1	1
161	1	1
162		excluded
			Exclude Annotation: VC_COV_UNR
163	1	1
164	1	1
			MISSING_ELSE
183	1	1
187	1	1
188	1	1
192	1	1
193	1	1
195	1	1
197	1	1
199	1	1
200	1	1
202	1	1
203	1	1
204	1	1
205		unreachable
206		unreachable
207	1	1
210	1	1
211	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
			MISSING_ELSE
228	1	1
243	1	1
244	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb

	Total	Covered	Percent
Conditions	38	30	78.95
Logical	38	30	78.95
Non-Logical	0	0
Event	0	0

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T2,T3

 LINE       123
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T44
1	0	Not Covered
1	1	Not Covered

 LINE       129
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T16,T17,T44
1	1	1	Not Covered

 LINE       135
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Covered	T16,T17,T44
1	0	Not Covered

 LINE       157
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       159
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Not Covered
1	1	Covered	T16,T17,T44

 LINE       161
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T4,T1,T2
1	1	Excluded		VC_COV_UNR

 LINE       183
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T2
1	1	Covered	T16,T17,T44

 LINE       207
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T2,T3

 LINE       228
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T1,T2
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T16,T17,T44
1	0	0	Covered	T1,T2,T3

 LINE       243
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T1,T2,T3
1	1	Covered	T16,T17,T44

 LINE       243
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T17,T44
1	1	Covered	T1,T2,T3

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb

	Line No.	Total	Covered	Percent
Branches		21	18	85.71
IF	111	2	2	100.00
IF	121	4	2	50.00
IF	139	4	4	100.00
IF	155	5	5	100.00
CASE	197	6	5	83.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	121	if ((!rst_dst_ni))
-2-:	123	if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d))
-3-:	129	if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	139	if ((!rst_dst_ni))
-2-:	141	if (gen_wr_req.dst_lat_d)
-3-:	143	if (gen_wr_req.dst_lat_q)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T16,T17,T44
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	155	if ((!rst_dst_ni))
-2-:	157	if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack))
-3-:	159	if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d))
-4-:	161	if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d))
-5-:	163	if (gen_wr_req.dst_lat_q)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests	Exclude Annotation
1	-	-	-	-	Covered	T4,T1,T2
0	1	-	-	-	Covered	T1,T2,T3
0	0	1	-	-	Covered	T16,T17,T44
0	0	0	1	-	Excluded		VC_COV_UNR
0	0	0	0	1	Covered	T1,T2,T3
0	0	0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	197	case (gen_wr_req.state_q)
-2-:	200	if (gen_wr_req.dst_req)
-3-:	204	if (dst_update)
-4-:	207	if ((dst_qs_o != dst_qs_i))
-5-:	217	if (gen_wr_req.dst_update_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StIdle	1	-	-	-	Covered	T16,T17,T44
StIdle	0	1	-	-	Unreachable
StIdle	0	0	1	-	Covered	T1,T2,T3
StIdle	0	0	0	-	Covered	T4,T1,T2
StWait	-	-	-	1	Covered	T1,T2,T3
StWait	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	Not Covered

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wr_req.DstUpdateReqCheck_A	34387974	0	0	919
gen_wr_req.HwIdSelCheck_A	34387974	3308990	0	0

gen_wr_req.DstUpdateReqCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34387974	0	0	919

gen_wr_req.HwIdSelCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34387974	3308990	0	0
T1	66713	6696	0	0
T2	9307	359	0	0
T3	6041	235	0	0
T5	43324	3929	0	0
T6	117928	11659	0	0
T7	13225	787	0	0
T8	78174	8116	0	0
T9	117440	12220	0	0
T10	60345	5224	0	0
T11	8760	341	0	0