Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1197965	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1172830

1

T1

462

T2

1006

T3

336

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2076945	1			T1	861		T2	1700		T4	81
values[0x0]	146615	1			T1	48		T2	113		T3	441
values[0x1]	147235	1			T1	51		T2	122		T3	468

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	959779	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1411016

1

T1

560

T2

1187

T3

404

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13824	1			T1	6		T2	7		T5	14
valid_sources[0x01]	7562	1			T1	2		T2	9		T5	7
valid_sources[0x02]	7983	1			T1	5		T2	5		T5	1
valid_sources[0x03]	7080	1			T1	6		T2	17		T5	29
valid_sources[0x04]	6826	1			T1	1		T2	16		T5	8
valid_sources[0x05]	6776	1			T1	1		T2	7		T13	3
valid_sources[0x06]	11241	1			T1	7		T2	8		T5	8
valid_sources[0x07]	15625	1			T1	5		T2	4		T5	1
valid_sources[0x08]	6830	1			T1	1		T2	18		T5	4
valid_sources[0x09]	13421	1			T1	5		T2	4		T5	9
valid_sources[0x0a]	6927	1			T2	14		T5	34		T6	17
valid_sources[0x0b]	7702	1			T2	7		T5	3		T6	20
valid_sources[0x0c]	7218	1			T1	6		T2	9		T5	5
valid_sources[0x0d]	19459	1			T2	11		T5	4		T6	18
valid_sources[0x0e]	13908	1			T1	10		T2	7		T5	2
valid_sources[0x0f]	7893	1			T2	1		T5	3		T6	28
valid_sources[0x10]	10005	1			T1	1		T2	9		T5	6
valid_sources[0x11]	9951	1			T1	7		T2	6		T6	21
valid_sources[0x12]	9251	1			T1	2		T2	4		T5	2
valid_sources[0x13]	9390	1			T1	4		T2	4		T5	2
valid_sources[0x14]	12418	1			T1	9		T2	13		T5	12
valid_sources[0x15]	9250	1			T1	8		T2	7		T5	6
valid_sources[0x16]	6946	1			T2	7		T5	39		T6	7
valid_sources[0x17]	9790	1			T1	4		T2	9		T5	3
valid_sources[0x18]	7892	1			T1	5		T2	6		T5	8
valid_sources[0x19]	7633	1			T1	4		T2	7		T5	1
valid_sources[0x1a]	12065	1			T2	7		T5	6		T6	19
valid_sources[0x1b]	8047	1			T2	6		T5	14		T6	26
valid_sources[0x1c]	6896	1			T1	19		T2	8		T5	5
valid_sources[0x1d]	11491	1			T1	3		T2	7		T5	4
valid_sources[0x1e]	7546	1			T1	4		T2	9		T5	5
valid_sources[0x1f]	8030	1			T2	5		T5	21		T6	14
valid_sources[0x20]	10263	1			T1	1		T2	9		T6	25
valid_sources[0x21]	9747	1			T1	3		T2	3		T5	7
valid_sources[0x22]	6925	1			T2	6		T5	4		T6	20
valid_sources[0x23]	20437	1			T1	1		T2	5		T5	10
valid_sources[0x24]	6831	1			T1	7		T2	7		T5	8
valid_sources[0x25]	11425	1			T1	4		T2	6		T5	5
valid_sources[0x26]	8099	1			T1	8		T2	3		T5	4
valid_sources[0x27]	6814	1			T1	1		T2	6		T5	27
valid_sources[0x28]	7775	1			T2	4		T5	1		T6	33
valid_sources[0x29]	11318	1			T1	10		T2	3		T5	3
valid_sources[0x2a]	6763	1			T2	7		T5	6		T6	22
valid_sources[0x2b]	9942	1			T1	8		T2	5		T5	3
valid_sources[0x2c]	7075	1			T1	1		T2	6		T5	2
valid_sources[0x2d]	7903	1			T1	1		T2	13		T5	10
valid_sources[0x2e]	6618	1			T1	9		T2	12		T5	20
valid_sources[0x2f]	6897	1			T2	6		T5	21		T6	20
valid_sources[0x30]	15687	1			T2	5		T5	3		T6	16
valid_sources[0x31]	7896	1			T1	6		T2	6		T5	8
valid_sources[0x32]	11196	1			T1	3		T2	11		T5	4
valid_sources[0x33]	9671	1			T1	6		T2	9		T5	2
valid_sources[0x34]	7865	1			T1	10		T2	5		T5	6
valid_sources[0x35]	13275	1			T2	13		T5	4		T6	24
valid_sources[0x36]	7240	1			T1	1		T2	17		T5	10
valid_sources[0x37]	9604	1			T2	4		T5	2		T6	22
valid_sources[0x38]	7183	1			T1	3		T2	11		T5	11
valid_sources[0x39]	12476	1			T1	10		T2	7		T5	11
valid_sources[0x3a]	6798	1			T1	7		T2	8		T5	10
valid_sources[0x3b]	9528	1			T1	3		T2	9		T5	5
valid_sources[0x3c]	9806	1			T1	4		T2	12		T5	8
valid_sources[0x3d]	6643	1			T2	9		T5	3		T6	19
valid_sources[0x3e]	8790	1			T2	10		T5	7		T6	24
valid_sources[0x3f]	12895	1			T1	1		T2	6		T5	7
valid_sources[0x40]	7448	1			T1	7		T2	8		T5	20
valid_sources[0x41]	7181	1			T1	6		T2	7		T5	8
valid_sources[0x42]	11304	1			T1	1		T2	10		T5	4
valid_sources[0x43]	7082	1			T2	4		T13	4		T5	3
valid_sources[0x44]	6835	1			T1	2		T2	6		T5	14
valid_sources[0x45]	7912	1			T1	13		T2	5		T5	10
valid_sources[0x46]	7860	1			T2	7		T5	8		T6	24
valid_sources[0x47]	7222	1			T1	7		T2	5		T5	1
valid_sources[0x48]	10378	1			T1	8		T2	14		T6	16
valid_sources[0x49]	8731	1			T1	6		T2	9		T5	23
valid_sources[0x4a]	7262	1			T1	2		T2	1		T5	12
valid_sources[0x4b]	7447	1			T1	6		T2	5		T5	12
valid_sources[0x4c]	6967	1			T2	5		T5	8		T6	15
valid_sources[0x4d]	8145	1			T1	3		T2	4		T5	24
valid_sources[0x4e]	9054	1			T1	1		T2	8		T5	13
valid_sources[0x4f]	6767	1			T1	7		T2	4		T6	16
valid_sources[0x50]	7404	1			T1	8		T2	10		T5	41
valid_sources[0x51]	7143	1			T1	3		T2	4		T5	16
valid_sources[0x52]	9572	1			T1	4		T2	10		T5	1
valid_sources[0x53]	7826	1			T1	1		T2	6		T5	34
valid_sources[0x54]	7707	1			T1	4		T2	6		T5	3
valid_sources[0x55]	11242	1			T2	6		T5	19		T6	16
valid_sources[0x56]	7651	1			T1	1		T2	4		T5	14
valid_sources[0x57]	10094	1			T2	11		T5	7		T6	12
valid_sources[0x58]	7402	1			T1	5		T2	10		T5	1
valid_sources[0x59]	8078	1			T1	3		T2	4		T5	5
valid_sources[0x5a]	8053	1			T1	1		T2	9		T5	16
valid_sources[0x5b]	11020	1			T1	4		T2	3		T5	10
valid_sources[0x5c]	6683	1			T1	3		T2	6		T5	19
valid_sources[0x5d]	7498	1			T1	5		T2	11		T5	14
valid_sources[0x5e]	6913	1			T1	3		T2	5		T5	26
valid_sources[0x5f]	11777	1			T1	1		T2	4		T5	3
valid_sources[0x60]	6872	1			T1	4		T2	4		T5	2
valid_sources[0x61]	7446	1			T1	1		T2	7		T5	4
valid_sources[0x62]	9736	1			T1	13		T2	5		T5	1
valid_sources[0x63]	7127	1			T1	1		T2	12		T5	18
valid_sources[0x64]	7099	1			T2	8		T6	14		T7	47
valid_sources[0x65]	8768	1			T2	6		T5	21		T6	11
valid_sources[0x66]	12132	1			T1	8		T2	12		T5	9
valid_sources[0x67]	20094	1			T1	1		T2	10		T5	13
valid_sources[0x68]	12258	1			T1	2		T2	9		T5	15
valid_sources[0x69]	6862	1			T1	1		T2	11		T5	10
valid_sources[0x6a]	6816	1			T1	2		T2	10		T5	2
valid_sources[0x6b]	11186	1			T1	5		T2	6		T5	4
valid_sources[0x6c]	11682	1			T1	2		T2	7		T5	6
valid_sources[0x6d]	6604	1			T1	5		T2	14		T5	7
valid_sources[0x6e]	8031	1			T1	2		T2	10		T5	39
valid_sources[0x6f]	7877	1			T1	5		T2	4		T5	13
valid_sources[0x70]	7370	1			T1	2		T2	10		T5	8
valid_sources[0x71]	9961	1			T1	8		T2	7		T5	11
valid_sources[0x72]	7254	1			T1	1		T2	5		T5	18
valid_sources[0x73]	7309	1			T2	3		T5	12		T6	17
valid_sources[0x74]	10250	1			T1	1		T2	6		T5	4
valid_sources[0x75]	7177	1			T1	1		T2	8		T5	5
valid_sources[0x76]	12530	1			T1	8		T2	10		T5	26
valid_sources[0x77]	6855	1			T1	3		T2	10		T5	3
valid_sources[0x78]	7083	1			T1	4		T2	8		T5	48
valid_sources[0x79]	6884	1			T1	4		T2	7		T5	8
valid_sources[0x7a]	6852	1			T1	11		T2	11		T5	13
valid_sources[0x7b]	7737	1			T1	4		T2	6		T5	10
valid_sources[0x7c]	9244	1			T2	19		T5	1		T6	31
valid_sources[0x7d]	6841	1			T1	2		T2	7		T5	14
valid_sources[0x7e]	9837	1			T1	2		T2	7		T4	144
valid_sources[0x7f]	8091	1			T1	4		T2	16		T5	7
valid_sources[0x80]	13693	1			T1	1		T2	5		T5	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1034323

1

T1

419

T2

894

T4

37

values[0x0]

all_enables

biggest_size

80349

1

T1

29

T2

61

T3

197

values[0x1]

all_enables

biggest_size

58158

1

T1

14

T2

51

T3

139