Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.67	86.67	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	86.67	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.67	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	6	39	86.67

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	5	11	68.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	29301	1			T1	8		T2	13		T3	182
auto[PWRUP]	122	1			T6	1		T49	3		T28	3
auto[ONEST_0]	71	1			T49	3		T46	3		T47	1
auto[ONEST_021]	20	1			T46	1		T47	1		T48	1
auto[ONEST_1]	82	1			T6	1		T28	3		T46	3
auto[ONEST_DONE]	4	1			T81	1		T203	1		T204	1
auto[LP_0]	122	1			T3	2		T6	2		T28	1
auto[LP_021]	30	1			T47	2		T48	2		T205	1
auto[LP_1]	133	1			T3	2		T6	3		T49	2
auto[LP_EVAL]	51	1			T6	2		T28	1		T48	2
auto[LP_SLP]	470	1			T3	8		T6	1		T49	6
auto[LP_PWRUP]	17	1			T49	1		T50	1		T206	1
auto[NP_0]	148	1			T3	2		T49	1		T28	2
auto[NP_021]	28	1			T28	1		T48	1		T37	2
auto[NP_1]	139	1			T3	1		T6	2		T49	2
auto[NP_EVAL]	40	1			T6	1		T49	1		T28	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

8

1

T50

1

T207

1

T208

2

min

28729

1

T1

8

T2

13

T3

177

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28733	1			T1	8		T2	13		T3	177
pow[0x1]	3	1			T209	1		T210	1		T211	1
pow[0x2]	16	1			T3	1		T81	1		T207	1
pow[0x3]	35	1			T3	1		T28	2		T50	2
pow[0x4]	57	1			T49	1		T28	2		T46	2
pow[0x5]	120	1			T3	1		T6	1		T49	2
pow[0x6]	254	1			T3	3		T6	2		T49	2
pow[0x7]	514	1			T3	3		T6	7		T49	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

204

1

T6

1

T49

4

T28

4

min

28289

1

T1

8

T2

13

T3

171

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	5	11	68.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x5]	0	1	1
pow[0x7]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28289	1			T1	8		T2	13		T3	171
pow[0x4]	1	1			T212	1		-	-		-	-
pow[0x6]	1	1			T213	1		-	-		-	-
pow[0x8]	8	1			T16	1		T207	1		T214	1
pow[0x9]	2	1			T215	1		T216	1		-	-
pow[0xa]	32	1			T28	1		T48	1		T205	2
pow[0xb]	25	1			T46	1		T47	1		T50	2
pow[0xc]	73	1			T6	1		T49	1		T48	2
pow[0xd]	127	1			T3	1		T49	1		T28	2
pow[0xe]	313	1			T3	4		T6	2		T49	3
pow[0xf]	569	1			T3	7		T6	9		T49	7