Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2228	1			T3	13		T6	10		T12	13
auto[PWRUP]	138	1			T6	1		T49	1		T28	2
auto[ONEST_0]	68	1			T3	2		T49	2		T28	1
auto[ONEST_021]	14	1			T46	1		T351	1		T352	1
auto[ONEST_1]	82	1			T3	1		T6	1		T46	2
auto[ONEST_DONE]	4	1			T246	1		T213	1		T277	1
auto[LP_0]	104	1			T3	1		T6	1		T49	1
auto[LP_021]	36	1			T46	2		T47	1		T351	2
auto[LP_1]	125	1			T3	1		T49	2		T28	1
auto[LP_EVAL]	57	1			T3	1		T6	2		T12	1
auto[LP_SLP]	506	1			T3	6		T12	2		T49	4
auto[LP_PWRUP]	39	1			T3	1		T28	1		T47	2
auto[NP_0]	208	1			T3	1		T6	2		T12	1
auto[NP_021]	53	1			T12	1		T28	1		T212	1
auto[NP_1]	221	1			T3	1		T6	1		T12	1
auto[NP_EVAL]	30	1			T6	1		T12	1		T49	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

6

1

T353

1

T354

1

T273

1

min

1951

1

T3

8

T6

11

T12

18

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1963	1			T3	8		T6	11		T12	19
pow[0x1]	15	1			T37	1		T355	1		T292	1
pow[0x2]	19	1			T50	2		T39	2		T355	1
pow[0x3]	37	1			T6	1		T49	1		T28	1
pow[0x4]	65	1			T49	1		T28	1		T47	2
pow[0x5]	142	1			T3	3		T6	1		T49	1
pow[0x6]	238	1			T3	4		T6	1		T49	2
pow[0x7]	470	1			T3	2		T6	2		T49	9

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

165

1

T49

3

T28

3

T46

2

min

1384

1

T3

1

T6

9

T12

15

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1391	1			T3	1		T6	9		T12	16
pow[0x1]	9	1			T38	1		T18	1		T199	1
pow[0x2]	37	1			T12	3		T14	1		T37	2
pow[0x3]	37	1			T6	2		T14	1		T39	3
pow[0x4]	57	1			T6	1		T14	1		T37	1
pow[0x5]	2	1			T166	1		T356	1		-	-
pow[0x6]	1	1			T357	1		-	-		-	-
pow[0x7]	2	1			T356	1		T202	1		-	-
pow[0x8]	3	1			T47	1		T50	1		T358	1
pow[0x9]	8	1			T212	1		T86	1		T355	1
pow[0xa]	13	1			T39	1		T81	1		T207	1
pow[0xb]	35	1			T3	1		T28	2		T46	1
pow[0xc]	60	1			T3	1		T49	1		T28	2
pow[0xd]	145	1			T3	2		T6	2		T49	3
pow[0xe]	285	1			T3	2		T6	1		T12	1
pow[0xf]	548	1			T3	5		T6	1		T49	5