Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1870	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1907	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1809	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1782	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1918	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1768	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1912	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1738	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1777	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1835	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1725	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1810	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1743	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1733	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1990	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1602	0	0
adc_en_ctl_rd_A	2147483647	1502	0	0
adc_fsm_rst_rd_A	2147483647	1324	0	0
adc_intr_ctl_rd_A	2147483647	1588	0	0
adc_lp_sample_ctl_rd_A	2147483647	1373	0	0
adc_pd_ctl_rd_A	2147483647	1823	0	0
adc_sample_ctl_rd_A	2147483647	1412	0	0
adc_wakeup_ctl_rd_A	2147483647	1428	0	0
intr_enable_rd_A	2147483647	2318	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1870	0	0
T15	418885	22	0	0
T16	723930	32	0	0
T17	0	40	0	0
T18	0	35	0	0
T19	0	35	0	0
T20	0	33	0	0
T21	0	14	0	0
T22	0	38	0	0
T23	0	11	0	0
T24	0	19	0	0
T25	211156	0	0	0
T26	351694	0	0	0
T27	401309	0	0	0
T28	458761	0	0	0
T29	832755	0	0	0
T30	300785	0	0	0
T31	243941	0	0	0
T32	414798	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1907	0	0
T15	418885	21	0	0
T16	723930	18	0	0
T17	0	42	0	0
T18	0	49	0	0
T19	0	40	0	0
T20	0	19	0	0
T21	0	6	0	0
T22	0	37	0	0
T23	0	10	0	0
T25	211156	0	0	0
T26	351694	0	0	0
T27	401309	0	0	0
T28	458761	0	0	0
T29	832755	0	0	0
T30	300785	0	0	0
T31	243941	0	0	0
T32	414798	0	0	0
T33	0	28	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1809	0	0
T15	418885	14	0	0
T16	723930	15	0	0
T17	0	37	0	0
T18	0	47	0	0
T19	0	34	0	0
T20	0	36	0	0
T21	0	6	0	0
T22	0	45	0	0
T23	0	23	0	0
T24	0	17	0	0
T25	211156	0	0	0
T26	351694	0	0	0
T27	401309	0	0	0
T28	458761	0	0	0
T29	832755	0	0	0
T30	300785	0	0	0
T31	243941	0	0	0
T32	414798	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1782	0	0
T15	418885	23	0	0
T16	723930	13	0	0
T17	0	34	0	0
T18	0	49	0	0
T19	0	39	0	0
T20	0	31	0	0
T21	0	16	0	0
T22	0	51	0	0
T23	0	30	0	0
T24	0	10	0	0
T25	211156	0	0	0
T26	351694	0	0	0
T27	401309	0	0	0
T28	458761	0	0	0
T29	832755	0	0	0
T30	300785	0	0	0
T31	243941	0	0	0
T32	414798	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1918	0	0
T15	418885	29	0	0
T16	723930	3	0	0
T17	0	19	0	0
T18	0	41	0	0
T19	0	40	0	0
T20	0	28	0	0
T21	0	13	0	0
T22	0	34	0	0
T23	0	22	0	0
T24	0	6	0	0
T25	211156	0	0	0
T26	351694	0	0	0
T27	401309	0	0	0
T28	458761	0	0	0
T29	832755	0	0	0
T30	300785	0	0	0
T31	243941	0	0	0
T32	414798	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1768	0	0
T15	418885	9	0	0
T16	723930	38	0	0
T17	0	42	0	0
T18	0	45	0	0
T19	0	37	0	0
T20	0	53	0	0
T21	0	2	0	0
T22	0	40	0	0
T23	0	14	0	0
T24	0	2	0	0
T25	211156	0	0	0
T26	351694	0	0	0
T27	401309	0	0	0
T28	458761	0	0	0
T29	832755	0	0	0
T30	300785	0	0	0
T31	243941	0	0	0
T32	414798	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1912	0	0
T15	418885	17	0	0
T16	723930	5	0	0
T17	0	27	0	0
T18	0	55	0	0
T19	0	50	0	0
T20	0	33	0	0
T21	0	4	0	0
T22	0	34	0	0
T23	0	28	0	0
T24	0	8	0	0
T25	211156	0	0	0
T26	351694	0	0	0
T27	401309	0	0	0
T28	458761	0	0	0
T29	832755	0	0	0
T30	300785	0	0	0
T31	243941	0	0	0
T32	414798	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1738	0	0
T15	418885	43	0	0
T16	723930	21	0	0
T17	0	19	0	0
T18	0	30	0	0
T19	0	28	0	0
T20	0	27	0	0
T21	0	23	0	0
T22	0	32	0	0
T23	0	7	0	0
T24	0	21	0	0
T25	211156	0	0	0
T26	351694	0	0	0
T27	401309	0	0	0
T28	458761	0	0	0
T29	832755	0	0	0
T30	300785	0	0	0
T31	243941	0	0	0
T32	414798	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1777	0	0
T15	418885	21	0	0
T16	723930	18	0	0
T17	0	36	0	0
T18	0	40	0	0
T19	0	34	0	0
T20	0	31	0	0
T21	0	12	0	0
T22	0	31	0	0
T23	0	20	0	0
T24	0	7	0	0
T25	211156	0	0	0
T26	351694	0	0	0
T27	401309	0	0	0
T28	458761	0	0	0
T29	832755	0	0	0
T30	300785	0	0	0
T31	243941	0	0	0
T32	414798	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1835	0	0
T15	418885	26	0	0
T16	723930	21	0	0
T17	0	39	0	0
T18	0	29	0	0
T19	0	49	0	0
T20	0	49	0	0
T21	0	14	0	0
T22	0	26	0	0
T23	0	7	0	0
T24	0	3	0	0
T25	211156	0	0	0
T26	351694	0	0	0
T27	401309	0	0	0
T28	458761	0	0	0
T29	832755	0	0	0
T30	300785	0	0	0
T31	243941	0	0	0
T32	414798	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1725	0	0
T15	418885	18	0	0
T16	723930	30	0	0
T17	0	31	0	0
T18	0	43	0	0
T19	0	50	0	0
T20	0	33	0	0
T21	0	11	0	0
T22	0	33	0	0
T23	0	18	0	0
T24	0	12	0	0
T25	211156	0	0	0
T26	351694	0	0	0
T27	401309	0	0	0
T28	458761	0	0	0
T29	832755	0	0	0
T30	300785	0	0	0
T31	243941	0	0	0
T32	414798	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1810	0	0
T15	418885	12	0	0
T16	723930	23	0	0
T17	0	48	0	0
T18	0	48	0	0
T19	0	23	0	0
T20	0	33	0	0
T21	0	16	0	0
T22	0	27	0	0
T23	0	20	0	0
T24	0	7	0	0
T25	211156	0	0	0
T26	351694	0	0	0
T27	401309	0	0	0
T28	458761	0	0	0
T29	832755	0	0	0
T30	300785	0	0	0
T31	243941	0	0	0
T32	414798	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1743	0	0
T15	418885	19	0	0
T16	723930	23	0	0
T17	0	34	0	0
T18	0	14	0	0
T19	0	41	0	0
T20	0	25	0	0
T21	0	11	0	0
T22	0	30	0	0
T23	0	15	0	0
T24	0	7	0	0
T25	211156	0	0	0
T26	351694	0	0	0
T27	401309	0	0	0
T28	458761	0	0	0
T29	832755	0	0	0
T30	300785	0	0	0
T31	243941	0	0	0
T32	414798	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1733	0	0
T15	418885	25	0	0
T16	723930	21	0	0
T17	0	31	0	0
T18	0	41	0	0
T19	0	43	0	0
T20	0	32	0	0
T21	0	7	0	0
T22	0	40	0	0
T23	0	12	0	0
T24	0	6	0	0
T25	211156	0	0	0
T26	351694	0	0	0
T27	401309	0	0	0
T28	458761	0	0	0
T29	832755	0	0	0
T30	300785	0	0	0
T31	243941	0	0	0
T32	414798	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1990	0	0
T15	418885	31	0	0
T16	723930	22	0	0
T17	0	22	0	0
T18	0	33	0	0
T19	0	58	0	0
T20	0	44	0	0
T21	0	17	0	0
T22	0	38	0	0
T23	0	28	0	0
T24	0	13	0	0
T25	211156	0	0	0
T26	351694	0	0	0
T27	401309	0	0	0
T28	458761	0	0	0
T29	832755	0	0	0
T30	300785	0	0	0
T31	243941	0	0	0
T32	414798	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1602	0	0
T15	418885	15	0	0
T16	723930	7	0	0
T17	0	30	0	0
T18	0	39	0	0
T19	0	41	0	0
T20	0	32	0	0
T21	0	7	0	0
T22	0	31	0	0
T23	0	21	0	0
T24	0	2	0	0
T25	211156	0	0	0
T26	351694	0	0	0
T27	401309	0	0	0
T28	458761	0	0	0
T29	832755	0	0	0
T30	300785	0	0	0
T31	243941	0	0	0
T32	414798	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1502	0	0
T15	418885	13	0	0
T16	723930	33	0	0
T17	0	46	0	0
T18	0	37	0	0
T19	0	37	0	0
T20	0	33	0	0
T21	0	20	0	0
T22	0	25	0	0
T23	0	18	0	0
T24	0	11	0	0
T25	211156	0	0	0
T26	351694	0	0	0
T27	401309	0	0	0
T28	458761	0	0	0
T29	832755	0	0	0
T30	300785	0	0	0
T31	243941	0	0	0
T32	414798	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1324	0	0
T15	418885	20	0	0
T16	723930	25	0	0
T17	0	24	0	0
T18	0	42	0	0
T19	0	33	0	0
T20	0	42	0	0
T21	0	7	0	0
T22	0	41	0	0
T23	0	21	0	0
T24	0	18	0	0
T25	211156	0	0	0
T26	351694	0	0	0
T27	401309	0	0	0
T28	458761	0	0	0
T29	832755	0	0	0
T30	300785	0	0	0
T31	243941	0	0	0
T32	414798	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1588	0	0
T15	418885	28	0	0
T16	723930	16	0	0
T17	0	17	0	0
T18	0	39	0	0
T19	0	34	0	0
T20	0	24	0	0
T21	0	7	0	0
T22	0	25	0	0
T23	0	23	0	0
T24	0	12	0	0
T25	211156	0	0	0
T26	351694	0	0	0
T27	401309	0	0	0
T28	458761	0	0	0
T29	832755	0	0	0
T30	300785	0	0	0
T31	243941	0	0	0
T32	414798	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1373	0	0
T15	418885	10	0	0
T16	723930	18	0	0
T17	0	38	0	0
T18	0	36	0	0
T19	0	52	0	0
T20	0	40	0	0
T21	0	11	0	0
T22	0	36	0	0
T23	0	16	0	0
T24	0	10	0	0
T25	211156	0	0	0
T26	351694	0	0	0
T27	401309	0	0	0
T28	458761	0	0	0
T29	832755	0	0	0
T30	300785	0	0	0
T31	243941	0	0	0
T32	414798	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1823	0	0
T15	418885	11	0	0
T16	723930	17	0	0
T17	0	26	0	0
T18	0	43	0	0
T19	0	40	0	0
T20	0	39	0	0
T21	0	28	0	0
T22	0	39	0	0
T23	0	17	0	0
T24	0	19	0	0
T25	211156	0	0	0
T26	351694	0	0	0
T27	401309	0	0	0
T28	458761	0	0	0
T29	832755	0	0	0
T30	300785	0	0	0
T31	243941	0	0	0
T32	414798	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1412	0	0
T15	418885	28	0	0
T16	723930	26	0	0
T17	0	40	0	0
T18	0	34	0	0
T19	0	29	0	0
T20	0	36	0	0
T21	0	17	0	0
T22	0	37	0	0
T23	0	35	0	0
T24	0	11	0	0
T25	211156	0	0	0
T26	351694	0	0	0
T27	401309	0	0	0
T28	458761	0	0	0
T29	832755	0	0	0
T30	300785	0	0	0
T31	243941	0	0	0
T32	414798	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1428	0	0
T15	418885	6	0	0
T16	723930	14	0	0
T17	0	12	0	0
T18	0	19	0	0
T19	0	28	0	0
T20	0	23	0	0
T21	0	16	0	0
T22	0	34	0	0
T23	0	11	0	0
T24	0	8	0	0
T25	211156	0	0	0
T26	351694	0	0	0
T27	401309	0	0	0
T28	458761	0	0	0
T29	832755	0	0	0
T30	300785	0	0	0
T31	243941	0	0	0
T32	414798	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2318	0	0
T15	418885	27	0	0
T16	723930	26	0	0
T17	0	44	0	0
T18	0	26	0	0
T19	0	85	0	0
T20	0	63	0	0
T21	0	72	0	0
T25	211156	0	0	0
T26	351694	0	0	0
T27	401309	0	0	0
T28	458761	0	0	0
T29	832755	0	0	0
T30	300785	0	0	0
T31	243941	0	0	0
T32	414798	0	0	0
T34	0	12	0	0
T35	0	9	0	0
T36	0	20	0	0