Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1203210	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1177574

1

T1

259

T2

1421

T3

3019

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2089811	1			T2	2548		T3	5641		T4	81
values[0x0]	145135	1			T1	347		T2	156		T3	244
values[0x1]	145838	1			T1	308		T2	159		T3	253

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	964800	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1415984

1

T1

305

T2

1721

T3

3629

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8196	1			T3	15		T5	8		T6	11
valid_sources[0x01]	6862	1			T3	24		T5	5		T6	10
valid_sources[0x02]	6341	1			T3	14		T5	8		T6	18
valid_sources[0x03]	15341	1			T3	19		T5	6		T6	9
valid_sources[0x04]	6429	1			T3	27		T5	7		T6	12
valid_sources[0x05]	6556	1			T3	15		T5	3		T6	5
valid_sources[0x06]	6645	1			T3	36		T5	2		T6	17
valid_sources[0x07]	7498	1			T3	28		T5	4		T6	3
valid_sources[0x08]	8692	1			T3	22		T5	4		T6	9
valid_sources[0x09]	6749	1			T3	23		T6	6		T8	1
valid_sources[0x0a]	6775	1			T3	27		T5	3		T6	2
valid_sources[0x0b]	6479	1			T3	31		T5	3		T6	24
valid_sources[0x0c]	23203	1			T3	30		T6	7		T9	3
valid_sources[0x0d]	7444	1			T3	18		T5	2		T6	9
valid_sources[0x0e]	6879	1			T3	24		T5	3		T6	7
valid_sources[0x0f]	17279	1			T3	27		T6	12		T9	4
valid_sources[0x10]	9829	1			T3	18		T5	6		T6	3
valid_sources[0x11]	12174	1			T3	51		T5	1		T6	1
valid_sources[0x12]	11380	1			T3	45		T5	5		T6	9
valid_sources[0x13]	8135	1			T3	32		T5	6		T8	3
valid_sources[0x14]	6666	1			T3	29		T5	5		T6	11
valid_sources[0x15]	6642	1			T3	17		T5	1		T6	13
valid_sources[0x16]	14103	1			T3	20		T5	3		T9	2
valid_sources[0x17]	9564	1			T3	18		T5	2		T6	5
valid_sources[0x18]	9596	1			T3	24		T5	3		T6	10
valid_sources[0x19]	26482	1			T3	42		T5	3		T6	12
valid_sources[0x1a]	9319	1			T3	38		T5	6		T6	20
valid_sources[0x1b]	6713	1			T3	29		T5	3		T6	16
valid_sources[0x1c]	12318	1			T3	23		T5	3		T6	2
valid_sources[0x1d]	6789	1			T3	22		T5	2		T6	8
valid_sources[0x1e]	6825	1			T3	39		T5	2		T6	42
valid_sources[0x1f]	6953	1			T3	42		T5	6		T9	5
valid_sources[0x20]	6841	1			T3	29		T5	5		T6	7
valid_sources[0x21]	7368	1			T3	20		T5	3		T6	12
valid_sources[0x22]	7603	1			T3	23		T5	7		T6	20
valid_sources[0x23]	7538	1			T3	24		T5	4		T6	25
valid_sources[0x24]	11404	1			T3	19		T5	1		T6	2
valid_sources[0x25]	9869	1			T3	13		T5	3		T6	13
valid_sources[0x26]	12048	1			T3	28		T5	8		T6	3
valid_sources[0x27]	7007	1			T3	25		T5	3		T6	4
valid_sources[0x28]	11274	1			T3	23		T5	7		T6	20
valid_sources[0x29]	9837	1			T3	39		T5	1		T9	22
valid_sources[0x2a]	7242	1			T3	27		T5	4		T6	5
valid_sources[0x2b]	6416	1			T3	10		T6	15		T9	4
valid_sources[0x2c]	11267	1			T3	16		T5	3		T6	9
valid_sources[0x2d]	11215	1			T3	17		T5	8		T6	19
valid_sources[0x2e]	7504	1			T3	28		T5	4		T6	15
valid_sources[0x2f]	10762	1			T3	26		T5	4		T6	5
valid_sources[0x30]	11494	1			T3	31		T5	5		T6	17
valid_sources[0x31]	11670	1			T3	28		T5	6		T6	12
valid_sources[0x32]	6907	1			T3	29		T5	3		T6	4
valid_sources[0x33]	6719	1			T3	10		T5	3		T6	9
valid_sources[0x34]	10797	1			T3	25		T5	5		T6	8
valid_sources[0x35]	6459	1			T3	8		T5	8		T6	22
valid_sources[0x36]	12268	1			T3	41		T5	6		T6	7
valid_sources[0x37]	13429	1			T3	24		T5	8		T6	4
valid_sources[0x38]	28771	1			T3	17		T5	6		T6	8
valid_sources[0x39]	9520	1			T3	30		T5	3		T9	2
valid_sources[0x3a]	9716	1			T3	24		T5	962		T6	6
valid_sources[0x3b]	15563	1			T3	18		T5	2		T6	10
valid_sources[0x3c]	7587	1			T3	27		T6	6		T9	9
valid_sources[0x3d]	6880	1			T3	34		T5	3		T6	9
valid_sources[0x3e]	13479	1			T3	9		T5	4		T6	27
valid_sources[0x3f]	6606	1			T3	27		T5	2		T6	4
valid_sources[0x40]	7721	1			T3	27		T5	1		T6	12
valid_sources[0x41]	11804	1			T3	45		T5	6		T6	7
valid_sources[0x42]	8716	1			T3	23		T5	1		T6	5
valid_sources[0x43]	10025	1			T3	32		T5	2		T6	4
valid_sources[0x44]	7606	1			T3	18		T6	2		T9	5
valid_sources[0x45]	6581	1			T3	18		T5	1		T6	26
valid_sources[0x46]	7166	1			T3	30		T5	5		T6	2
valid_sources[0x47]	6599	1			T3	24		T5	4		T6	19
valid_sources[0x48]	11068	1			T3	24		T5	4		T6	6
valid_sources[0x49]	7961	1			T3	17		T5	5		T6	11
valid_sources[0x4a]	7208	1			T3	25		T5	1		T6	15
valid_sources[0x4b]	13411	1			T3	23		T5	2		T6	8
valid_sources[0x4c]	6959	1			T3	32		T5	3		T6	5
valid_sources[0x4d]	7310	1			T3	37		T5	5		T9	76
valid_sources[0x4e]	13610	1			T3	26		T5	9		T6	31
valid_sources[0x4f]	13897	1			T3	14		T5	1		T6	13
valid_sources[0x50]	7107	1			T3	38		T5	6		T6	16
valid_sources[0x51]	6596	1			T3	12		T5	5		T6	17
valid_sources[0x52]	9855	1			T3	18		T5	2		T6	5
valid_sources[0x53]	7594	1			T3	20		T5	3		T6	9
valid_sources[0x54]	7506	1			T3	10		T5	5		T6	31
valid_sources[0x55]	9530	1			T3	30		T5	7		T6	10
valid_sources[0x56]	6613	1			T3	21		T6	2		T9	1
valid_sources[0x57]	7295	1			T3	25		T5	4		T6	23
valid_sources[0x58]	8915	1			T3	20		T5	2		T6	1
valid_sources[0x59]	6568	1			T3	9		T5	4		T6	10
valid_sources[0x5a]	6690	1			T3	20		T5	10		T6	11
valid_sources[0x5b]	16070	1			T3	21		T5	10		T6	11
valid_sources[0x5c]	6921	1			T3	19		T5	7		T6	24
valid_sources[0x5d]	7389	1			T3	19		T5	7		T6	11
valid_sources[0x5e]	13977	1			T3	24		T5	3		T6	23
valid_sources[0x5f]	10732	1			T3	17		T5	8		T6	30
valid_sources[0x60]	7057	1			T3	27		T5	4		T6	18
valid_sources[0x61]	6830	1			T3	16		T5	4		T6	13
valid_sources[0x62]	6997	1			T3	29		T5	4		T6	16
valid_sources[0x63]	6613	1			T3	38		T5	7		T9	1
valid_sources[0x64]	6713	1			T3	21		T5	4		T6	11
valid_sources[0x65]	7079	1			T3	25		T5	1		T6	10
valid_sources[0x66]	6670	1			T3	25		T5	3		T6	30
valid_sources[0x67]	9558	1			T1	655		T3	23		T5	4
valid_sources[0x68]	10782	1			T3	56		T5	2		T6	18
valid_sources[0x69]	15692	1			T3	27		T5	4		T6	32
valid_sources[0x6a]	6605	1			T3	13		T5	2		T6	19
valid_sources[0x6b]	18236	1			T3	23		T5	7		T6	16
valid_sources[0x6c]	10949	1			T3	20		T9	4		T10	6
valid_sources[0x6d]	9288	1			T3	21		T5	7		T6	22
valid_sources[0x6e]	7169	1			T3	25		T5	6		T6	10
valid_sources[0x6f]	6935	1			T3	24		T5	1		T6	14
valid_sources[0x70]	8988	1			T3	16		T5	4		T6	1
valid_sources[0x71]	10796	1			T3	16		T5	2		T6	35
valid_sources[0x72]	11078	1			T3	8		T5	3		T6	15
valid_sources[0x73]	8316	1			T3	14		T5	4		T6	17
valid_sources[0x74]	8114	1			T3	24		T5	5		T6	3
valid_sources[0x75]	9270	1			T3	28		T5	5		T6	11
valid_sources[0x76]	6671	1			T3	16		T5	6		T6	22
valid_sources[0x77]	7910	1			T3	23		T5	3		T6	12
valid_sources[0x78]	7899	1			T3	12		T5	2		T9	6
valid_sources[0x79]	7858	1			T3	8		T6	9		T9	1
valid_sources[0x7a]	18184	1			T3	68		T5	3		T6	4
valid_sources[0x7b]	8979	1			T3	24		T5	1		T6	23
valid_sources[0x7c]	10207	1			T3	31		T5	6		T6	12
valid_sources[0x7d]	10960	1			T3	22		T5	8		T6	8
valid_sources[0x7e]	7144	1			T3	14		T5	6		T6	17
valid_sources[0x7f]	8196	1			T3	15		T5	5		T6	6
valid_sources[0x80]	8629	1			T3	9		T5	3		T6	28

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1042360

1

T2

1270

T3

2792

T4

43

values[0x0]

all_enables

biggest_size

78777

1

T1

166

T2

93

T3

136

values[0x1]

all_enables

biggest_size

56437

1

T1

93

T2

58

T3

91