Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.67	86.67	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	86.67	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.67	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	6	39	86.67

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	5	11	68.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	27942	1			T1	176		T2	21		T3	17
auto[PWRUP]	117	1			T10	1		T53	1		T39	1
auto[ONEST_0]	62	1			T1	1		T53	2		T37	1
auto[ONEST_021]	12	1			T53	1		T57	1		T59	1
auto[ONEST_1]	82	1			T1	1		T10	1		T53	1
auto[ONEST_DONE]	2	1			T176	1		T177	1		-	-
auto[LP_0]	119	1			T1	1		T10	1		T53	4
auto[LP_021]	24	1			T16	1		T55	2		T49	1
auto[LP_1]	135	1			T10	2		T53	1		T37	1
auto[LP_EVAL]	66	1			T17	1		T54	1		T170	1
auto[LP_SLP]	461	1			T1	7		T10	5		T53	5
auto[LP_PWRUP]	26	1			T10	1		T91	1		T178	1
auto[NP_0]	156	1			T1	3		T10	1		T53	3
auto[NP_021]	29	1			T179	1		T180	2		T181	1
auto[NP_1]	148	1			T1	1		T10	1		T53	2
auto[NP_EVAL]	33	1			T10	1		T53	1		T16	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

8

1

T49

1

T171

1

T182

1

min

27399

1

T1

172

T2

21

T3

17

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27404	1			T1	172		T2	21		T3	17
pow[0x1]	9	1			T57	1		T183	1		T180	1
pow[0x2]	13	1			T57	2		T179	1		T184	1
pow[0x3]	43	1			T1	1		T16	1		T17	1
pow[0x4]	61	1			T53	1		T54	2		T57	1
pow[0x5]	135	1			T53	4		T37	2		T57	2
pow[0x6]	264	1			T1	4		T10	5		T53	5
pow[0x7]	510	1			T1	5		T10	4		T53	7

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

213

1

T1

3

T10

2

T53

4

min

26960

1

T1

165

T2

21

T3

17

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	5	11	68.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x6]	0	1	1
pow[0x7]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	26960	1			T1	165		T2	21		T3	17
pow[0x2]	1	1			T185	1		-	-		-	-
pow[0x5]	2	1			T186	1		T187	1		-	-
pow[0x8]	3	1			T188	1		T189	1		T104	1
pow[0x9]	9	1			T57	1		T190	1		T191	1
pow[0xa]	19	1			T53	1		T49	1		T179	1
pow[0xb]	45	1			T16	1		T54	1		T170	1
pow[0xc]	60	1			T39	1		T17	1		T54	2
pow[0xd]	154	1			T1	2		T39	1		T16	1
pow[0xe]	267	1			T1	2		T10	4		T53	2
pow[0xf]	549	1			T1	5		T10	8		T53	10