Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.33	93.33	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	93.33	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.33	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	3	42	93.33

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	2	14	87.50	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2245	1			T1	12		T3	5		T10	13
auto[PWRUP]	135	1			T1	1		T53	1		T37	1
auto[ONEST_0]	77	1			T10	2		T53	1		T37	2
auto[ONEST_021]	25	1			T53	1		T57	1		T171	2
auto[ONEST_1]	82	1			T1	1		T53	3		T54	1
auto[ONEST_DONE]	4	1			T39	1		T182	1		T323	1
auto[LP_0]	127	1			T10	2		T53	1		T26	1
auto[LP_021]	19	1			T54	2		T171	3		T324	2
auto[LP_1]	139	1			T1	2		T10	1		T53	4
auto[LP_EVAL]	60	1			T1	1		T10	1		T39	1
auto[LP_SLP]	490	1			T1	5		T10	4		T53	6
auto[LP_PWRUP]	28	1			T1	1		T57	1		T48	1
auto[NP_0]	223	1			T1	2		T10	4		T37	1
auto[NP_021]	48	1			T53	1		T37	1		T39	1
auto[NP_1]	223	1			T1	1		T10	1		T53	2
auto[NP_EVAL]	29	1			T53	2		T15	1		T16	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

10

1

T54

1

T20

1

T325

1

min

1899

1

T1

8

T3

5

T10

6

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1919	1			T1	8		T3	5		T10	7
pow[0x1]	8	1			T16	1		T55	1		T326	1
pow[0x2]	13	1			T170	1		T55	1		T91	1
pow[0x3]	38	1			T1	2		T16	1		T55	1
pow[0x4]	58	1			T1	1		T53	1		T54	2
pow[0x5]	119	1			T1	1		T10	2		T53	1
pow[0x6]	274	1			T53	6		T16	1		T17	2
pow[0x7]	511	1			T1	4		T10	6		T53	10

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

204

1

T1

4

T10

4

T53

1

min

1323

1

T3

5

T10

2

T53

2

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	2	14	87.50

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1
pow[0x7]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1329	1			T3	5		T10	2		T53	2
pow[0x1]	16	1			T37	1		T15	1		T17	1
pow[0x2]	29	1			T39	2		T16	4		T49	1
pow[0x3]	54	1			T37	1		T39	1		T26	4
pow[0x4]	53	1			T37	1		T15	5		T17	1
pow[0x6]	2	1			T327	1		T323	1		-	-
pow[0x8]	5	1			T328	1		T329	1		T323	1
pow[0x9]	10	1			T1	1		T10	1		T91	1
pow[0xa]	13	1			T91	2		T330	1		T190	2
pow[0xb]	25	1			T171	1		T180	1		T184	1
pow[0xc]	69	1			T1	2		T53	2		T57	1
pow[0xd]	147	1			T1	1		T53	2		T54	1
pow[0xe]	273	1			T1	4		T10	4		T53	3
pow[0xf]	547	1			T1	5		T10	5		T53	10