Unified Coverage Report :: Module :: adc_ctrl_core

Module : adc_ctrl_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_adc_ctrl_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.83	100.00	99.76		100.00	99.37	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_ctrl_fsm	99.75	100.00	100.00		100.00	98.73	100.00
u_adc_ctrl_intr	99.00	100.00	96.00			100.00	100.00
u_oneshot_done_sync	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
TOTAL		63	63	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	73	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	213	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	8	8
63	8	8
72	1	1
73	1	1
74	1	1
75	1	1
83	1	1
86	1	1
87	1	1
88	1	1
89	1	1
104	8	8
107	8	8
117	8	8
121	8	8
137	1	1
138	1	1
140	1	1
141	1	1
145	1	1
213	1	1

---

Cond Coverage for Module : adc_ctrl_core

	Total	Covered	Percent
Conditions	293	293	100.00
Logical	293	293	100.00
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION (reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done : (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0))
             -----------------1----------------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T3,T7,T9

 LINE       83
 SUB-EXPRESSION (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0)
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][0].cond)) ? ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v)) : ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v)))

-1-	Status	Tests
0	Covered	T3,T6,T9
1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T9,T11
0	1	Covered	T6,T9,T11
1	0	Covered	T3,T6,T9

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][1].cond)) ? ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v)) : ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v)))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T3,T6

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][2].cond)) ? ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v)) : ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v)))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T7
1	0	Covered	T2,T3,T5
1	1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T8
0	1	Covered	T1,T6,T8
1	0	Covered	T1,T3,T6

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][3].cond)) ? ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v)) : ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v)))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T3,T6

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][4].cond)) ? ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v)) : ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v)))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T3,T5
1	1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T8
0	1	Covered	T1,T6,T9
1	0	Covered	T1,T3,T6

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][5].cond)) ? ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v)) : ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v)))

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T6,T7

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][6].cond)) ? ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v)) : ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v)))

-1-	Status	Tests
0	Covered	T1,T3,T8
1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T10
0	1	Covered	T1,T8,T10
1	0	Covered	T1,T3,T8

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][7].cond)) ? ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v)) : ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v)))

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][0].cond)) ? ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v)) : ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v)))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T9
0	1	Covered	T1,T6,T9
1	0	Covered	T1,T3,T6

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][1].cond)) ? ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v)) : ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v)))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T3,T6

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][2].cond)) ? ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v)) : ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v)))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T8
0	1	Covered	T1,T6,T8
1	0	Covered	T1,T3,T6

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][3].cond)) ? ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v)) : ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v)))

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T6,T7

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][4].cond)) ? ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v)) : ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v)))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T3,T5
1	1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T8
0	1	Covered	T1,T6,T8
1	0	Covered	T1,T3,T6

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][5].cond)) ? ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v)) : ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v)))

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T6,T7

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][6].cond)) ? ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v)) : ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v)))

-1-	Status	Tests
0	Covered	T1,T3,T8
1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T10
0	1	Covered	T1,T8,T10
1	0	Covered	T1,T3,T8

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][7].cond)) ? ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v)) : ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v)))

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][0].en, aon_filter_ctl[1][0].en})) & 
      2  (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en)) & 
      3  (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T2
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T1,T2,T5
1	1	1	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[0] & aon_filter_ctl[0][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[0] & aon_filter_ctl[1][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T2,T3

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][1].en, aon_filter_ctl[1][1].en})) & 
      2  (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en)) & 
      3  (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T2
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T1,T2,T5
1	1	1	Covered	T1,T2,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[1] & aon_filter_ctl[0][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T2,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[1] & aon_filter_ctl[1][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T2,T5

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][2].en, aon_filter_ctl[1][2].en})) & 
      2  (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en)) & 
      3  (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T2
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T1,T2,T5
1	1	1	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[2] & aon_filter_ctl[0][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[2] & aon_filter_ctl[1][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T2,T3

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][3].en, aon_filter_ctl[1][3].en})) & 
      2  (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en)) & 
      3  (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T2
1	0	1	Covered	T2,T5,T6
1	1	0	Covered	T2,T3,T5
1	1	1	Covered	T2,T5,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Covered	T2,T3,T5
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[3] & aon_filter_ctl[0][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T4,T1,T2
1	1	Covered	T2,T3,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T5
0	1	Covered	T2,T5,T6
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[3] & aon_filter_ctl[1][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T4,T1,T2
1	1	Covered	T2,T5,T6

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][4].en, aon_filter_ctl[1][4].en})) & 
      2  (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en)) & 
      3  (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T2
1	0	1	Covered	T2,T5,T6
1	1	0	Covered	T2,T5,T6
1	1	1	Covered	T2,T3,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Covered	T2,T3,T5
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[4] & aon_filter_ctl[0][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T4,T1,T2
1	1	Covered	T2,T3,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Covered	T2,T3,T5
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[4] & aon_filter_ctl[1][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T4,T1,T2
1	1	Covered	T2,T3,T5

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][5].en, aon_filter_ctl[1][5].en})) & 
      2  (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en)) & 
      3  (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T2
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T1,T2,T5
1	1	1	Covered	T1,T2,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[5] & aon_filter_ctl[0][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T2,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[5] & aon_filter_ctl[1][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T2,T5

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][6].en, aon_filter_ctl[1][6].en})) & 
      2  (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en)) & 
      3  (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T2
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T1,T2,T5
1	1	1	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[6] & aon_filter_ctl[0][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[6] & aon_filter_ctl[1][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T2,T3

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][7].en, aon_filter_ctl[1][7].en})) & 
      2  (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en)) & 
      3  (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T2
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T1,T2,T5
1	1	1	Covered	T1,T2,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[7] & aon_filter_ctl[0][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T2,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[7] & aon_filter_ctl[1][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T2,T5

 LINE       121
 EXPRESSION (adc_ctrl_done && match[0])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       121
 EXPRESSION (adc_ctrl_done && match[1])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       121
 EXPRESSION (adc_ctrl_done && match[2])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       121
 EXPRESSION (adc_ctrl_done && match[3])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T6

 LINE       121
 EXPRESSION (adc_ctrl_done && match[4])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T5
1	1	Covered	T2,T3,T5

 LINE       121
 EXPRESSION (adc_ctrl_done && match[5])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       121
 EXPRESSION (adc_ctrl_done && match[6])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       121
 EXPRESSION (adc_ctrl_done && match[7])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       140
 EXPRESSION (aon_fsm_trans | reg2hw_i.filter_status.trans.q)
             ------1------   ---------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Covered	T3,T5,T6
1	0	Covered	T3,T5,T6

 LINE       145
 EXPRESSION (((|(reg2hw_i.filter_status.match.q & reg2hw_i.adc_wakeup_ctl.match_en.q))) || (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q))
             -------------------------------------1------------------------------------    ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Covered	T5,T6,T10
1	0	Covered	T3,T5,T6

 LINE       145
 SUB-EXPRESSION (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q)
                 ---------------1--------------   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T10
1	0	Covered	T3,T6,T9
1	1	Covered	T5,T6,T10

---

Branch Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	83	3	3	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	83	(reg2hw_i.adc_en_ctl.oneshot_mode.q) ? 
-2-:	83	(reg2hw_i.adc_en_ctl.adc_enable.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T7,T9
0	1	Covered	T1,T2,T3
0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T3,T6,T9

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T1,T3,T8

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T1,T3,T8

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T1,T2,T5

---

Assert Coverage for Module : adc_ctrl_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	33	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	33	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxFilters_A	32620087	32346198	0	0
gen_filter_match[0].MatchCheck00_A	32620087	9569732	0	0
gen_filter_match[0].MatchCheck01_A	32620087	2576720	0	0
gen_filter_match[0].MatchCheck10_A	32620087	2347162	0	0
gen_filter_match[0].MatchCheck11_A	32620087	17852584	0	0
gen_filter_match[1].MatchCheck00_A	32620087	10669981	0	0
gen_filter_match[1].MatchCheck01_A	32620087	1371141	0	0
gen_filter_match[1].MatchCheck10_A	32620087	1147208	0	0
gen_filter_match[1].MatchCheck11_A	32620087	19157868	0	0
gen_filter_match[2].MatchCheck00_A	32620087	11825067	0	0
gen_filter_match[2].MatchCheck01_A	32620087	638195	0	0
gen_filter_match[2].MatchCheck10_A	32620087	443768	0	0
gen_filter_match[2].MatchCheck11_A	32620087	19439168	0	0
gen_filter_match[3].MatchCheck00_A	32620087	11834816	0	0
gen_filter_match[3].MatchCheck01_A	32620087	448535	0	0
gen_filter_match[3].MatchCheck10_A	32620087	243051	0	0
gen_filter_match[3].MatchCheck11_A	32620087	19819796	0	0
gen_filter_match[4].MatchCheck00_A	32620087	12027379	0	0
gen_filter_match[4].MatchCheck01_A	32620087	77499	0	0
gen_filter_match[4].MatchCheck10_A	32620087	32798	0	0
gen_filter_match[4].MatchCheck11_A	32620087	20208522	0	0
gen_filter_match[5].MatchCheck00_A	32620087	11460123	0	0
gen_filter_match[5].MatchCheck01_A	32620087	10	0	0
gen_filter_match[5].MatchCheck10_A	32620087	32610	0	0
gen_filter_match[5].MatchCheck11_A	32620087	20853455	0	0
gen_filter_match[6].MatchCheck00_A	32620087	11473026	0	0
gen_filter_match[6].MatchCheck01_A	32620087	96908	0	0
gen_filter_match[6].MatchCheck10_A	32620087	68700	0	0
gen_filter_match[6].MatchCheck11_A	32620087	20707564	0	0
gen_filter_match[7].MatchCheck00_A	32620087	11314055	0	0
gen_filter_match[7].MatchCheck01_A	32620087	199459	0	0
gen_filter_match[7].MatchCheck10_A	32620087	283562	0	0
gen_filter_match[7].MatchCheck11_A	32620087	20549122	0	0

MaxFilters_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32620087	32346198	0	0
T1	64631	64565	0	0
T2	64418	64357	0	0
T3	3690	3102	0	0
T4	103	5	0	0
T5	42190	42109	0	0
T6	113813	113725	0	0
T7	60031	57181	0	0
T8	32871	32804	0	0
T9	111315	105743	0	0
T10	64272	64215	0	0

gen_filter_match[0].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32620087	9569732	0	0
T1	64631	32389	0	0
T2	64418	4	0	0
T3	3690	2990	0	0
T4	103	5	0	0
T5	42190	3	0	0
T6	113813	71395	0	0
T7	60031	23788	0	0
T8	32871	32804	0	0
T9	111315	103545	0	0
T10	64272	32119	0	0

gen_filter_match[0].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32620087	2576720	0	0
T24	928	0	0	0
T32	15782	0	0	0
T52	93	0	0	0
T120	32818	32741	0	0
T121	33084	33003	0	0
T122	0	33286	0	0
T123	0	33609	0	0
T124	0	32729	0	0
T125	0	35986	0	0
T126	0	39501	0	0
T127	0	38071	0	0
T128	0	36449	0	0
T129	0	40007	0	0
T130	32888	0	0	0
T131	6037	0	0	0
T132	32428	0	0	0
T133	32998	0	0	0
T134	64126	0	0	0

gen_filter_match[0].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32620087	2347162	0	0
T5	42190	1	0	0
T6	113813	0	0	0
T7	60031	0	0	0
T8	32871	0	0	0
T9	111315	0	0	0
T10	64272	0	0	0
T11	113782	0	0	0
T12	567	0	0	0
T21	121862	0	0	0
T29	0	32182	0	0
T93	0	31558	0	0
T116	1139	0	0	0
T123	0	47151	0	0
T132	0	32357	0	0
T135	0	1	0	0
T136	0	32259	0	0
T137	0	2	0	0
T138	0	1	0	0
T139	0	34010	0	0

gen_filter_match[0].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32620087	17852584	0	0
T1	64631	32176	0	0
T2	64418	64353	0	0
T3	3690	112	0	0
T5	42190	42105	0	0
T6	113813	42330	0	0
T7	60031	33393	0	0
T8	32871	0	0	0
T9	111315	2198	0	0
T10	64272	32096	0	0
T11	113782	76616	0	0
T12	0	207	0	0

gen_filter_match[1].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32620087	10669981	0	0
T1	64631	3	0	0
T2	64418	4	0	0
T3	3690	3102	0	0
T4	103	5	0	0
T5	42190	3	0	0
T6	113813	32403	0	0
T7	60031	24168	0	0
T8	32871	3	0	0
T9	111315	37635	0	0
T10	64272	32099	0	0

gen_filter_match[1].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32620087	1371141	0	0
T9	111315	34981	0	0
T10	64272	0	0	0
T11	113782	41469	0	0
T12	567	0	0	0
T21	121862	0	0	0
T29	96736	0	0	0
T30	107143	0	0	0
T51	82	0	0	0
T84	0	32213	0	0
T90	0	1	0	0
T92	0	32162	0	0
T116	1139	0	0	0
T126	0	31775	0	0
T127	0	35916	0	0
T140	0	33452	0	0
T141	0	40373	0	0
T142	0	32189	0	0
T143	99488	0	0	0

gen_filter_match[1].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32620087	1147208	0	0
T5	42190	1	0	0
T6	113813	0	0	0
T7	60031	0	0	0
T8	32871	0	0	0
T9	111315	1	0	0
T10	64272	0	0	0
T11	113782	0	0	0
T12	567	0	0	0
T13	0	1	0	0
T21	121862	0	0	0
T116	1139	0	0	0
T117	0	32860	0	0
T119	0	39187	0	0
T135	0	1	0	0
T137	0	2	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	0	32914	0	0

gen_filter_match[1].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32620087	19157868	0	0
T1	64631	64562	0	0
T2	64418	64353	0	0
T3	3690	0	0	0
T5	42190	42105	0	0
T6	113813	81322	0	0
T7	60031	33013	0	0
T8	32871	32801	0	0
T9	111315	33126	0	0
T10	64272	32116	0	0
T11	113782	37098	0	0
T21	0	121787	0	0

gen_filter_match[2].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32620087	11825067	0	0
T1	64631	32389	0	0
T2	64418	4	0	0
T3	3690	350	0	0
T4	103	5	0	0
T5	42190	3	0	0
T6	113813	3	0	0
T7	60031	24168	0	0
T8	32871	32804	0	0
T9	111315	105743	0	0
T10	64272	32119	0	0

gen_filter_match[2].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32620087	638195	0	0
T6	113813	42330	0	0
T7	60031	33013	0	0
T8	32871	0	0	0
T9	111315	0	0	0
T10	64272	0	0	0
T11	113782	37098	0	0
T12	567	0	0	0
T21	121862	0	0	0
T51	82	0	0	0
T69	0	1	0	0
T116	1139	0	0	0
T117	0	35126	0	0
T147	0	31790	0	0
T148	0	32278	0	0
T149	0	33281	0	0
T150	0	35327	0	0
T151	0	119	0	0

gen_filter_match[2].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32620087	443768	0	0
T5	42190	1	0	0
T6	113813	0	0	0
T7	60031	0	0	0
T8	32871	0	0	0
T9	111315	0	0	0
T10	64272	0	0	0
T11	113782	0	0	0
T12	567	0	0	0
T13	0	2	0	0
T21	121862	0	0	0
T30	0	1	0	0
T90	0	1	0	0
T92	0	32928	0	0
T116	1139	0	0	0
T135	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0
T145	0	1	0	0
T152	0	35033	0	0

gen_filter_match[2].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32620087	19439168	0	0
T1	64631	32176	0	0
T2	64418	64353	0	0
T3	3690	2752	0	0
T5	42190	42105	0	0
T6	113813	71392	0	0
T7	60031	0	0	0
T8	32871	0	0	0
T9	111315	0	0	0
T10	64272	32096	0	0
T11	113782	41469	0	0
T21	0	121787	0	0
T29	0	96638	0	0
T30	0	72135	0	0

gen_filter_match[3].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32620087	11834816	0	0
T1	64631	64565	0	0
T2	64418	4	0	0
T3	3690	350	0	0
T4	103	5	0	0
T5	42190	3	0	0
T6	113813	38995	0	0
T7	60031	57181	0	0
T8	32871	3	0	0
T9	111315	37635	0	0
T10	64272	64215	0	0

gen_filter_match[3].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32620087	448535	0	0
T8	32871	32801	0	0
T9	111315	33126	0	0
T10	64272	0	0	0
T11	113782	0	0	0
T12	567	0	0	0
T13	0	32	0	0
T21	121862	0	0	0
T29	96736	0	0	0
T30	107143	0	0	0
T51	82	0	0	0
T69	0	1	0	0
T90	0	35523	0	0
T116	1139	0	0	0
T119	0	31656	0	0
T150	0	33030	0	0
T153	0	52374	0	0
T154	0	32079	0	0
T155	0	1	0	0

gen_filter_match[3].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32620087	243051	0	0
T5	42190	1	0	0
T6	113813	0	0	0
T7	60031	0	0	0
T8	32871	0	0	0
T9	111315	1	0	0
T10	64272	0	0	0
T11	113782	0	0	0
T12	567	0	0	0
T21	121862	0	0	0
T90	0	1	0	0
T116	1139	0	0	0
T135	0	1	0	0
T138	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0
T156	0	32818	0	0
T157	0	2	0	0
T158	0	33129	0	0

gen_filter_match[3].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32620087	19819796	0	0
T2	64418	64353	0	0
T3	3690	2752	0	0
T5	42190	42105	0	0
T6	113813	74730	0	0
T7	60031	0	0	0
T8	32871	0	0	0
T9	111315	34981	0	0
T10	64272	0	0	0
T11	113782	0	0	0
T12	567	207	0	0
T21	0	121787	0	0
T143	0	99423	0	0
T159	0	32947	0	0
T160	0	98585	0	0

gen_filter_match[4].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32620087	12027379	0	0
T1	64631	64565	0	0
T2	64418	4	0	0
T3	3690	350	0	0
T4	103	5	0	0
T5	42190	3	0	0
T6	113813	38995	0	0
T7	60031	57181	0	0
T8	32871	3	0	0
T9	111315	37634	0	0
T10	64272	64215	0	0

gen_filter_match[4].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32620087	77499	0	0
T30	107143	1	0	0
T31	26065	0	0	0
T93	96675	0	0	0
T94	98002	0	0	0
T117	69403	0	0	0
T137	0	2	0	0
T143	99488	0	0	0
T149	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T159	33048	0	0	0
T160	98682	0	0	0
T161	0	36359	0	0
T162	0	1	0	0
T163	0	1	0	0
T164	0	1	0	0
T165	40084	0	0	0
T166	64112	0	0	0

gen_filter_match[4].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32620087	32798	0	0
T5	42190	2	0	0
T6	113813	0	0	0
T7	60031	0	0	0
T8	32871	0	0	0
T9	111315	2	0	0
T10	64272	0	0	0
T11	113782	0	0	0
T12	567	0	0	0
T13	0	1	0	0
T21	121862	0	0	0
T29	0	1	0	0
T116	1139	0	0	0
T135	0	2	0	0
T137	0	2	0	0
T138	0	1	0	0
T145	0	1	0	0
T156	0	1	0	0
T165	0	1	0	0

gen_filter_match[4].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32620087	20208522	0	0
T2	64418	64353	0	0
T3	3690	2752	0	0
T5	42190	42104	0	0
T6	113813	74730	0	0
T7	60031	0	0	0
T8	32871	32801	0	0
T9	111315	68107	0	0
T10	64272	0	0	0
T11	113782	76616	0	0
T12	567	207	0	0
T21	0	121787	0	0
T29	0	32181	0	0

gen_filter_match[5].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32620087	11460123	0	0
T1	64631	3	0	0
T2	64418	4	0	0
T3	3690	3102	0	0
T4	103	5	0	0
T5	42190	3	0	0
T6	113813	71395	0	0
T7	60031	57181	0	0
T8	32871	3	0	0
T9	111315	105743	0	0
T10	64272	3	0	0

gen_filter_match[5].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32620087	10	0	0
T29	96736	1	0	0
T30	107143	1	0	0
T31	26065	0	0	0
T69	0	1	0	0
T70	0	1	0	0
T93	96675	0	0	0
T94	98002	0	0	0
T137	0	2	0	0
T143	99488	0	0	0
T155	0	1	0	0
T159	33048	0	0	0
T160	98682	0	0	0
T165	40084	0	0	0
T166	64112	0	0	0
T167	0	1	0	0
T168	0	2	0	0

gen_filter_match[5].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32620087	32610	0	0
T5	42190	2	0	0
T6	113813	0	0	0
T7	60031	0	0	0
T8	32871	0	0	0
T9	111315	0	0	0
T10	64272	0	0	0
T11	113782	0	0	0
T12	567	0	0	0
T21	121862	0	0	0
T29	0	1	0	0
T30	0	1	0	0
T116	1139	0	0	0
T134	0	1	0	0
T135	0	2	0	0
T137	0	2	0	0
T144	0	1	0	0
T145	0	1	0	0
T156	0	1	0	0
T165	0	1	0	0

gen_filter_match[5].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32620087	20853455	0	0
T1	64631	64562	0	0
T2	64418	64353	0	0
T3	3690	0	0	0
T5	42190	42104	0	0
T6	113813	42330	0	0
T7	60031	0	0	0
T8	32871	32801	0	0
T9	111315	0	0	0
T10	64272	64212	0	0
T11	113782	72245	0	0
T21	0	121787	0	0
T29	0	64455	0	0
T30	0	69560	0	0

gen_filter_match[6].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32620087	11473026	0	0
T1	64631	32389	0	0
T2	64418	4	0	0
T3	3690	350	0	0
T4	103	5	0	0
T5	42190	4	0	0
T6	113813	38995	0	0
T7	60031	57181	0	0
T8	32871	3	0	0
T9	111315	70761	0	0
T10	64272	64215	0	0

gen_filter_match[6].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32620087	96908	0	0
T69	0	1	0	0
T93	96675	32660	0	0
T94	98002	0	0	0
T117	69403	0	0	0
T118	900	0	0	0
T119	103650	0	0	0
T128	0	1	0	0
T135	33612	0	0	0
T136	32358	0	0	0
T149	0	1	0	0
T156	0	1	0	0
T162	0	1	0	0
T165	40084	0	0	0
T166	64112	0	0	0
T169	0	1	0	0
T170	0	32512	0	0
T171	0	31723	0	0
T172	0	2	0	0
T173	32326	0	0	0

gen_filter_match[6].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32620087	68700	0	0
T5	42190	1	0	0
T6	113813	0	0	0
T7	60031	0	0	0
T8	32871	0	0	0
T9	111315	1	0	0
T10	64272	0	0	0
T11	113782	0	0	0
T12	567	0	0	0
T21	121862	0	0	0
T29	0	1	0	0
T30	0	1	0	0
T116	1139	0	0	0
T134	0	1	0	0
T135	0	1	0	0
T137	0	2	0	0
T138	0	1	0	0
T145	0	1	0	0
T165	0	1	0	0

gen_filter_match[6].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32620087	20707564	0	0
T1	64631	32176	0	0
T2	64418	64353	0	0
T3	3690	2752	0	0
T5	42190	42104	0	0
T6	113813	74730	0	0
T7	60031	0	0	0
T8	32871	32801	0	0
T9	111315	34981	0	0
T10	64272	0	0	0
T11	113782	41469	0	0
T12	0	207	0	0
T21	0	121787	0	0

gen_filter_match[7].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32620087	11314055	0	0
T1	64631	32389	0	0
T2	64418	4	0	0
T3	3690	3102	0	0
T4	103	5	0	0
T5	42190	4	0	0
T6	113813	71395	0	0
T7	60031	57181	0	0
T8	32871	3	0	0
T9	111315	105743	0	0
T10	64272	32119	0	0

gen_filter_match[7].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32620087	199459	0	0
T15	646	0	0	0
T28	184	0	0	0
T70	0	1	0	0
T149	0	1	0	0
T155	0	1	0	0
T162	0	1	0	0
T164	0	1	0	0
T174	142011	32703	0	0
T175	0	31617	0	0
T176	0	1	0	0
T177	0	31215	0	0
T178	0	33228	0	0
T179	38528	0	0	0
T180	32403	0	0	0
T181	64697	0	0	0
T182	648	0	0	0
T183	78	0	0	0
T184	7242	0	0	0
T185	1182	0	0	0

gen_filter_match[7].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32620087	283562	0	0
T5	42190	1	0	0
T6	113813	0	0	0
T7	60031	0	0	0
T8	32871	0	0	0
T9	111315	0	0	0
T10	64272	0	0	0
T11	113782	0	0	0
T12	567	0	0	0
T21	121862	0	0	0
T29	0	1	0	0
T30	0	1	0	0
T116	1139	0	0	0
T134	0	1	0	0
T135	0	1	0	0
T137	0	2	0	0
T138	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T165	0	1	0	0

gen_filter_match[7].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32620087	20549122	0	0
T1	64631	32176	0	0
T2	64418	64353	0	0
T3	3690	0	0	0
T5	42190	42104	0	0
T6	113813	42330	0	0
T7	60031	0	0	0
T8	32871	32801	0	0
T9	111315	0	0	0
T10	64272	32096	0	0
T11	113782	76616	0	0
T21	0	121787	0	0
T29	0	96637	0	0
T30	0	37513	0	0