Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : adc_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.82 99.07 96.67 100.00 100.00 98.83 98.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
adc_ctrl_csr_assert 96.00 96.00
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
tlul_assert_device 100.00 100.00 100.00 100.00
u_adc_ctrl_core 99.83 100.00 99.76 100.00 99.37 100.00
u_reg 97.96 98.97 96.02 100.00 98.76 96.05

Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : adc_ctrl
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN4911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
49 1 1

Cond Coverage for Module : adc_ctrl
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       49
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------
-1--2-StatusTests
01CoveredT51,T52,T60
10CoveredT4,T1,T2
11CoveredT4,T51,T52
Toggle Coverage for Module : adc_ctrl
TotalCoveredPercent
Totals 34 34 100.00
Total Bits 368 368 100.00
Total Bits 0->1 184 184 100.00
Total Bits 1->0 184 184 100.00

Ports 34 34 100.00
Port Bits 368 368 100.00
Port Bits 0->1 184 184 100.00
Port Bits 1->0 184 184 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T1,T2 Yes T4,T1,T2 INPUT
clk_aon_i Yes Yes T4,T1,T2 Yes T4,T1,T2 INPUT
rst_ni Yes Yes T3,T7,T9 Yes T4,T1,T2 INPUT
rst_aon_ni Yes Yes T3,T7,T9 Yes T4,T1,T2 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T4,T1,T2 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T1,T2 Yes T4,T1,T2 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T3,T6,T11 Yes T3,T6,T11 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T4,T1,T2 Yes T4,T1,T2 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_source[7:0] Yes Yes T4,T1,T2 Yes T4,T1,T2 INPUT
tl_i.a_size[1:0] Yes Yes T4,T1,T2 Yes T4,T1,T2 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T4,T1,T2 Yes T4,T1,T2 INPUT
tl_i.a_valid Yes Yes T4,T1,T2 Yes T4,T1,T2 INPUT
tl_o.a_ready Yes Yes T4,T1,T2 Yes T4,T1,T2 OUTPUT
tl_o.d_error Yes Yes T3,T12,T24 Yes T3,T12,T24 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T4,*T1,*T2 Yes T4,T1,T2 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T4,T1,T2 Yes T4,T1,T2 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T4,T1,T2 Yes T4,T1,T2 OUTPUT
tl_o.d_size[1:0] Yes Yes T4,T1,T2 Yes T4,T1,T2 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T4,T1,T2 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T4,T1,T2 Yes T4,T1,T2 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T1,T2 Yes T4,T1,T2 INPUT
alert_rx_i[0].ack_p Yes Yes T4,T51,T52 Yes T4,T51,T52 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T4,T1,T2 Yes T4,T1,T2 OUTPUT
alert_tx_o[0].alert_p Yes Yes T4,T51,T52 Yes T4,T51,T52 OUTPUT
adc_o.pd Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
adc_o.channel_sel[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
adc_i.data_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
adc_i.data[9:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
intr_match_pending_o Yes Yes T3,T8,T9 Yes T3,T8,T9 OUTPUT
wkup_req_o Yes Yes T3,T5,T6 Yes T3,T5,T6 OUTPUT

*Tests covering at least one bit in the range
Assert Coverage for Module : adc_ctrl
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 7 7 100.00 7 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 7 7 100.00 7 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AdcKnown_A 2147483647 2147483647 0 0
AlertsKnown_A 2147483647 2147483647 0 0
FpvSecCmRegWeOnehotCheck_A 2147483647 80 0 0
IntrKnown 2147483647 2147483647 0 0
TlOAReadyKnown 2147483647 2147483647 0 0
TlODValidKnown 2147483647 2147483647 0 0
WakeKnown 2147483647 2147483647 0 0


AdcKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 743273 743266 0 0
T2 322096 322095 0 0
T3 240873 237828 0 0
T4 51532 51436 0 0
T5 210956 210950 0 0
T6 142269 142268 0 0
T7 288148 288119 0 0
T8 279411 279401 0 0
T9 973662 973084 0 0
T10 318154 318154 0 0

AlertsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 743273 743266 0 0
T2 322096 322095 0 0
T3 240873 237828 0 0
T4 51532 51436 0 0
T5 210956 210950 0 0
T6 142269 142268 0 0
T7 288148 288119 0 0
T8 279411 279401 0 0
T9 973662 973084 0 0
T10 318154 318154 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 80 0 0
T44 124029 20 0 0
T45 0 10 0 0
T46 0 20 0 0
T61 0 10 0 0
T62 0 20 0 0
T63 577272 0 0 0
T64 50612 0 0 0
T65 144996 0 0 0
T66 156244 0 0 0
T67 235717 0 0 0
T68 396521 0 0 0
T69 120496 0 0 0
T70 792405 0 0 0
T71 346393 0 0 0

IntrKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 743273 743266 0 0
T2 322096 322095 0 0
T3 240873 237828 0 0
T4 51532 51436 0 0
T5 210956 210950 0 0
T6 142269 142268 0 0
T7 288148 288119 0 0
T8 279411 279401 0 0
T9 973662 973084 0 0
T10 318154 318154 0 0

TlOAReadyKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 743273 743266 0 0
T2 322096 322095 0 0
T3 240873 237828 0 0
T4 51532 51436 0 0
T5 210956 210950 0 0
T6 142269 142268 0 0
T7 288148 288119 0 0
T8 279411 279401 0 0
T9 973662 973084 0 0
T10 318154 318154 0 0

TlODValidKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 743273 743266 0 0
T2 322096 322095 0 0
T3 240873 237828 0 0
T4 51532 51436 0 0
T5 210956 210950 0 0
T6 142269 142268 0 0
T7 288148 288119 0 0
T8 279411 279401 0 0
T9 973662 973084 0 0
T10 318154 318154 0 0

WakeKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 743273 743266 0 0
T2 322096 322095 0 0
T3 240873 237828 0 0
T4 51532 51436 0 0
T5 210956 210950 0 0
T6 142269 142268 0 0
T7 288148 288119 0 0
T8 279411 279401 0 0
T9 973662 973084 0 0
T10 318154 318154 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%