Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1525	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1562	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1652	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1601	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1580	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1765	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1649	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1582	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1595	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1607	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1543	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1481	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1635	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1777	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1715	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1736	0	0
adc_en_ctl_rd_A	2147483647	1330	0	0
adc_fsm_rst_rd_A	2147483647	1313	0	0
adc_intr_ctl_rd_A	2147483647	1858	0	0
adc_lp_sample_ctl_rd_A	2147483647	1317	0	0
adc_pd_ctl_rd_A	2147483647	1368	0	0
adc_sample_ctl_rd_A	2147483647	1254	0	0
adc_wakeup_ctl_rd_A	2147483647	1158	0	0
intr_enable_rd_A	2147483647	2227	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1525	0	0
T3	240873	20	0	0
T5	210956	0	0	0
T6	142269	0	0	0
T7	288148	0	0	0
T8	279411	0	0	0
T9	973662	0	0	0
T10	318154	0	0	0
T11	828883	0	0	0
T12	181235	49	0	0
T13	0	18	0	0
T14	0	45	0	0
T15	0	16	0	0
T16	0	23	0	0
T17	0	17	0	0
T18	0	18	0	0
T19	0	14	0	0
T20	0	20	0	0
T21	731186	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1562	0	0
T3	240873	25	0	0
T5	210956	0	0	0
T6	142269	0	0	0
T7	288148	0	0	0
T8	279411	0	0	0
T9	973662	0	0	0
T10	318154	0	0	0
T11	828883	0	0	0
T12	181235	41	0	0
T13	0	35	0	0
T14	0	24	0	0
T15	0	15	0	0
T16	0	45	0	0
T17	0	14	0	0
T18	0	22	0	0
T19	0	19	0	0
T20	0	23	0	0
T21	731186	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1652	0	0
T3	240873	16	0	0
T5	210956	0	0	0
T6	142269	0	0	0
T7	288148	0	0	0
T8	279411	0	0	0
T9	973662	0	0	0
T10	318154	0	0	0
T11	828883	0	0	0
T12	181235	40	0	0
T13	0	21	0	0
T14	0	33	0	0
T15	0	11	0	0
T16	0	29	0	0
T17	0	31	0	0
T18	0	19	0	0
T19	0	16	0	0
T20	0	14	0	0
T21	731186	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1601	0	0
T3	240873	21	0	0
T5	210956	0	0	0
T6	142269	0	0	0
T7	288148	0	0	0
T8	279411	0	0	0
T9	973662	0	0	0
T10	318154	0	0	0
T11	828883	0	0	0
T12	181235	34	0	0
T13	0	10	0	0
T14	0	31	0	0
T15	0	25	0	0
T16	0	22	0	0
T17	0	26	0	0
T18	0	23	0	0
T19	0	16	0	0
T20	0	3	0	0
T21	731186	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1580	0	0
T3	240873	14	0	0
T5	210956	0	0	0
T6	142269	0	0	0
T7	288148	0	0	0
T8	279411	0	0	0
T9	973662	0	0	0
T10	318154	0	0	0
T11	828883	0	0	0
T12	181235	35	0	0
T13	0	22	0	0
T14	0	46	0	0
T15	0	20	0	0
T16	0	23	0	0
T17	0	14	0	0
T18	0	25	0	0
T19	0	21	0	0
T20	0	17	0	0
T21	731186	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1765	0	0
T3	240873	20	0	0
T5	210956	0	0	0
T6	142269	0	0	0
T7	288148	0	0	0
T8	279411	0	0	0
T9	973662	0	0	0
T10	318154	0	0	0
T11	828883	0	0	0
T12	181235	46	0	0
T13	0	19	0	0
T14	0	35	0	0
T15	0	22	0	0
T16	0	23	0	0
T17	0	3	0	0
T18	0	28	0	0
T19	0	13	0	0
T20	0	11	0	0
T21	731186	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1649	0	0
T3	240873	30	0	0
T5	210956	0	0	0
T6	142269	0	0	0
T7	288148	0	0	0
T8	279411	0	0	0
T9	973662	0	0	0
T10	318154	0	0	0
T11	828883	0	0	0
T12	181235	42	0	0
T13	0	19	0	0
T14	0	27	0	0
T15	0	22	0	0
T16	0	7	0	0
T17	0	18	0	0
T18	0	25	0	0
T19	0	8	0	0
T20	0	23	0	0
T21	731186	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1582	0	0
T3	240873	22	0	0
T5	210956	0	0	0
T6	142269	0	0	0
T7	288148	0	0	0
T8	279411	0	0	0
T9	973662	0	0	0
T10	318154	0	0	0
T11	828883	0	0	0
T12	181235	31	0	0
T13	0	15	0	0
T14	0	33	0	0
T15	0	15	0	0
T16	0	21	0	0
T17	0	9	0	0
T18	0	27	0	0
T19	0	10	0	0
T20	0	12	0	0
T21	731186	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1595	0	0
T3	240873	20	0	0
T5	210956	0	0	0
T6	142269	0	0	0
T7	288148	0	0	0
T8	279411	0	0	0
T9	973662	0	0	0
T10	318154	0	0	0
T11	828883	0	0	0
T12	181235	36	0	0
T13	0	13	0	0
T14	0	29	0	0
T15	0	20	0	0
T16	0	32	0	0
T17	0	14	0	0
T18	0	18	0	0
T19	0	13	0	0
T20	0	24	0	0
T21	731186	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1607	0	0
T3	240873	19	0	0
T5	210956	0	0	0
T6	142269	0	0	0
T7	288148	0	0	0
T8	279411	0	0	0
T9	973662	0	0	0
T10	318154	0	0	0
T11	828883	0	0	0
T12	181235	28	0	0
T13	0	18	0	0
T14	0	16	0	0
T15	0	10	0	0
T16	0	27	0	0
T17	0	23	0	0
T18	0	23	0	0
T19	0	7	0	0
T20	0	18	0	0
T21	731186	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1543	0	0
T3	240873	11	0	0
T5	210956	0	0	0
T6	142269	0	0	0
T7	288148	0	0	0
T8	279411	0	0	0
T9	973662	0	0	0
T10	318154	0	0	0
T11	828883	0	0	0
T12	181235	43	0	0
T13	0	14	0	0
T14	0	28	0	0
T15	0	20	0	0
T16	0	23	0	0
T17	0	15	0	0
T18	0	10	0	0
T19	0	4	0	0
T20	0	17	0	0
T21	731186	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1481	0	0
T3	240873	6	0	0
T5	210956	0	0	0
T6	142269	0	0	0
T7	288148	0	0	0
T8	279411	0	0	0
T9	973662	0	0	0
T10	318154	0	0	0
T11	828883	0	0	0
T12	181235	38	0	0
T13	0	15	0	0
T14	0	34	0	0
T15	0	22	0	0
T16	0	25	0	0
T17	0	7	0	0
T18	0	12	0	0
T19	0	21	0	0
T20	0	19	0	0
T21	731186	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1635	0	0
T3	240873	1	0	0
T5	210956	0	0	0
T6	142269	0	0	0
T7	288148	0	0	0
T8	279411	0	0	0
T9	973662	0	0	0
T10	318154	0	0	0
T11	828883	0	0	0
T12	181235	29	0	0
T13	0	25	0	0
T14	0	32	0	0
T15	0	13	0	0
T16	0	26	0	0
T17	0	23	0	0
T18	0	20	0	0
T19	0	8	0	0
T20	0	23	0	0
T21	731186	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1777	0	0
T3	240873	50	0	0
T5	210956	0	0	0
T6	142269	0	0	0
T7	288148	0	0	0
T8	279411	0	0	0
T9	973662	0	0	0
T10	318154	0	0	0
T11	828883	0	0	0
T12	181235	49	0	0
T13	0	19	0	0
T14	0	38	0	0
T15	0	14	0	0
T16	0	18	0	0
T17	0	16	0	0
T18	0	15	0	0
T19	0	11	0	0
T20	0	29	0	0
T21	731186	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1715	0	0
T3	240873	25	0	0
T5	210956	0	0	0
T6	142269	0	0	0
T7	288148	0	0	0
T8	279411	0	0	0
T9	973662	0	0	0
T10	318154	0	0	0
T11	828883	0	0	0
T12	181235	31	0	0
T13	0	19	0	0
T14	0	31	0	0
T15	0	19	0	0
T16	0	19	0	0
T17	0	5	0	0
T18	0	23	0	0
T19	0	20	0	0
T20	0	17	0	0
T21	731186	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1736	0	0
T3	240873	31	0	0
T5	210956	0	0	0
T6	142269	0	0	0
T7	288148	0	0	0
T8	279411	0	0	0
T9	973662	0	0	0
T10	318154	0	0	0
T11	828883	0	0	0
T12	181235	28	0	0
T13	0	20	0	0
T14	0	30	0	0
T15	0	13	0	0
T16	0	23	0	0
T17	0	12	0	0
T18	0	10	0	0
T19	0	10	0	0
T20	0	21	0	0
T21	731186	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1330	0	0
T3	240873	13	0	0
T5	210956	0	0	0
T6	142269	0	0	0
T7	288148	0	0	0
T8	279411	0	0	0
T9	973662	0	0	0
T10	318154	0	0	0
T11	828883	0	0	0
T12	181235	30	0	0
T13	0	12	0	0
T14	0	18	0	0
T15	0	25	0	0
T16	0	32	0	0
T17	0	21	0	0
T18	0	14	0	0
T19	0	6	0	0
T20	0	31	0	0
T21	731186	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1313	0	0
T3	240873	19	0	0
T5	210956	0	0	0
T6	142269	0	0	0
T7	288148	0	0	0
T8	279411	0	0	0
T9	973662	0	0	0
T10	318154	0	0	0
T11	828883	0	0	0
T12	181235	31	0	0
T13	0	16	0	0
T14	0	46	0	0
T15	0	19	0	0
T16	0	25	0	0
T17	0	18	0	0
T18	0	18	0	0
T19	0	18	0	0
T20	0	8	0	0
T21	731186	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1858	0	0
T3	240873	33	0	0
T5	210956	0	0	0
T6	142269	0	0	0
T7	288148	0	0	0
T8	279411	0	0	0
T9	973662	0	0	0
T10	318154	0	0	0
T11	828883	0	0	0
T12	181235	30	0	0
T13	0	21	0	0
T14	0	21	0	0
T15	0	33	0	0
T16	0	22	0	0
T17	0	11	0	0
T18	0	16	0	0
T19	0	21	0	0
T20	0	14	0	0
T21	731186	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1317	0	0
T3	240873	17	0	0
T5	210956	0	0	0
T6	142269	0	0	0
T7	288148	0	0	0
T8	279411	0	0	0
T9	973662	0	0	0
T10	318154	0	0	0
T11	828883	0	0	0
T12	181235	30	0	0
T13	0	22	0	0
T14	0	30	0	0
T15	0	16	0	0
T16	0	26	0	0
T17	0	26	0	0
T18	0	28	0	0
T19	0	4	0	0
T20	0	19	0	0
T21	731186	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1368	0	0
T3	240873	11	0	0
T5	210956	0	0	0
T6	142269	0	0	0
T7	288148	0	0	0
T8	279411	0	0	0
T9	973662	0	0	0
T10	318154	0	0	0
T11	828883	0	0	0
T12	181235	40	0	0
T13	0	24	0	0
T14	0	23	0	0
T15	0	14	0	0
T16	0	26	0	0
T17	0	15	0	0
T18	0	17	0	0
T19	0	20	0	0
T20	0	18	0	0
T21	731186	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1254	0	0
T3	240873	19	0	0
T5	210956	0	0	0
T6	142269	0	0	0
T7	288148	0	0	0
T8	279411	0	0	0
T9	973662	0	0	0
T10	318154	0	0	0
T11	828883	0	0	0
T12	181235	45	0	0
T13	0	15	0	0
T14	0	34	0	0
T15	0	13	0	0
T16	0	10	0	0
T17	0	28	0	0
T18	0	13	0	0
T19	0	26	0	0
T20	0	12	0	0
T21	731186	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1158	0	0
T3	240873	11	0	0
T5	210956	0	0	0
T6	142269	0	0	0
T7	288148	0	0	0
T8	279411	0	0	0
T9	973662	0	0	0
T10	318154	0	0	0
T11	828883	0	0	0
T12	181235	28	0	0
T13	0	30	0	0
T14	0	47	0	0
T15	0	10	0	0
T16	0	13	0	0
T17	0	38	0	0
T18	0	28	0	0
T19	0	5	0	0
T20	0	16	0	0
T21	731186	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2227	0	0
T3	240873	20	0	0
T5	210956	0	0	0
T6	142269	0	0	0
T7	288148	0	0	0
T8	279411	0	0	0
T9	973662	0	0	0
T10	318154	0	0	0
T11	828883	0	0	0
T12	181235	29	0	0
T13	0	56	0	0
T14	0	66	0	0
T15	0	10	0	0
T16	0	29	0	0
T17	0	22	0	0
T18	0	32	0	0
T21	731186	0	0	0
T22	0	21	0	0
T23	0	28	0	0