Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1080665	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1058077

1

T1

59

T2

32

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1875214	1			T1	81		T3	1		T18	1
values[0x0]	131884	1			T1	33		T2	29		T3	1
values[0x1]	131644	1			T1	30		T2	32		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	865499	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1273243

1

T1

72

T2

34

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5918	1			T8	2		T10	9		T11	1
valid_sources[0x01]	6017	1			T10	11		T13	6		T14	26
valid_sources[0x02]	8862	1			T2	1		T8	1		T10	9
valid_sources[0x03]	8799	1			T2	1		T3	1		T10	6
valid_sources[0x04]	6239	1			T10	12		T13	3		T14	7
valid_sources[0x05]	10453	1			T10	13		T13	1		T14	7
valid_sources[0x06]	6506	1			T9	2		T10	11		T13	4
valid_sources[0x07]	6670	1			T10	9		T13	3		T15	15
valid_sources[0x08]	7226	1			T10	8		T13	7		T48	1
valid_sources[0x09]	6008	1			T8	3		T9	1		T10	10
valid_sources[0x0a]	6094	1			T8	5		T10	12		T30	5
valid_sources[0x0b]	6011	1			T8	3		T9	2		T10	9
valid_sources[0x0c]	12992	1			T10	14		T11	1		T13	1
valid_sources[0x0d]	5912	1			T8	2		T10	15		T11	1
valid_sources[0x0e]	5935	1			T8	1		T10	10		T13	2
valid_sources[0x0f]	14443	1			T3	1		T10	9		T11	1
valid_sources[0x10]	18887	1			T6	1		T9	1		T10	6
valid_sources[0x11]	5762	1			T8	3		T9	3		T10	4
valid_sources[0x12]	6294	1			T6	2		T10	10		T13	4
valid_sources[0x13]	11392	1			T2	1		T10	11		T11	1
valid_sources[0x14]	6094	1			T9	1		T10	13		T13	4
valid_sources[0x15]	5940	1			T8	3		T10	12		T13	12
valid_sources[0x16]	5795	1			T7	2		T8	1		T9	2
valid_sources[0x17]	7675	1			T2	1		T10	16		T13	3
valid_sources[0x18]	7075	1			T7	10		T10	11		T13	1
valid_sources[0x19]	10137	1			T8	2		T9	5		T10	14
valid_sources[0x1a]	6335	1			T10	13		T13	1		T14	16
valid_sources[0x1b]	8299	1			T9	2		T10	12		T11	1
valid_sources[0x1c]	6148	1			T8	3		T10	11		T13	1
valid_sources[0x1d]	11259	1			T6	1		T7	15		T10	12
valid_sources[0x1e]	10879	1			T2	1		T4	24		T8	2
valid_sources[0x1f]	8547	1			T2	1		T10	12		T13	2
valid_sources[0x20]	6547	1			T8	1		T9	1		T10	13
valid_sources[0x21]	10432	1			T8	1		T10	13		T13	2
valid_sources[0x22]	5975	1			T9	1		T10	11		T11	1
valid_sources[0x23]	5759	1			T10	7		T13	2		T14	10
valid_sources[0x24]	5902	1			T10	12		T13	1		T33	2
valid_sources[0x25]	5797	1			T6	1		T10	12		T13	2
valid_sources[0x26]	7248	1			T8	3		T9	1		T10	18
valid_sources[0x27]	6834	1			T10	12		T11	1		T13	2
valid_sources[0x28]	13194	1			T10	6		T13	1		T14	8
valid_sources[0x29]	7815	1			T7	15		T9	1		T10	6
valid_sources[0x2a]	6346	1			T10	5		T13	3		T48	1
valid_sources[0x2b]	10579	1			T8	10		T10	14		T13	2
valid_sources[0x2c]	6384	1			T6	1		T10	5		T13	1
valid_sources[0x2d]	5649	1			T10	10		T11	1		T30	2
valid_sources[0x2e]	10264	1			T19	7		T10	8		T30	1
valid_sources[0x2f]	8463	1			T2	1		T8	1		T9	4
valid_sources[0x30]	10295	1			T6	1		T10	13		T30	1
valid_sources[0x31]	7031	1			T2	1		T9	2		T10	19
valid_sources[0x32]	8860	1			T7	15		T9	1		T10	16
valid_sources[0x33]	5842	1			T8	2		T10	11		T13	7
valid_sources[0x34]	6052	1			T2	1		T9	4		T10	13
valid_sources[0x35]	6045	1			T9	6		T10	16		T13	3
valid_sources[0x36]	11461	1			T6	1		T8	4		T10	12
valid_sources[0x37]	6060	1			T10	9		T13	4		T14	17
valid_sources[0x38]	6078	1			T9	2		T10	14		T13	5
valid_sources[0x39]	6247	1			T2	1		T8	4		T10	9
valid_sources[0x3a]	10203	1			T10	8		T13	2		T48	1
valid_sources[0x3b]	9928	1			T6	1		T10	5		T48	1
valid_sources[0x3c]	6127	1			T7	2		T8	1		T9	1
valid_sources[0x3d]	5956	1			T8	1		T10	15		T13	1
valid_sources[0x3e]	5878	1			T4	23		T8	1		T9	2
valid_sources[0x3f]	6998	1			T8	1		T9	2		T10	8
valid_sources[0x40]	18750	1			T9	1		T10	12		T33	1
valid_sources[0x41]	12349	1			T7	3		T10	15		T13	5
valid_sources[0x42]	13992	1			T9	1		T10	9		T13	4
valid_sources[0x43]	5657	1			T10	18		T13	4		T48	1
valid_sources[0x44]	8743	1			T2	2		T6	1		T10	10
valid_sources[0x45]	8015	1			T10	15		T13	3		T14	8
valid_sources[0x46]	6215	1			T2	2		T10	12		T13	2
valid_sources[0x47]	6593	1			T10	5		T13	5		T33	2
valid_sources[0x48]	6176	1			T9	1		T10	7		T13	13
valid_sources[0x49]	6038	1			T20	3		T10	17		T13	5
valid_sources[0x4a]	5950	1			T2	1		T10	8		T30	3
valid_sources[0x4b]	5928	1			T18	1		T8	3		T10	16
valid_sources[0x4c]	14870	1			T2	3		T9	1		T10	12
valid_sources[0x4d]	6056	1			T10	12		T13	6		T14	5
valid_sources[0x4e]	6274	1			T7	52		T10	6		T13	7
valid_sources[0x4f]	8246	1			T8	1		T9	2		T10	10
valid_sources[0x50]	10228	1			T10	8		T48	1		T33	1
valid_sources[0x51]	10063	1			T2	1		T6	1		T9	2
valid_sources[0x52]	6179	1			T8	4		T10	12		T11	2
valid_sources[0x53]	10858	1			T6	1		T8	1		T10	16
valid_sources[0x54]	6017	1			T8	3		T9	1		T10	13
valid_sources[0x55]	5867	1			T1	144		T10	10		T14	10
valid_sources[0x56]	10500	1			T2	1		T9	5		T10	11
valid_sources[0x57]	6181	1			T8	4		T9	2		T10	9
valid_sources[0x58]	6214	1			T9	1		T10	9		T11	1
valid_sources[0x59]	6957	1			T10	9		T13	3		T14	7
valid_sources[0x5a]	6177	1			T7	8		T8	3		T10	10
valid_sources[0x5b]	10539	1			T8	1		T9	3		T10	8
valid_sources[0x5c]	8861	1			T2	1		T9	1		T10	11
valid_sources[0x5d]	6041	1			T10	6		T13	5		T33	1
valid_sources[0x5e]	10370	1			T8	1		T10	12		T13	5
valid_sources[0x5f]	5946	1			T7	76		T8	1		T9	2
valid_sources[0x60]	6147	1			T8	2		T9	1		T10	16
valid_sources[0x61]	7101	1			T8	1		T10	6		T13	1
valid_sources[0x62]	7031	1			T8	1		T9	1		T10	8
valid_sources[0x63]	7065	1			T8	2		T10	9		T13	14
valid_sources[0x64]	11369	1			T4	7		T7	17		T9	1
valid_sources[0x65]	10088	1			T7	116		T10	12		T13	14
valid_sources[0x66]	9957	1			T8	3		T10	10		T13	5
valid_sources[0x67]	7128	1			T7	12		T8	1		T9	3
valid_sources[0x68]	9359	1			T10	12		T13	1		T14	14
valid_sources[0x69]	6270	1			T10	8		T11	1		T48	3
valid_sources[0x6a]	10631	1			T8	2		T10	8		T30	1
valid_sources[0x6b]	5622	1			T2	1		T9	2		T10	19
valid_sources[0x6c]	6789	1			T8	1		T10	7		T11	1
valid_sources[0x6d]	5855	1			T8	1		T10	8		T11	1
valid_sources[0x6e]	9941	1			T10	14		T13	1		T33	1
valid_sources[0x6f]	5734	1			T8	5		T9	1		T10	19
valid_sources[0x70]	8206	1			T2	1		T4	29		T10	5
valid_sources[0x71]	6904	1			T10	6		T11	1		T13	5
valid_sources[0x72]	6459	1			T10	14		T13	2		T14	30
valid_sources[0x73]	7424	1			T2	2		T7	5		T8	2
valid_sources[0x74]	6127	1			T8	2		T10	11		T13	8
valid_sources[0x75]	7420	1			T10	10		T30	1		T13	2
valid_sources[0x76]	6085	1			T7	4		T10	12		T14	13
valid_sources[0x77]	10429	1			T2	1		T10	8		T13	3
valid_sources[0x78]	11016	1			T9	1		T10	9		T13	8
valid_sources[0x79]	6507	1			T9	3		T10	17		T13	1
valid_sources[0x7a]	10187	1			T9	1		T10	9		T13	2
valid_sources[0x7b]	8807	1			T8	1		T9	2		T10	5
valid_sources[0x7c]	6725	1			T2	1		T9	1		T10	6
valid_sources[0x7d]	5777	1			T2	3		T9	1		T10	12
valid_sources[0x7e]	6178	1			T10	15		T13	7		T48	1
valid_sources[0x7f]	15930	1			T10	9		T13	1		T14	19
valid_sources[0x80]	12916	1			T10	12		T11	1		T13	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

932909

1

T1

46

T18

1

T4

44

values[0x0]

all_enables

biggest_size

72633

1

T1

8

T2

16

T3

1

values[0x1]

all_enables

biggest_size

52535

1

T1

5

T2

16

T18

1