Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	26361	1			T5	8		T7	12		T10	11
auto[PWRUP]	99	1			T43	2		T44	3		T49	1
auto[ONEST_0]	48	1			T36	1		T47	1		T46	1
auto[ONEST_021]	16	1			T43	1		T47	1		T205	1
auto[ONEST_1]	67	1			T47	2		T44	3		T52	2
auto[ONEST_DONE]	5	1			T44	1		T54	1		T206	1
auto[LP_0]	110	1			T7	1		T43	3		T44	2
auto[LP_021]	22	1			T44	1		T45	1		T46	1
auto[LP_1]	112	1			T43	4		T47	1		T44	2
auto[LP_EVAL]	55	1			T36	1		T47	2		T46	1
auto[LP_SLP]	433	1			T35	1		T36	1		T43	5
auto[LP_PWRUP]	23	1			T49	1		T50	1		T207	1
auto[NP_0]	133	1			T43	1		T47	2		T44	3
auto[NP_021]	23	1			T182	1		T208	1		T209	2
auto[NP_1]	136	1			T43	5		T47	3		T44	3
auto[NP_EVAL]	35	1			T43	1		T44	1		T46	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

9

1

T51

1

T209

1

T210

1

min

25963

1

T5

8

T7

11

T10

11

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	25967	1			T5	8		T7	11		T10	11
pow[0x1]	4	1			T43	1		T94	2		T211	1
pow[0x2]	13	1			T43	1		T49	2		T45	1
pow[0x3]	26	1			T47	1		T50	2		T51	1
pow[0x4]	58	1			T45	1		T46	1		T205	2
pow[0x5]	89	1			T43	1		T47	1		T44	3
pow[0x6]	214	1			T36	1		T43	7		T47	2
pow[0x7]	418	1			T36	1		T43	8		T47	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

151

1

T36

1

T43

2

T47

1

min

25553

1

T5

8

T7

11

T10

11

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	25553	1			T5	8		T7	11		T10	11
pow[0x5]	2	1			T212	1		T213	1		-	-
pow[0x6]	1	1			T43	1		-	-		-	-
pow[0x7]	3	1			T44	1		T214	1		T215	1
pow[0x8]	4	1			T44	1		T53	1		T216	1
pow[0x9]	9	1			T46	1		T182	1		T217	2
pow[0xa]	13	1			T43	2		T54	1		T27	1
pow[0xb]	26	1			T205	1		T209	1		T32	2
pow[0xc]	59	1			T7	1		T43	3		T47	1
pow[0xd]	133	1			T43	2		T44	4		T45	1
pow[0xe]	228	1			T7	1		T43	2		T47	3
pow[0xf]	508	1			T35	1		T36	2		T43	7