Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	1989	1			T3	20		T7	11		T8	5
auto[PWRUP]	136	1			T35	1		T37	1		T44	1
auto[ONEST_0]	71	1			T43	1		T44	1		T49	1
auto[ONEST_021]	17	1			T7	1		T47	1		T207	1
auto[ONEST_1]	81	1			T35	1		T43	1		T47	2
auto[ONEST_DONE]	2	1			T210	1		T310	1		-	-
auto[LP_0]	87	1			T43	1		T49	1		T45	1
auto[LP_021]	31	1			T205	1		T182	3		T51	1
auto[LP_1]	111	1			T36	1		T47	3		T44	1
auto[LP_EVAL]	47	1			T36	1		T43	1		T47	1
auto[LP_SLP]	441	1			T7	1		T35	3		T36	2
auto[LP_PWRUP]	23	1			T50	1		T51	1		T207	1
auto[NP_0]	187	1			T7	1		T8	1		T35	2
auto[NP_021]	28	1			T21	2		T43	2		T52	1
auto[NP_1]	143	1			T7	2		T33	1		T35	1
auto[NP_EVAL]	17	1			T44	1		T38	2		T40	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

12

1

T352

1

T210

1

T94

1

min

1667

1

T3

20

T7

13

T8

6

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1677	1			T3	20		T7	14		T8	6
pow[0x1]	8	1			T35	1		T182	1		T209	1
pow[0x2]	15	1			T44	1		T182	1		T54	1
pow[0x3]	41	1			T35	1		T43	1		T44	1
pow[0x4]	45	1			T44	1		T49	1		T46	1
pow[0x5]	118	1			T43	3		T47	1		T49	1
pow[0x6]	229	1			T43	4		T47	3		T44	3
pow[0x7]	421	1			T36	1		T43	2		T47	9

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

167

1

T43

1

T47

1

T44

2

min

1207

1

T3

20

T7

11

T8

5

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1213	1			T3	20		T7	11		T8	5
pow[0x1]	7	1			T21	1		T274	1		T28	1
pow[0x2]	16	1			T43	1		T40	1		T24	1
pow[0x3]	24	1			T7	3		T35	1		T36	1
pow[0x4]	22	1			T8	1		T35	1		T44	1
pow[0x5]	2	1			T353	1		T215	1		-	-
pow[0x7]	3	1			T206	1		T354	1		T327	1
pow[0x8]	2	1			T355	1		T215	1		-	-
pow[0x9]	9	1			T207	1		T102	1		T356	2
pow[0xa]	21	1			T44	1		T45	1		T46	1
pow[0xb]	34	1			T47	1		T45	1		T50	1
pow[0xc]	65	1			T44	1		T49	1		T46	1
pow[0xd]	115	1			T43	3		T45	5		T205	1
pow[0xe]	208	1			T35	1		T43	2		T47	2
pow[0xf]	490	1			T35	1		T36	1		T43	9